SPRUJ79 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 â–º C29x SYSTEM RESOURCES
    1.     Technical Reference Manual Overview
  4. 2 F29x Processor
    1. 2.1 CPU Architecture
      1. 2.1.1 C29x Related Collateral
    2. 2.2 Lock and Commit Registers
    3. 2.3 C29x CPU Registers
      1. 2.3.1 C29CPU Base Address Table
      2. 2.3.2 C29_RTINT_STACK Registers
      3. 2.3.3 C29_SECCALL_STACK Registers
      4. 2.3.4 C29_SECURE_REGS Registers
      5. 2.3.5 C29_DIAG_REGS Registers
      6. 2.3.6 C29_SELFTEST_REGS Registers
  5. 3 System Control and Interrupts
    1. 3.1  C29x System Control Introduction
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
      2. 3.2.2 Device Configuration Registers
    3. 3.3  Resets
      1. 3.3.1 Reset Sources
      2. 3.3.2 External Reset (XRS)
      3. 3.3.3 Simulate External Reset
      4. 3.3.4 Power-On Reset (POR)
      5. 3.3.5 Debugger Reset (SYSRS)
      6. 3.3.6 Watchdog Reset (WDRS)
      7. 3.3.7 ESM NMI Watchdog Reset (NMIWDRS)
      8. 3.3.8 EtherCAT Slave Controller (ESC) Module Reset Output
    4. 3.4  Safety Features
      1. 3.4.1 Write Protection on Registers
        1. 3.4.1.1 LOCK Protection on System Configuration Registers
        2. 3.4.1.2 EALLOW Protection
      2. 3.4.2 PIPE Vector Address Validity Check
      3. 3.4.3 NMIWDs
      4. 3.4.4 System Control Registers Parity Protection
      5. 3.4.5 ECC Enabled RAMs, Shared RAMs Protection
      6. 3.4.6 ECC Enabled Flash Memory
      7. 3.4.7 ERRORSTS Pin
    5. 3.5  Clocking
      1. 3.5.1 Clock Sources
        1. 3.5.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.5.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.5.1.3 External Oscillator (XTAL)
        4. 3.5.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.5.2 Derived Clocks
        1. 3.5.2.1 Oscillator Clock (OSCCLK)
        2. 3.5.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.5.3 Device Clock Domains
        1. 3.5.3.1 System Clock (PLLSYSCLK)
        2. 3.5.3.2 CPU Clock (CPUCLK)
        3. 3.5.3.3 Peripheral Clock (PERx.SYSCLK)
        4. 3.5.3.4 MCAN Bit Clock
        5. 3.5.3.5 CPU Timer2 Clock (TIMER2CLK)
      4. 3.5.4 External Clock Output (XCLKOUT)
      5. 3.5.5 Clock Connectivity
      6. 3.5.6 Using an External Crystal or Resonator
        1. 3.5.6.1 X1/X2 Precondition Circuit
      7. 3.5.7 PLL
        1. 3.5.7.1 System Clock Setup
        2. 3.5.7.2 SYS PLL Bypass
      8. 3.5.8 Clock (OSCCLK) Failure Detection
        1. 3.5.8.1 Missing Clock Detection Logic
        2. 3.5.8.2 Dual Clock Comparator (DCC)
    6. 3.6  Bus Architecture
      1. 3.6.1 Safe Interconnect
        1. 3.6.1.1 Safe Interconnect for Read Operation
        2. 3.6.1.2 Safe Interconnect for Write Operation
      2. 3.6.2 Peripheral Access Configuration using FRAMESEL
      3. 3.6.3 Bus Arbitration
    7. 3.7  32-Bit CPU Timers 0/1/2
    8. 3.8  Watchdog Timers
      1. 3.8.1 Servicing the Watchdog Timer
      2. 3.8.2 Minimum Window Check
      3. 3.8.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.8.4 Watchdog Operation in Low-Power Modes
      5. 3.8.5 Emulation Considerations
    9. 3.9  Low-Power Modes
      1. 3.9.1 IDLE
      2. 3.9.2 STANDBY
    10. 3.10 Memory Subsystem (MEMSS)
      1. 3.10.1 Introduction
      2. 3.10.2 Features
      3. 3.10.3 Configuration Bits
        1. 3.10.3.1 Memory Initialization
      4. 3.10.4 RAM
        1. 3.10.4.1  MEMSS Architecture
        2. 3.10.4.2  RAM Memory Controller Overview
        3. 3.10.4.3  Memory Controllers
          1. 3.10.4.3.1 128-Bit LPx and CPx Memory Controller
          2. 3.10.4.3.2 64-Bit LDx and CDx Memory Controller
          3. 3.10.4.3.3 M0 Memory Controller
        4. 3.10.4.4  RTDMA Burst Support
        5. 3.10.4.5  Atomic Memory Operations
        6. 3.10.4.6  RAM ECC
        7. 3.10.4.7  Read-Modify-Write Operations
        8. 3.10.4.8  Dataline Buffer
        9. 3.10.4.9  HSM Sync Bridge
        10. 3.10.4.10 Access Bridges
          1. 3.10.4.10.1 Debug Access Bridge
          2. 3.10.4.10.2 Global Access Bridge
          3. 3.10.4.10.3 Program Access Bridge
      5. 3.10.5 ROM
        1. 3.10.5.1 ROM Dataline Buffer
        2. 3.10.5.2 ROM Prefetch
      6. 3.10.6 Arbitration
      7. 3.10.7 Test Modes
      8. 3.10.8 Emulation Mode
    11. 3.11 System Control Register Configuration Restrictions
    12. 3.12 Software
      1. 3.12.1  SYSCTL Registers to Driverlib Functions
      2. 3.12.2  MEMSS Registers to Driverlib Functions
      3. 3.12.3  CPU Registers to Driverlib Functions
      4. 3.12.4  WD Registers to Driverlib Functions
      5. 3.12.5  CPUTIMER Registers to Driverlib Functions
      6. 3.12.6  XINT Registers to Driverlib Functions
      7. 3.12.7  LPOST Registers to Driverlib Functions
      8. 3.12.8  SYSCTL Examples
        1. 3.12.8.1 Missing clock detection (MCD) - SINGLE_CORE
        2. 3.12.8.2 XCLKOUT (External Clock Output) Configuration - SINGLE_CORE
      9. 3.12.9  TIMER Examples
        1. 3.12.9.1 Timer Academy Lab - SINGLE_CORE
        2. 3.12.9.2 CPU Timers - SINGLE_CORE
        3. 3.12.9.3 CPU Timers - SINGLE_CORE
      10. 3.12.10 WATCHDOG Examples
        1. 3.12.10.1 Watchdog - SINGLE_CORE
      11. 3.12.11 LPM Examples
        1. 3.12.11.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO - SINGLE_CORE
        2. 3.12.11.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog - SINGLE_CORE
        3. 3.12.11.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO - SINGLE_CORE
        4. 3.12.11.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog - SINGLE_CORE
    13. 3.13 SYSCTRL Registers
      1. 3.13.1  SYSCTRL Base Address Table
      2. 3.13.2  DEV_CFG_REGS Registers
      3. 3.13.3  MEMSS_L_CONFIG_REGS Registers
      4. 3.13.4  MEMSS_C_CONFIG_REGS Registers
      5. 3.13.5  MEMSS_M_CONFIG_REGS Registers
      6. 3.13.6  MEMSS_MISCI_REGS Registers
      7. 3.13.7  CPU_SYS_REGS Registers
      8. 3.13.8  CPU_PER_CFG_REGS Registers
      9. 3.13.9  WD_REGS Registers
      10. 3.13.10 CPUTIMER_REGS Registers
      11. 3.13.11 XINT_REGS Registers
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Device Boot Flow
      2. 4.5.2 CPU1 Boot Flow
      3. 4.5.3 Emulation Boot Flow
      4. 4.5.4 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 MPOST and LPOST Configurations
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Memory Maps
        1. 4.7.4.1 Boot ROM Memory-Maps
        2. 4.7.4.2 Reserved RAM Memory-Maps
      5. 4.7.5  ROM Structure and Status Information
      6. 4.7.6  Boot Modes and Loaders
        1. 4.7.6.1 Boot Modes
          1. 4.7.6.1.1 Flash Boot
          2. 4.7.6.1.2 RAM Boot
          3. 4.7.6.1.3 Wait Boot
        2. 4.7.6.2 Bootloaders
          1. 4.7.6.2.1 SPI Boot Mode
          2. 4.7.6.2.2 I2C Boot Mode
          3. 4.7.6.2.3 Parallel Boot Mode
          4. 4.7.6.2.4 CAN Boot Mode
          5. 4.7.6.2.5 CAN-FD Boot Mode
          6. 4.7.6.2.6 UART Boot Mode
      7. 4.7.7  GPIO Assignments
      8. 4.7.8  HSM and C29 ROM Task Ownership and Interactions
        1. 4.7.8.1 Application Authentication by HSM
      9. 4.7.9  Boot Status Information
        1. 4.7.9.1 Booting Status
      10. 4.7.10 BootROM Timing
    8. 4.8 Software
      1. 4.8.1 BOOT Examples
  7. 5 Lockstep Compare Module (LCM)
    1. 5.1 Introduction
      1. 5.1.1 Features
      2. 5.1.2 Block Diagram
      3. 5.1.3 Lockstep Compare Modules
    2. 5.2 Enabling LCM Comparators
    3. 5.3 LCM Redundant Module Configuration
    4. 5.4 LCM Error Handling
    5. 5.5 Debug Mode with LCM
    6. 5.6 Register Parity Error Protection
    7. 5.7 Functional Logic
      1. 5.7.1 Comparator Logic
      2. 5.7.2 Self-Test Logic
        1. 5.7.2.1 Match Test Mode
        2. 5.7.2.2 Mismatch Test Mode
      3. 5.7.3 Error Injection Tests
        1. 5.7.3.1 Comparator Error Force Test
        2. 5.7.3.2 Register Parity Error Test
    8. 5.8 Software
      1. 5.8.1 LCM Registers to Driverlib Functions
    9. 5.9 LCM Registers
      1. 5.9.1 LCM Base Address Table
      2. 5.9.2 LCM_REGS Registers
  8. 6 Peripheral Interrupt Priority and Expansion (PIPE)
    1. 6.1 Introduction
      1. 6.1.1 Features
      2. 6.1.2 Interrupt Concepts
      3. 6.1.3 PIPE Related Collateral
    2. 6.2 Interrupt Architecture
      1. 6.2.1 Dynamic Priority Arbitration Block
      2. 6.2.2 Post Processing Block
      3. 6.2.3 Memory-Mapped Registers
    3. 6.3 Interrupt Propagation
    4. 6.4 Configuring Interrupts
      1. 6.4.1 Enabling and Disabling Interrupts
      2. 6.4.2 Prioritization
        1. 6.4.2.1 User-Configured Interrupt Priority
        2. 6.4.2.2 Index-Based Fixed Interrupt Priority
      3. 6.4.3 Nesting and Priority Grouping
      4. 6.4.4 Stack Protection
      5. 6.4.5 Context
    5. 6.5 Safety and Security
      1. 6.5.1 Access Control
      2. 6.5.2 PIPE Errors
      3. 6.5.3 Register Data Integrity and Safety
      4. 6.5.4 Self-Test and Diagnostics
    6. 6.6 Software
      1. 6.6.1 PIPE Registers to Driverlib Functions
      2. 6.6.2 INTERRUPT Examples
        1. 6.6.2.1 RTINT vs INT Latency example - SINGLE_CORE
        2. 6.6.2.2 INT and RTINT Nesting Example - SINGLE_CORE
    7. 6.7 PIPE Registers
      1. 6.7.1 PIPE Base Address Table
      2. 6.7.2 PIPE_REGS Registers
  9. 7  Error Signaling Module (ESM_C29)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 ESM Related Collateral
    2. 7.2 ESM Subsystem
      1. 7.2.1 System ESM
        1. 7.2.1.1 Error Pin Monitor Event
      2. 7.2.2 Safety Aggregator
        1. 7.2.2.1 EDC Controller Interface Description
          1. 7.2.2.1.1 EDC_REGS Registers
        2. 7.2.2.2 Read Operation on EDC Controller
        3. 7.2.2.3 Write Operation on EDC Controller
        4. 7.2.2.4 Safety Aggregator Error Injection
      3. 7.2.3 ESM Subsystem Integration View
    3. 7.3 ESM Functional Description
      1. 7.3.1 Error Event Inputs
      2. 7.3.2 Error Interrupt Outputs
        1. 7.3.2.1 High Priority Watchdog
        2. 7.3.2.2 Critical Priority Interrupt Output
      3. 7.3.3 Error Pin Output (ERR_O/ERRORSTS)
        1. 7.3.3.1 Minimum Time Interval
        2. 7.3.3.2 PWM Mode
      4. 7.3.4 Reset Type Information for ESM Registers
      5. 7.3.5 Clock Stop
      6. 7.3.6 Commit/Lock for MMRs
      7. 7.3.7 Safety Protection for MMRs
      8. 7.3.8 Register Configuration Tieoffs
        1. 7.3.8.1 Group0 High Priority Tieoff
        2. 7.3.8.2 High Priority Watchdog Enable Tieoff
    4. 7.4 ESM Configuration Guide
    5. 7.5 Interrupt Condition Control and Handling
      1. 7.5.1 ESM Low Priority Error Interrupt
      2. 7.5.2 ESM High Priority Error Interrupt
      3. 7.5.3 Critical Priority Error Interrupt
      4. 7.5.4 High Priority Watchdog Interrupt
      5. 7.5.5 Safety Aggregator Interrupt Control and Handling
    6. 7.6 Software
      1. 7.6.1 ESM_CPU Registers to Driverlib Functions
      2. 7.6.2 ESM_SYS Registers to Driverlib Functions
      3. 7.6.3 ESM_SAFETY_AGGREGATOR Registers to Driverlib Functions
      4. 7.6.4 ESM Examples
        1. 7.6.4.1 ESM Multicore Example (CPU1,CPU3) - MULTI_CORE
        2. 7.6.4.2 ESM Multicore Example (CPU1,CPU3) - MULTI_CORE
        3. 7.6.4.3 ESM - SINGLE_CORE
        4. 7.6.4.4 ESM - SINGLE_CORE
    7. 7.7 ESM Registers
      1. 7.7.1 ESM Base Address Table
      2. 7.7.2 ESM_CPU_REGS Registers
      3. 7.7.3 ESM_SYSTEM_REGS Registers
      4. 7.7.4 ESM_SAFETYAGG_REGS Registers
  10. 8  Error Aggregator
    1. 8.1 Introduction
    2. 8.2 Error Aggregator Modules
    3. 8.3 Error Propagation Path from Source to CPU
    4. 8.4 Error Aggregator Interface
      1. 8.4.1 Functional Description
    5. 8.5 Error Condition Handling User Guide
    6. 8.6 Error Type Information
    7. 8.7 Error Sources Information
    8. 8.8 Software
      1. 8.8.1 ERROR_AGGREGATOR Registers to Driverlib Functions
    9. 8.9 ERRORAGGREGATOR Registers
      1. 8.9.1 ERRORAGGREGATOR Base Address Table
      2. 8.9.2 HSM_ERROR_AGGREGATOR_CONFIG_REGS Registers
      3. 8.9.3 ERROR_AGGREGATOR_CONFIG_REGS Registers
  11. 9 Flash Module
    1. 9.1 Introduction to Flash Memory
      1. 9.1.1 FLASH Related Collateral
      2. 9.1.2 Features
      3. 9.1.3 Flash Tools
      4. 9.1.4 Block Diagram
    2. 9.2 Flash Subsystem Overview
    3. 9.3 Flash Banks and Pumps
    4. 9.4 Flash Read Interfaces
      1. 9.4.1 Bank Modes and Swapping
      2. 9.4.2 Flash Wait States
      3. 9.4.3 Buffer and Cache Mechanisms
        1. 9.4.3.1 Prefetch Mechanism and Block Cache
        2. 9.4.3.2 Data Line Buffer
        3. 9.4.3.3 Sequential Data Pre-read Mode
      4. 9.4.4 Flash Read Arbitration
      5. 9.4.5 Error Correction Code (ECC) Protection
      6. 9.4.6 Procedure to Change Flash Read Interface Registers
    5. 9.5 Flash Erase and Program
      1. 9.5.1 Flash Semaphore and Update Protection
      2. 9.5.2 Erase
      3. 9.5.3 Program
    6. 9.6 Migrating an Application from RAM to Flash
    7. 9.7 Flash Registers
      1. 9.7.1 FLASH Base Address Table
      2. 9.7.2 FLASH_CMD_REGS_FLC1 Registers
      3. 9.7.3 FLASH_CMD_REGS_FLC2 Registers
      4. 9.7.4 FRI_CTRL_REGS Registers
  12. 10Safety and Security Unit (SSU)
    1. 10.1  Introduction
      1. 10.1.1 SSU Related Collateral
      2. 10.1.2 Block Diagram
      3. 10.1.3 System SSU Configuration Example
    2. 10.2  Access Protection Ranges
      1. 10.2.1 Access Protection Inheritance
    3. 10.3  LINKs
    4. 10.4  STACKs
    5. 10.5  ZONEs
    6. 10.6  SSU-CPU Interface
      1. 10.6.1 SSU Operation in Lockstep Mode
    7. 10.7  SSU Operation Modes
    8. 10.8  Security Configuration and Flash Management
      1. 10.8.1 BANKMGMT Sectors
      2. 10.8.2 SECCFG Sectors
      3. 10.8.3 SECCFG Sector Address Mapping
      4. 10.8.4 SECCFG Sector Memory Map
      5. 10.8.5 SECCFG CRC
    9. 10.9  Flash Write/Erase Access Control
      1. 10.9.1 Permanent Flash Lock (Write/Erase Protection)
      2. 10.9.2 Updating Flash MAIN Sectors
      3. 10.9.3 Firmware-Over-The-Air Updates (FOTA)
      4. 10.9.4 Updating Flash SECCFG Sectors
      5. 10.9.5 Reading Flash SECCFG Sectors
    10. 10.10 RAMOPEN Feature
    11. 10.11 Debug Authorization
      1. 10.11.1 Global CPU Debug Enable
      2. 10.11.2 ZONE Debug
      3. 10.11.3 Authentication for Debug Access
        1. 10.11.3.1 Password-based Authentication
        2. 10.11.3.2 CPU-based Authentication
    12. 10.12 Hardcoded Protections
    13. 10.13 SSU Register Access Permissions
      1. 10.13.1 Permissions for SSU General Control Registers
      2. 10.13.2 Permissions for SSU CPU1 Configuration Registers
      3. 10.13.3 Permissions for SSU CPU2+ Configuration Registers
      4. 10.13.4 Permissions for CPU1 Access Protection Registers
      5. 10.13.5 Permissions for CPU2+ Access Protection Registers
    14. 10.14 SSU Fault Signals
    15. 10.15 Software
      1. 10.15.1 SSU Registers to Driverlib Functions
    16. 10.16 SSU Registers
      1. 10.16.1 SSU Base Address Table
      2. 10.16.2 SSU_GEN_REGS Registers
      3. 10.16.3 SSU_CPU1_CFG_REGS Registers
      4. 10.16.4 SSU_CPU2_CFG_REGS Registers
      5. 10.16.5 SSU_CPU3_CFG_REGS Registers
      6. 10.16.6 SSU_CPU1_AP_REGS Registers
      7. 10.16.7 SSU_CPU2_AP_REGS Registers
      8. 10.16.8 SSU_CPU3_AP_REGS Registers
  13. 11Configurable Logic Block (CLB)
    1. 11.1  Introduction
      1. 11.1.1 CLB Related Collateral
    2. 11.2  Description
      1. 11.2.1 CLB Clock
    3. 11.3  CLB Input/Output Connection
      1. 11.3.1 Overview
      2. 11.3.2 CLB Input Selection
      3. 11.3.3 CLB Output Selection
      4. 11.3.4 CLB Output Signal Multiplexer
    4. 11.4  CLB Tile
      1. 11.4.1 Static Switch Block
      2. 11.4.2 Counter Block
        1. 11.4.2.1 Counter Description
        2. 11.4.2.2 Counter Operation
        3. 11.4.2.3 Serializer Mode
        4. 11.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 11.4.3 FSM Block
      4. 11.4.4 LUT4 Block
      5. 11.4.5 Output LUT Block
      6. 11.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 11.4.7 High Level Controller (HLC)
        1. 11.4.7.1 High Level Controller Events
        2. 11.4.7.2 High Level Controller Instructions
        3. 11.4.7.3 <Src> and <Dest>
        4. 11.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 11.5  CPU Interface
      1. 11.5.1 Register Description
      2. 11.5.2 Non-Memory Mapped Registers
    6. 11.6  RTDMA Access
    7. 11.7  CLB Data Export Through SPI RX Buffer
    8. 11.8  CLB Pipeline Mode
    9. 11.9  Software
      1. 11.9.1 CLB Registers to Driverlib Functions
      2. 11.9.2 CLB Examples
    10. 11.10 CLB Registers
      1. 11.10.1 CLB Base Address Table
      2. 11.10.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 11.10.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 11.10.4 CLB_DATA_EXCHANGE_REGS Registers
  14. 12Dual-Clock Comparator (DCC)
    1. 12.1 Introduction
      1. 12.1.1 Features
      2. 12.1.2 Block Diagram
    2. 12.2 Module Operation
      1. 12.2.1 Configuring DCC Counters
      2. 12.2.2 Single-Shot Measurement Mode
      3. 12.2.3 Continuous Monitoring Mode
      4. 12.2.4 Error Conditions
    3. 12.3 Interrupts
    4. 12.4 Software
      1. 12.4.1 DCC Registers to Driverlib Functions
      2. 12.4.2 DCC Examples
        1. 12.4.2.1 DCC Single shot Clock verification - SINGLE_CORE
        2. 12.4.2.2 DCC Single shot Clock measurement - SINGLE_CORE
        3. 12.4.2.3 DCC Continuous clock monitoring - SINGLE_CORE
    5. 12.5 DCC Registers
      1. 12.5.1 DCC Base Address Table
      2. 12.5.2 DCC_REGS Registers
  15. 13Real-Time Direct Memory Access (RTDMA)
    1. 13.1  Introduction
      1. 13.1.1 Features
      2. 13.1.2 RTDMA Related Collateral
      3. 13.1.3 Block Diagram
    2. 13.2  RTDMA Trigger Source Options
    3. 13.3  RTDMA Bus
    4. 13.4  Address Pointer and Transfer Control
    5. 13.5  Pipeline Timing and Throughput
    6. 13.6  Channel Priority
      1. 13.6.1 Round-Robin Mode
      2. 13.6.2 Software Configurable Priority of Channels
    7. 13.7  Overrun Detection Feature
    8. 13.8  Burst Mode
    9. 13.9  Safety and Security
      1. 13.9.1 Safety
        1. 13.9.1.1 Lockstep Mode
        2. 13.9.1.2 Memory Protection Unit (MPU)
          1. 13.9.1.2.1 MPU Errors
      2. 13.9.2 Security
      3. 13.9.3 RTDMA Errors
      4. 13.9.4 Self-Test and Diagnostics
    10. 13.10 Software
      1. 13.10.1 RTDMA Registers to Driverlib Functions
      2. 13.10.2 RTDMA Examples
        1. 13.10.2.1 RTDMA Academy Lab - SINGLE_CORE
        2. 13.10.2.2 RTDMA Transfer - SINGLE_CORE
        3. 13.10.2.3 RTDMA Transfer with MPU - SINGLE_CORE
    11. 13.11 RTDMA Registers
      1. 13.11.1 RTDMA Base Address Table
      2. 13.11.2 RTDMA_REGS Registers
      3. 13.11.3 RTDMA_DIAG_REGS Registers
      4. 13.11.4 RTDMA_SELFTEST_REGS Registers
      5. 13.11.5 RTDMA_MPU_REGS Registers
      6. 13.11.6 RTDMA_CH_REGS Registers
  16. 14External Memory Interface (EMIF)
    1. 14.1 Introduction
      1. 14.1.1 Purpose of the Peripheral
      2. 14.1.2 Features
        1. 14.1.2.1 Asynchronous Memory Support
        2. 14.1.2.2 Synchronous DRAM Memory Support
      3. 14.1.3 Functional Block Diagram
      4. 14.1.4 Configuring Device Pins
    2. 14.2 EMIF Module Architecture
      1. 14.2.1  EMIF Clock Control
      2. 14.2.2  EMIF Requests
      3. 14.2.3  EMIF Signal Descriptions
      4. 14.2.4  EMIF Signal Multiplexing Control
      5. 14.2.5  SDRAM Controller and Interface
        1. 14.2.5.1  SDRAM Commands
        2. 14.2.5.2  Interfacing to SDRAM
        3. 14.2.5.3  SDRAM Configuration Registers
        4. 14.2.5.4  SDRAM Auto-Initialization Sequence
        5. 14.2.5.5  SDRAM Configuration Procedure
        6. 14.2.5.6  EMIF Refresh Controller
          1. 14.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 14.2.5.7  Self-Refresh Mode
        8. 14.2.5.8  Power-Down Mode
        9. 14.2.5.9  SDRAM Read Operation
        10. 14.2.5.10 SDRAM Write Operations
        11. 14.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 14.2.6  Asynchronous Controller and Interface
        1. 14.2.6.1 Interfacing to Asynchronous Memory
        2. 14.2.6.2 Accessing Larger Asynchronous Memories
        3. 14.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 14.2.6.4 Read and Write Operations in Normal Mode
          1. 14.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 14.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 14.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 14.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 14.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 14.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 14.2.7  Data Bus Parking
      8. 14.2.8  Reset and Initialization Considerations
      9. 14.2.9  Interrupt Support
        1. 14.2.9.1 Interrupt Events
      10. 14.2.10 RTDMA Event Support
      11. 14.2.11 EMIF Signal Multiplexing
      12. 14.2.12 Memory Map
      13. 14.2.13 Priority and Arbitration
      14. 14.2.14 System Considerations
        1. 14.2.14.1 Asynchronous Request Times
      15. 14.2.15 Power Management
        1. 14.2.15.1 Power Management Using Self-Refresh Mode
        2. 14.2.15.2 Power Management Using Power Down Mode
      16. 14.2.16 Emulation Considerations
    3. 14.3 EMIF Subsystem (EMIFSS)
      1. 14.3.1 Burst Support
      2. 14.3.2 EMIFSS Performance Improvement
      3. 14.3.3 Buffer Module
        1. 14.3.3.1 CPU Write FIFO
      4. 14.3.4 Emulation Mode
    4. 14.4 Example Configuration
      1. 14.4.1 Hardware Interface
      2. 14.4.2 Software Configuration
        1. 14.4.2.1 Configuring the SDRAM Interface
          1. 14.4.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 14.4.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 14.4.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 14.4.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 14.4.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 14.4.2.2 Configuring the Flash Interface
          1. 14.4.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    5. 14.5 Software
      1. 14.5.1 EMIF Registers to Driverlib Functions
      2. 14.5.2 EMIF Examples
    6. 14.6 EMIF Registers
      1. 14.6.1 EMIF Base Address Table
      2. 14.6.2 EMIF_REGS Registers
  17. 15General-Purpose Input/Output (GPIO)
    1. 15.1  Introduction
      1. 15.1.1 GPIO Related Collateral
    2. 15.2  Configuration Overview
    3. 15.3  Digital Inputs on ADC Pins (AIOs)
    4. 15.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 15.5  Digital General-Purpose I/O Control
    6. 15.6  Input Qualification
      1. 15.6.1 No Synchronization (Asynchronous Input)
      2. 15.6.2 Synchronization to SYSCLKOUT Only
      3. 15.6.3 Qualification Using a Sampling Window
    7. 15.7  PMBUS and I2C Signals
    8. 15.8  GPIO and Peripheral Muxing
      1. 15.8.1 GPIO Muxing
      2. 15.8.2 Peripheral Muxing
    9. 15.9  Internal Pullup Configuration Requirements
    10. 15.10 Software
      1. 15.10.1 GPIO Registers to Driverlib Functions
      2. 15.10.2 GPIO Examples
        1. 15.10.2.1 Device GPIO Toggle - SINGLE_CORE
        2. 15.10.2.2 XINT/XBAR example - SINGLE_CORE
      3. 15.10.3 LED Examples
        1. 15.10.3.1 LED Blinky Example - MULTI_CORE
        2. 15.10.3.2 LED Blinky Example (CPU1,CPU3) - MULTI_CORE
        3. 15.10.3.3 LED Blinky example - SINGLE_CORE
        4. 15.10.3.4 LED Blinky Example (CPU1|CPU2|CPU3) - MULTI_CORE
        5. 15.10.3.5 LED Blinky Example (CPU2) - MULTI_CORE
        6. 15.10.3.6 LED Blinky Example (CPU3) - MULTI_CORE
    11. 15.11 GPIO Registers
      1. 15.11.1 GPIO Base Address Table
      2. 15.11.2 GPIO_CTRL_REGS Registers
      3. 15.11.3 GPIO_DATA_REGS Registers
      4. 15.11.4 GPIO_DATA_READ_REGS Registers
  18. 16Interprocessor Communication (IPC)
    1. 16.1 Introduction
    2. 16.2 IPC Flags and Interrupts
    3. 16.3 IPC Command Registers
    4. 16.4 Free-Running Counter
    5. 16.5 IPC Communication Protocol
    6. 16.6 Software
      1. 16.6.1 IPC Registers to Driverlib Functions
      2. 16.6.2 IPC Examples
        1. 16.6.2.1 IPC basic message passing example with interrupt - MULTI_CORE
        2. 16.6.2.2 IPC basic message passing example with interrupt - MULTI_CORE
        3. 16.6.2.3 IPC basic message passing example with interrupt - MULTI_CORE
        4. 16.6.2.4 IPC basic message passing example with interrupt - MULTI_CORE
    7. 16.7 IPC Registers
      1. 16.7.1 IPC Base Address Table
      2. 16.7.2 IPC_COUNTER_REGS Registers
      3. 16.7.3 CPU1_IPC_SEND_REGS Registers
      4. 16.7.4 CPU2_IPC_SEND_REGS Registers
      5. 16.7.5 CPU3_IPC_SEND_REGS Registers
      6. 16.7.6 CPU1_IPC_RCV_REGS Registers
      7. 16.7.7 CPU2_IPC_RCV_REGS Registers
      8. 16.7.8 CPU3_IPC_RCV_REGS Registers
  19. 17Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 17.1 Introduction
    2. 17.2 Enhanced Bus Comparator Unit
      1. 17.2.1 Enhanced Bus Comparator Unit Operations
      2. 17.2.2 Stack Qualification
      3. 17.2.3 Event Masking and Exporting
    3. 17.3 System Event Counter Unit
      1. 17.3.1 System Event Counter Modes
        1. 17.3.1.1 Counting Active Levels Versus Edges
        2. 17.3.1.2 Max and Min Mode
        3. 17.3.1.3 Cumulative Mode
        4. 17.3.1.4 Input Signal Selection
      2. 17.3.2 Reset on Event
      3. 17.3.3 Operation Conditions
    4. 17.4 Program Counter Trace
      1. 17.4.1 Functional Block Diagram
      2. 17.4.2 Trace Qualification Modes
        1. 17.4.2.1 Trace Input Signal Conditioning
      3. 17.4.3 Trace Memory
      4. 17.4.4 PC Trace Software Operation
      5. 17.4.5 Trace Operation in Debug Mode
    5. 17.5 ERAD Ownership, Initialization, and Reset
      1. 17.5.1 Feature Level Ownership
      2. 17.5.2 Feature Access Security Mechanism
      3. 17.5.3 PC Trace Access Security Mechanism
    6. 17.6 ERAD Programming Sequence
      1. 17.6.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 17.6.2 Timer and Counter Programming Sequence
    7. 17.7 Software
      1. 17.7.1 ERAD Registers to Driverlib Functions
    8. 17.8 ERAD Registers
      1. 17.8.1 ERAD Base Address Table
        1. 17.8.1.1 ERAD_REGS Registers
  20. 18Data Logger and Trace (DLT)
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 DLT Related Collateral
      3. 18.1.3 Interfaces
        1. 18.1.3.1 Block Diagram
    2. 18.2 Functional Overview
      1. 18.2.1 DLT Configuration
        1. 18.2.1.1 LINK Filter
        2. 18.2.1.2 TAG Filter
        3. 18.2.1.3 ERAD Event Trigger
        4. 18.2.1.4 Concurrent FILTERING modes
      2. 18.2.2 Time-stamping
      3. 18.2.3 FIFO Construction
        1. 18.2.3.1 FIFO Interrupt
    3. 18.3 Software
      1. 18.3.1 DLT Registers to Driverlib Functions
      2. 18.3.2 DLT Examples
        1. 18.3.2.1 DLT TAG filter example - SINGLE_CORE
        2. 18.3.2.2 DLT TAG filter example - SINGLE_CORE
        3. 18.3.2.3 DLT ERAD filter example - SINGLE_CORE
    4. 18.4 DLT Registers
      1. 18.4.1 DLT Base Address Table
      2. 18.4.2 DLT_CORE_REGS Registers
      3. 18.4.3 DLT_FIFO_REGS Registers
  21. 19Waveform Analyzer Diagnostic (WADI)
    1. 19.1 WADI Overview
      1. 19.1.1 Features
      2. 19.1.2 WADI Related Collateral
      3. 19.1.3 Block Diagram
      4. 19.1.4 Description
    2. 19.2 Signal and Trigger Input Configuration
      1. 19.2.1 SIG1 and SIG2 Configuration
      2. 19.2.2 Trigger 1 and Trigger 2
    3. 19.3 WADI Block
      1. 19.3.1 Overview
      2. 19.3.2 Counters
      3. 19.3.3 Pulse Width
        1. 19.3.3.1 Pulse Width Single Measurement
        2. 19.3.3.2 Pulse Width Aggregation
        3. 19.3.3.3 Pulse Width Average and Peak
      4. 19.3.4 Edge Count
        1. 19.3.4.1 Edge Count with Fixed Window
        2. 19.3.4.2 Edge Count with Moving Window
      5. 19.3.5 Signal1 to Signal2 Comparison
      6. 19.3.6 Dead Band and Phase
      7. 19.3.7 Simultaneous Measurement
    4. 19.4 Safe State Sequencer (SSS)
      1. 19.4.1 SSS Configuration
    5. 19.5 Lock and Commit Registers
    6. 19.6 Interrupt and Error Handling
    7. 19.7 RTDMA Interfaces
      1. 19.7.1 RTDMA Trigger
    8. 19.8 Software
      1. 19.8.1 WADI Registers to Driverlib Functions
      2. 19.8.2 WADI Examples
        1. 19.8.2.1 WADI Duty and Frequency check - SINGLE_CORE
    9. 19.9 WADI Registers
      1. 19.9.1 WADI Base Address Table
      2. 19.9.2 WADI_CONFIG_REGS Registers
      3. 19.9.3 WADI_OPER_SSS_REGS Registers
  22. 20Crossbar (X-BAR)
    1. 20.1 X-BAR Related Collateral
    2. 20.2 Input X-BAR, ICL XBAR, MINDB XBAR,
      1. 20.2.1 ICL and MINDB X-BAR
    3. 20.3 ePWM , CLB, and GPIO Output X-BAR
      1. 20.3.1 ePWM X-BAR
        1. 20.3.1.1 ePWM X-BAR Architecture
      2. 20.3.2 CLB X-BAR
        1. 20.3.2.1 CLB X-BAR Architecture
      3. 20.3.3 GPIO Output X-BAR
        1. 20.3.3.1 GPIO Output X-BAR Architecture
      4. 20.3.4 X-BAR Flags
    4. 20.4 Software
      1. 20.4.1 INPUT_XBAR Registers to Driverlib Functions
      2. 20.4.2 EPWM_XBAR Registers to Driverlib Functions
      3. 20.4.3 CLB_XBAR Registers to Driverlib Functions
      4. 20.4.4 OUTPUT_XBAR Registers to Driverlib Functions
      5. 20.4.5 MDL_XBAR Registers to Driverlib Functions
      6. 20.4.6 ICL_XBAR Registers to Driverlib Functions
      7. 20.4.7 XBAR Registers to Driverlib Functions
      8. 20.4.8 XBAR Examples
        1. 20.4.8.1 Input XBAR to Output XBAR Connection - SINGLE_CORE
        2. 20.4.8.2 Output XBAR Pulse Stretch - SINGLE_CORE
    5. 20.5 XBAR Registers
      1. 20.5.1 XBAR Base Address Table
      2. 20.5.2 INPUT_XBAR_REGS Registers
      3. 20.5.3 EPWM_XBAR_REGS Registers
      4. 20.5.4 CLB_XBAR_REGS Registers
      5. 20.5.5 OUTPUTXBAR_REGS Registers
      6. 20.5.6 MDL_XBAR_REGS Registers
      7. 20.5.7 ICL_XBAR_REGS Registers
      8. 20.5.8 OUTPUTXBAR_FLAG_REGS Registers
      9. 20.5.9 XBAR_REGS Registers
  23. 21Embedded Pattern Generator (EPG)
    1. 21.1 Introduction
      1. 21.1.1 Features
      2. 21.1.2 EPG Block Diagram
      3. 21.1.3 EPG Related Collateral
    2. 21.2 Clock Generator Modules
      1. 21.2.1 DCLK (50% duty cycle clock)
      2. 21.2.2 Clock Stop
    3. 21.3 Signal Generator Module
    4. 21.4 EPG Peripheral Signal Mux Selection
    5. 21.5 Application Software Notes
    6. 21.6 EPG Example Use Cases
      1. 21.6.1 EPG Example: Synchronous Clocks with Offset
        1. 21.6.1.1 Synchronous Clocks with Offset Register Configuration
      2. 21.6.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 21.6.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 21.6.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 21.6.3.1 Serial Data Bit Stream (MSB first) Register Configuration
      4. 21.6.4 EPG Example: Clock and Data Pair
        1. 21.6.4.1 Clock and Data Pair Register Configuration
      5. 21.6.5 EPG Example: Clock and Skewed Data Pair
        1. 21.6.5.1 Clock and Skewed Data Pair Register Configuration
      6. 21.6.6 EPG Example: Capturing Serial Data with a Known Baud Rate
        1. 21.6.6.1 Capturing Serial Data with a Known Baud Rate Register Configuration
    7. 21.7 EPG Interrupt
    8. 21.8 Software
      1. 21.8.1 EPG Registers to Driverlib Functions
      2. 21.8.2 EPG Examples
        1. 21.8.2.1 EPG Generating Synchronous Clocks - SINGLE_CORE
        2. 21.8.2.2 EPG Generating Two Offset Clocks - SINGLE_CORE
        3. 21.8.2.3 EPG Generating Two Offset Clocks With SIGGEN - SINGLE_CORE
        4. 21.8.2.4 EPG Generate Serial Data - SINGLE_CORE
        5. 21.8.2.5 EPG Generate Serial Data Shift Mode - SINGLE_CORE
    9. 21.9 EPG Registers
      1. 21.9.1 EPG Base Address Table
      2. 21.9.2 EPG_REGS Registers
      3. 21.9.3 EPG_MUX_REGS Registers
  24. 22â–º ANALOG PERIPHERALS
    1.     Technical Reference Manual Overview
  25. 23Analog Subsystem
    1. 23.1 Introduction
      1. 23.1.1 Features
      2. 23.1.2 Block Diagram
    2. 23.2 Optimizing Power-Up Time
    3. 23.3 Digital Inputs on ADC Pins (AIOs)
    4. 23.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 23.5 Analog Pins and Internal Connections
    6. 23.6 Software
      1. 23.6.1 ASYSCTL Registers to Driverlib Functions
    7. 23.7 Lock Registers
    8. 23.8 ASBSYS Registers
      1. 23.8.1 ASBSYS Base Address Table
      2. 23.8.2 ANALOG_SUBSYS_REGS Registers
  26. 24Analog-to-Digital Converter (ADC)
    1. 24.1  Introduction
      1. 24.1.1 ADC Related Collateral
      2. 24.1.2 Features
      3. 24.1.3 Block Diagram
    2. 24.2  ADC Configurability
      1. 24.2.1 Clock Configuration
      2. 24.2.2 Resolution
      3. 24.2.3 Voltage Reference
        1. 24.2.3.1 External Reference Mode
        2. 24.2.3.2 Internal Reference Mode
        3. 24.2.3.3 Ganged References
        4. 24.2.3.4 Selecting Reference Mode
      4. 24.2.4 Signal Mode
      5. 24.2.5 Expected Conversion Results
      6. 24.2.6 Interpreting Conversion Results
    3. 24.3  SOC Principle of Operation
      1. 24.3.1 SOC Configuration
      2. 24.3.2 Trigger Operation
        1. 24.3.2.1 Global Software Trigger
        2. 24.3.2.2 Trigger Repeaters
          1. 24.3.2.2.1 Oversampling Mode
          2. 24.3.2.2.2 Undersampling Mode
          3. 24.3.2.2.3 Trigger Phase Delay
          4. 24.3.2.2.4 Re-trigger Spread
          5. 24.3.2.2.5 Trigger Repeater Configuration
            1. 24.3.2.2.5.1 Register Shadow Updates
          6. 24.3.2.2.6 Re-Trigger Logic
          7. 24.3.2.2.7 Multi-Path Triggering Behavior
      3. 24.3.3 ADC Acquisition (Sample and Hold) Window
      4. 24.3.4 ADC Input Models
      5. 24.3.5 Channel Selection
        1. 24.3.5.1 External Channel Selection
          1. 24.3.5.1.1 External Channel Selection Timing
    4. 24.4  SOC Configuration Examples
      1. 24.4.1 Single Conversion from ePWM Trigger
      2. 24.4.2 Oversampled Conversion from ePWM Trigger
      3. 24.4.3 Multiple Conversions from CPU Timer Trigger
      4. 24.4.4 Software Triggering of SOCs
    5. 24.5  ADC Conversion Priority
    6. 24.6  Burst Mode
      1. 24.6.1 Burst Mode Example
      2. 24.6.2 Burst Mode Priority Example
    7. 24.7  EOC and Interrupt Operation
      1. 24.7.1 Interrupt Overflow
      2. 24.7.2 Continue to Interrupt Mode
      3. 24.7.3 Early Interrupt Configuration Mode
    8. 24.8  Post-Processing Blocks
      1. 24.8.1 PPB Offset Correction
      2. 24.8.2 PPB Error Calculation
      3. 24.8.3 PPB Result Delta Calculation
      4. 24.8.4 PPB Limit Detection and Zero-Crossing Detection
        1. 24.8.4.1 PPB Digital Trip Filter
      5. 24.8.5 PPB Sample Delay Capture
      6. 24.8.6 PPB Oversampling
        1. 24.8.6.1 Accumulation, Minimum, Maximum, and Average Functions
        2. 24.8.6.2 Outlier Rejection
    9. 24.9  Result Safety Checker
      1. 24.9.1 Result Safety Checker Operation
      2. 24.9.2 Result Safety Checker Interrupts and Events
    10. 24.10 Opens/Shorts Detection Circuit (OSDETECT)
      1. 24.10.1 Implementation
      2. 24.10.2 Detecting an Open Input Pin
      3. 24.10.3 Detecting a Shorted Input Pin
    11. 24.11 Power-Up Sequence
    12. 24.12 ADC Calibration
      1. 24.12.1 ADC Zero Offset Calibration
    13. 24.13 ADC Timings
      1. 24.13.1 ADC Timing Diagrams
      2. 24.13.2 Post-Processing Block Timings
    14. 24.14 Additional Information
      1. 24.14.1 Ensuring Synchronous Operation
        1. 24.14.1.1 Basic Synchronous Operation
        2. 24.14.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 24.14.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 24.14.1.4 Synchronous Operation with Different Resolutions
        5. 24.14.1.5 Non-overlapping Conversions
      2. 24.14.2 Choosing an Acquisition Window Duration
      3. 24.14.3 Achieving Simultaneous Sampling
      4. 24.14.4 Result Register Mapping
      5. 24.14.5 Internal Temperature Sensor
      6. 24.14.6 Designing an External Reference Circuit
      7. 24.14.7 Internal Test Mode
      8. 24.14.8 ADC Gain and Offset Calibration
    15. 24.15 Software
      1. 24.15.1 ADC Registers to Driverlib Functions
      2. 24.15.2 ADC Examples
        1. 24.15.2.1  ADC Software Triggering - SINGLE_CORE
        2. 24.15.2.2  ADC ePWM Triggering - SINGLE_CORE
        3. 24.15.2.3  ADC Temperature Sensor Conversion - SINGLE_CORE
        4. 24.15.2.4  ADC Synchronous SOC Software Force (adc_soc_software_sync) - SINGLE_CORE
        5. 24.15.2.5  ADC Continuous Triggering (adc_soc_continuous) - SINGLE_CORE
        6. 24.15.2.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma) - SINGLE_CORE
        7. 24.15.2.7  ADC PPB Offset (adc_ppb_offset) - SINGLE_CORE
        8. 24.15.2.8  ADC PPB Limits (adc_ppb_limits) - SINGLE_CORE
        9. 24.15.2.9  ADC PPB Delay Capture (adc_ppb_delay) - SINGLE_CORE
        10. 24.15.2.10 ADC ePWM Triggering Multiple SOC - SINGLE_CORE
        11. 24.15.2.11 ADC Burst Mode - SINGLE_CORE
        12. 24.15.2.12 ADC Burst Mode Oversampling - SINGLE_CORE
        13. 24.15.2.13 ADC SOC Oversampling - SINGLE_CORE
        14. 24.15.2.14 ADC PPB PWM trip (adc_ppb_pwm_trip) - SINGLE_CORE
        15. 24.15.2.15 ADC Trigger Repeater Oversampling - SINGLE_CORE
        16. 24.15.2.16 ADC Trigger Repeater Undersampling - SINGLE_CORE
        17. 24.15.2.17 ADC Safety Checker - SINGLE_CORE
    16. 24.16 ADC Registers
      1. 24.16.1 ADC Base Address Table
      2. 24.16.2 ADC_RESULT_REGS Registers
      3. 24.16.3 ADC_REGS Registers
      4. 24.16.4 ADC_SAFECHECK_REGS Registers
      5. 24.16.5 ADC_SAFECHECK_INTEVT_REGS Registers
      6. 24.16.6 ADC_GLOBAL_REGS Registers
  27. 25Buffered Digital-to-Analog Converter (DAC)
    1. 25.1 Introduction
      1. 25.1.1 DAC Related Collateral
      2. 25.1.2 Features
      3. 25.1.3 Block Diagram
    2. 25.2 Using the DAC
      1. 25.2.1 Initialization Sequence
      2. 25.2.2 DAC Offset Adjustment
      3. 25.2.3 EPWMSYNCPER Signal
    3. 25.3 Lock Registers
    4. 25.4 Software
      1. 25.4.1 DAC Registers to Driverlib Functions
      2. 25.4.2 DAC Examples
        1. 25.4.2.1 Buffered DAC Enable - SINGLE_CORE
        2. 25.4.2.2 Buffered DAC Random - SINGLE_CORE
    5. 25.5 DAC Registers
      1. 25.5.1 DAC Base Address Table
      2. 25.5.2 DAC_REGS Registers
  28. 26Comparator Subsystem (CMPSS)
    1. 26.1 Introduction
      1. 26.1.1 CMPSS Related Collateral
      2. 26.1.2 Features
      3. 26.1.3 Block Diagram
    2. 26.2 Comparator
    3. 26.3 Reference DAC
    4. 26.4 Ramp Generator
      1. 26.4.1 Ramp Generator Overview
      2. 26.4.2 Ramp Generator Behavior
      3. 26.4.3 Ramp Generator Behavior at Corner Cases
    5. 26.5 Digital Filter
      1. 26.5.1 Filter Initialization Sequence
    6. 26.6 Using the CMPSS
      1. 26.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 26.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 26.6.3 Calibrating the CMPSS
      4. 26.6.4 Enabling and Disabling the CMPSS Clock
    7. 26.7 Software
      1. 26.7.1 CMPSS Registers to Driverlib Functions
      2. 26.7.2 CMPSS Examples
        1. 26.7.2.1 CMPSS Asynchronous Trip - SINGLE_CORE
        2. 26.7.2.2 CMPSS Digital Filter Configuration - SINGLE_CORE
    8. 26.8 CMPSS Registers
      1. 26.8.1 CMPSS Base Address Table
      2. 26.8.2 CMPSS_REGS Registers
  29. 27â–º CONTROL PERIPHERALS
    1.     Technical Reference Manual Overview
  30. 28Enhanced Capture (eCAP)
    1. 28.1 Introduction
      1. 28.1.1 Features
      2. 28.1.2 ECAP Related Collateral
    2. 28.2 Description
    3. 28.3 Configuring Device Pins for the eCAP
    4. 28.4 Capture and APWM Operating Mode
    5. 28.5 Capture Mode Description
      1. 28.5.1  Event Prescaler
      2. 28.5.2  Glitch Filter
      3. 28.5.3  Edge Polarity Select and Qualifier
      4. 28.5.4  Continuous/One-Shot Control
      5. 28.5.5  32-Bit Counter and Phase Control
      6. 28.5.6  CAP1-CAP4 Registers
      7. 28.5.7  eCAP Synchronization
        1. 28.5.7.1 Example 1 - Using SWSYNC with ECAP Module
      8. 28.5.8  Interrupt Control
      9. 28.5.9  RTDMA Interrupt
      10. 28.5.10 ADC SOC Event
      11. 28.5.11 Shadow Load and Lockout Control
      12. 28.5.12 APWM Mode Operation
      13. 28.5.13 Signal Monitoring Unit
        1. 28.5.13.1 Pulse Width and Period Monitoring
        2. 28.5.13.2 Edge Monitoring
    6. 28.6 Application of the eCAP Module
      1. 28.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 28.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 28.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 28.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 28.7 Application of the APWM Mode
      1. 28.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 28.8 Software
      1. 28.8.1 ECAP Registers to Driverlib Functions
      2. 28.8.2 ECAP Examples
        1. 28.8.2.1 eCAP APWM Example - SINGLE_CORE
        2. 28.8.2.2 eCAP Capture PWM Example - SINGLE_CORE
        3. 28.8.2.3 eCAP APWM Phase-shift Example - SINGLE_CORE
    9. 28.9 ECAP Registers
      1. 28.9.1 ECAP Base Address Table
      2. 28.9.2 ECAP_REGS Registers
      3. 28.9.3 ECAP_SIGNAL_MONITORING Registers
      4. 28.9.4 HRCAP_REGS Registers
  31. 29High Resolution Capture (HRCAP)
    1. 29.1 Introduction
      1. 29.1.1 HRCAP Related Collateral
      2. 29.1.2 Features
      3. 29.1.3 Description
    2. 29.2 Operational Details
      1. 29.2.1 HRCAP Clocking
      2. 29.2.2 HRCAP Initialization Sequence
      3. 29.2.3 HRCAP Interrupts
      4. 29.2.4 HRCAP Calibration
        1. 29.2.4.1 Applying the Scale Factor
    3. 29.3 Known Exceptions
    4. 29.4 Software
      1. 29.4.1 HRCAP Examples
        1. 29.4.1.1 HRCAP Capture and Calibration Example - SINGLE_CORE
    5. 29.5 HRCAP Registers
      1. 29.5.1 HRCAP Base Address Table
      2. 29.5.2 HRCAP_REGS Registers
  32. 30Enhanced Pulse Width Modulator (ePWM)
    1. 30.1  Introduction
      1. 30.1.1 EPWM Related Collateral
      2. 30.1.2 Submodule Overview
    2. 30.2  Configuring Device Pins
    3. 30.3  ePWM Modules Overview
    4. 30.4  Time-Base (TB) Submodule
      1. 30.4.1 Purpose of the Time-Base Submodule
      2. 30.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 30.4.3 Calculating PWM Period and Frequency
        1. 30.4.3.1 Time-Base Period Shadow Register
        2. 30.4.3.2 Time-Base Clock Synchronization
        3. 30.4.3.3 Time-Base Counter Synchronization
        4. 30.4.3.4 ePWM SYNC Selection
      4. 30.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 30.4.5 Simultaneous Writes Between ePWM Register Instances
      6. 30.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 30.4.7 Global Load
        1. 30.4.7.1 Global Load Pulse Pre-Scalar
        2. 30.4.7.2 One-Shot Load Mode
        3. 30.4.7.3 One-Shot Sync Mode
    5. 30.5  Counter-Compare (CC) Submodule
      1. 30.5.1 Purpose of the Counter-Compare Submodule
      2. 30.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 30.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 30.5.4 Count Mode Timing Waveforms
    6. 30.6  Action-Qualifier (AQ) Submodule
      1. 30.6.1 Purpose of the Action-Qualifier Submodule
      2. 30.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 30.6.3 Action-Qualifier Event Priority
      4. 30.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 30.6.5 Configuration Requirements for Common Waveforms
    7. 30.7  XCMP Complex Waveform Generator Mode
      1. 30.7.1 XCMP Allocation to CMPA and CMPB
      2. 30.7.2 XCMP Shadow Buffers
      3. 30.7.3 XCMP Operation
    8. 30.8  Dead-Band Generator (DB) Submodule
      1. 30.8.1 Purpose of the Dead-Band Submodule
      2. 30.8.2 Dead-band Submodule Additional Operating Modes
      3. 30.8.3 Operational Highlights for the Dead-Band Submodule
    9. 30.9  PWM Chopper (PC) Submodule
      1. 30.9.1 Purpose of the PWM Chopper Submodule
      2. 30.9.2 Operational Highlights for the PWM Chopper Submodule
      3. 30.9.3 Waveforms
        1. 30.9.3.1 One-Shot Pulse
        2. 30.9.3.2 Duty Cycle Control
    10. 30.10 Trip-Zone (TZ) Submodule
      1. 30.10.1 Purpose of the Trip-Zone Submodule
      2. 30.10.2 Operational Highlights for the Trip-Zone Submodule
        1. 30.10.2.1 Trip-Zone Configurations
      3. 30.10.3 Generating Trip Event Interrupts
    11. 30.11 Diode Emulation (DE) Submodule
      1. 30.11.1 DEACTIVE Mode
      2. 30.11.2 Exiting DE Mode
      3. 30.11.3 Re-Entering DE Mode
      4. 30.11.4 DE Monitor
    12. 30.12 Minimum Dead-Band (MINDB) + Illegal Combination Logic (ICL) Submodules
      1. 30.12.1 Minimum Dead-Band (MINDB)
      2. 30.12.2 Illegal Combo Logic (ICL)
    13. 30.13 Event-Trigger (ET) Submodule
      1. 30.13.1 Operational Overview of the ePWM Event-Trigger Submodule
    14. 30.14 Digital Compare (DC) Submodule
      1. 30.14.1 Purpose of the Digital Compare Submodule
      2. 30.14.2 Enhanced Trip Action Using CMPSS
      3. 30.14.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 30.14.4 Operation Highlights of the Digital Compare Submodule
        1. 30.14.4.1 Digital Compare Events
        2. 30.14.4.2 Event Filtering
        3. 30.14.4.3 Valley Switching
        4. 30.14.4.4 Event Detection
          1. 30.14.4.4.1 Input Signal Detection
          2. 30.14.4.4.2 MIN and MAX Detection Circuit
    15. 30.15 ePWM Crossbar (X-BAR)
    16. 30.16 Applications to Power Topologies
      1. 30.16.1  Overview of Multiple Modules
      2. 30.16.2  Key Configuration Capabilities
      3. 30.16.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 30.16.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 30.16.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 30.16.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 30.16.7  Practical Applications Using Phase Control Between PWM Modules
      8. 30.16.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 30.16.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 30.16.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 30.16.11 Controlling H-Bridge LLC Resonant Converter
    17. 30.17 Register Lock Protection
    18. 30.18 High-Resolution Pulse Width Modulator (HRPWM)
      1. 30.18.1 Operational Description of HRPWM
        1. 30.18.1.1 Controlling the HRPWM Capabilities
        2. 30.18.1.2 HRPWM Source Clock
        3. 30.18.1.3 Configuring the HRPWM
        4. 30.18.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 30.18.1.5 Principle of Operation
          1. 30.18.1.5.1 Edge Positioning
          2. 30.18.1.5.2 Scaling Considerations
          3. 30.18.1.5.3 Duty Cycle Range Limitation
          4. 30.18.1.5.4 High-Resolution Period
            1. 30.18.1.5.4.1 High-Resolution Period Configuration
        6. 30.18.1.6 Deadband High-Resolution Operation
        7. 30.18.1.7 Scale Factor Optimizing Software (SFO)
        8. 30.18.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 30.18.1.8.1 #Defines for HRPWM Header Files
          2. 30.18.1.8.2 Implementing a Simple Buck Converter
            1. 30.18.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 30.18.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 30.18.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 30.18.1.8.3.1 PWM DAC Function Initialization Code
            2. 30.18.1.8.3.2 PWM DAC Function Run-Time Code
      2. 30.18.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 30.18.2.1 Scale Factor Optimizer Function - int SFO()
        2. 30.18.2.2 Software Usage
          1. 30.18.2.2.1 A Sample of How to Add "Include" Files
          2.        1131
          3. 30.18.2.2.2 Declaring an Element
          4.        1133
          5. 30.18.2.2.3 Initializing With a Scale Factor Value
          6.        1135
          7. 30.18.2.2.4 SFO Function Calls
    19. 30.19 Software
      1. 30.19.1 EPWM Registers to Driverlib Functions
      2. 30.19.2 HRPWMCAL Registers to Driverlib Functions
      3. 30.19.3 EPWM Examples
        1. 30.19.3.1  ePWM Trip Zone - SINGLE_CORE
        2. 30.19.3.2  ePWM Up Down Count Action Qualifier - SINGLE_CORE
        3. 30.19.3.3  ePWM Synchronization - SINGLE_CORE
        4. 30.19.3.4  ePWM Digital Compare - SINGLE_CORE
        5. 30.19.3.5  ePWM Digital Compare Event Filter Blanking Window - SINGLE_CORE
        6. 30.19.3.6  ePWM Valley Switching - SINGLE_CORE
        7. 30.19.3.7  ePWM Digital Compare Edge Filter - SINGLE_CORE
        8. 30.19.3.8  ePWM Deadband - SINGLE_CORE
        9. 30.19.3.9  ePWM DMA - SINGLE_CORE
        10. 30.19.3.10 ePWM Chopper - SINGLE_CORE
        11. 30.19.3.11 EPWM Configure Signal - SINGLE_CORE
        12. 30.19.3.12 Realization of Monoshot mode - SINGLE_CORE
        13. 30.19.3.13 EPWM Action Qualifier (epwm_up_aq) - SINGLE_CORE
        14. 30.19.3.14 ePWM XCMP Mode - SINGLE_CORE
        15. 30.19.3.15 ePWM Event Detection - SINGLE_CORE
    20. 30.20 EPWM Registers
      1. 30.20.1 EPWM Base Address Table
      2. 30.20.2 EPWM_REGS Registers
      3. 30.20.3 EPWM_XCMP_REGS Registers
      4. 30.20.4 DE_REGS Registers
      5. 30.20.5 MINDB_LUT_REGS Registers
      6. 30.20.6 HRPWMCAL_REGS Registers
  33. 31Enhanced Quadrature Encoder Pulse (eQEP)
    1. 31.1  Introduction
      1. 31.1.1 EQEP Related Collateral
    2. 31.2  Configuring Device Pins
    3. 31.3  Description
      1. 31.3.1 EQEP Inputs
      2. 31.3.2 Functional Description
      3. 31.3.3 eQEP Memory Map
    4. 31.4  Quadrature Decoder Unit (QDU)
      1. 31.4.1 Position Counter Input Modes
        1. 31.4.1.1 Quadrature Count Mode
        2. 31.4.1.2 Direction-Count Mode
        3. 31.4.1.3 Up-Count Mode
        4. 31.4.1.4 Down-Count Mode
      2. 31.4.2 eQEP Input Polarity Selection
      3. 31.4.3 Position-Compare Sync Output
    5. 31.5  Position Counter and Control Unit (PCCU)
      1. 31.5.1 Position Counter Operating Modes
        1. 31.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 31.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 31.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 31.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 31.5.2 Position Counter Latch
        1. 31.5.2.1 Index Event Latch
        2. 31.5.2.2 Strobe Event Latch
      3. 31.5.3 Position Counter Initialization
      4. 31.5.4 eQEP Position-compare Unit
    6. 31.6  eQEP Edge Capture Unit
    7. 31.7  eQEP Watchdog
    8. 31.8  eQEP Unit Timer Base
    9. 31.9  QMA Module
      1. 31.9.1 Modes of Operation
        1. 31.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 31.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 31.9.2 Interrupt and Error Generation
    10. 31.10 eQEP Interrupt Structure
    11. 31.11 Software
      1. 31.11.1 EQEP Registers to Driverlib Functions
      2. 31.11.2 EQEP Examples
        1. 31.11.2.1 Frequency Measurement Using eQEP via unit timeout interrupt - SINGLE_CORE
        2. 31.11.2.2 Motor speed and direction measurement using eQEP via unit timeout interrupt - SINGLE_CORE
    12. 31.12 EQEP Registers
      1. 31.12.1 EQEP Base Address Table
      2. 31.12.2 EQEP_REGS Registers
  34. 32Sigma Delta Filter Module (SDFM)
    1. 32.1  Introduction
      1. 32.1.1 SDFM Related Collateral
      2. 32.1.2 Features
      3. 32.1.3 Block Diagram
    2. 32.2  Configuring Device Pins
    3. 32.3  Input Qualification
    4. 32.4  Input Control Unit
    5. 32.5  SDFM Clock Control
    6. 32.6  Sinc Filter
      1. 32.6.1 Data Rate and Latency of the Sinc Filter
    7. 32.7  Data (Primary) Filter Unit
      1. 32.7.1 32-bit or 16-bit Data Filter Output Representation
      2. 32.7.2 Data FIFO
      3. 32.7.3 SDSYNC Event
    8. 32.8  Comparator (Secondary) Filter Unit
      1. 32.8.1 Higher Threshold (HLT) Comparators
      2. 32.8.2 Lower Threshold (LLT) Comparators
      3. 32.8.3 Digital Filter
    9. 32.9  Theoretical SDFM Filter Output
    10. 32.10 Interrupt Unit
      1. 32.10.1 SDFM (SDyERR) Interrupt Sources
      2. 32.10.2 Data Ready (DRINT) Interrupt Sources
    11. 32.11 Software
      1. 32.11.1 SDFM Registers to Driverlib Functions
      2. 32.11.2 SDFM Examples
    12. 32.12 SDFM Registers
      1. 32.12.1 SDFM Base Address Table
      2. 32.12.2 SDFM_REGS Registers
  35. 33â–º COMMUNICATION PERIPHERALS
    1.     Technical Reference Manual Overview
  36. 34Modular Controller Area Network (MCAN)
    1. 34.1 MCAN Introduction
      1. 34.1.1 MCAN Related Collateral
      2. 34.1.2 MCAN Features
    2. 34.2 MCAN Environment
    3. 34.3 CAN Network Basics
    4. 34.4 MCAN Integration
    5. 34.5 MCAN Functional Description
      1. 34.5.1  Module Clocking Requirements
      2. 34.5.2  Interrupt Requests
      3. 34.5.3  Operating Modes
        1. 34.5.3.1 Software Initialization
        2. 34.5.3.2 Normal Operation
        3. 34.5.3.3 CAN FD Operation
      4. 34.5.4  Transmitter Delay Compensation
        1. 34.5.4.1 Description
        2. 34.5.4.2 Transmitter Delay Compensation Measurement
      5. 34.5.5  Restricted Operation Mode
      6. 34.5.6  Bus Monitoring Mode
      7. 34.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 34.5.7.1 Frame Transmission in DAR Mode
      8. 34.5.8  Clock Stop Mode
        1. 34.5.8.1 Suspend Mode
        2. 34.5.8.2 Wakeup Request
      9. 34.5.9  Test Modes
        1. 34.5.9.1 External Loop Back Mode
        2. 34.5.9.2 Internal Loop Back Mode
      10. 34.5.10 Timestamp Generation
        1. 34.5.10.1 External Timestamp Counter
      11. 34.5.11 Timeout Counter
      12. 34.5.12 Safety
        1. 34.5.12.1 ECC Wrapper
        2. 34.5.12.2 ECC Aggregator
          1. 34.5.12.2.1 ECC Aggregator Overview
          2. 34.5.12.2.2 ECC Aggregator Registers
        3. 34.5.12.3 Reads to ECC Control and Status Registers
        4. 34.5.12.4 ECC Interrupts
      13. 34.5.13 Rx Handling
        1. 34.5.13.1 Acceptance Filtering
          1. 34.5.13.1.1 Range Filter
          2. 34.5.13.1.2 Filter for Specific IDs
          3. 34.5.13.1.3 Classic Bit Mask Filter
          4. 34.5.13.1.4 Standard Message ID Filtering
          5. 34.5.13.1.5 Extended Message ID Filtering
        2. 34.5.13.2 Rx FIFOs
          1. 34.5.13.2.1 Rx FIFO Blocking Mode
          2. 34.5.13.2.2 Rx FIFO Overwrite Mode
        3. 34.5.13.3 Dedicated Rx Buffers
          1. 34.5.13.3.1 Rx Buffer Handling
      14. 34.5.14 Tx Handling
        1. 34.5.14.1 Transmit Pause
        2. 34.5.14.2 Dedicated Tx Buffers
        3. 34.5.14.3 Tx FIFO
        4. 34.5.14.4 Tx Queue
        5. 34.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 34.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 34.5.14.7 Transmit Cancellation
        8. 34.5.14.8 Tx Event Handling
      15. 34.5.15 FIFO Acknowledge Handling
      16. 34.5.16 Message RAM
        1. 34.5.16.1 Message RAM Configuration
        2. 34.5.16.2 Rx Buffer and FIFO Element
        3. 34.5.16.3 Tx Buffer Element
        4. 34.5.16.4 Tx Event FIFO Element
        5. 34.5.16.5 Standard Message ID Filter Element
        6. 34.5.16.6 Extended Message ID Filter Element
    6. 34.6 Software
      1. 34.6.1 MCAN Examples
        1. 34.6.1.1 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
        2. 34.6.1.2 MCAN Loopback with Polling Example Using SYSCONFIG Tool - SINGLE_CORE
        3. 34.6.1.3 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
    7. 34.7 MCAN Registers
      1. 34.7.1 MCAN Base Address Table
      2. 34.7.2 MCANSS_REGS Registers
      3. 34.7.3 MCAN_REGS Registers
      4. 34.7.4 MCAN_ERROR_REGS Registers
  37. 35EtherCAT® SubordinateDevice Controller (ESC)
    1. 35.1 Introduction
      1. 35.1.1  EtherCAT Related Collateral
      2. 35.1.2  ESC Features
      3. 35.1.3  ESC Subsystem Integrated Features
      4. 35.1.4  ESC versus Beckhoff ET1100
      5. 35.1.5  EtherCAT IP Block Diagram
      6. 35.1.6  ESC Functional Blocks
        1. 35.1.6.1  Interface to EtherCAT MainDevice
        2. 35.1.6.2  Process Data Interface
        3. 35.1.6.3  General-Purpose Inputs and Outputs
        4. 35.1.6.4  EtherCAT Processing Unit (EPU)
        5. 35.1.6.5  Fieldbus Memory Management Unit (FMMU)
        6. 35.1.6.6  Sync Manager
        7. 35.1.6.7  Monitoring
        8. 35.1.6.8  Reset Controller
        9. 35.1.6.9  PHY Management
        10. 35.1.6.10 Distributed Clock (DC)
        11. 35.1.6.11 EEPROM
        12. 35.1.6.12 Status / LEDs
      7. 35.1.7  EtherCAT Physical Layer
        1. 35.1.7.1 MII Interface
        2. 35.1.7.2 PHY Management Interface
          1. 35.1.7.2.1 PHY Address Configuration
          2. 35.1.7.2.2 PHY Reset Signal
          3. 35.1.7.2.3 PHY Clock
      8. 35.1.8  EtherCAT Protocol
      9. 35.1.9  EtherCAT State Machine (ESM)
      10. 35.1.10 More Information on EtherCAT
      11. 35.1.11 Beckhoff® Automation EtherCAT IP Errata
    2. 35.2 ESC and ESCSS Description
      1. 35.2.1  ESC RAM Parity and Memory Address Maps
        1. 35.2.1.1 ESC RAM Parity Logic
        2. 35.2.1.2 CPU1 ESC Memory Address Map
        3. 35.2.1.3 CPU2 ESC Memory Address Map
      2. 35.2.2  Local Host Communication
        1. 35.2.2.1 Byte Accessibility Through PDI
        2. 35.2.2.2 Software Details for Operation Across Clock Domains
      3. 35.2.3  Debug Emulation Mode Operation
      4. 35.2.4  ESC SubSystem
        1. 35.2.4.1 CPU1 Bus Interface
        2. 35.2.4.2 CPU2/CPU3 Bus Interface
      5. 35.2.5  Interrupts and Interrupt Mapping
      6. 35.2.6  Power, Clocks, and Resets
        1. 35.2.6.1 Power
        2. 35.2.6.2 Clocking
        3. 35.2.6.3 Resets
          1. 35.2.6.3.1 Chip-Level Reset
          2. 35.2.6.3.2 EtherCAT Soft Resets
          3. 35.2.6.3.3 Reset Out (RESET_OUT)
      7. 35.2.7  LED Controls
      8. 35.2.8  SubordinateDevice Node Configuration and EEPROM
      9. 35.2.9  General-Purpose Inputs and Outputs
        1. 35.2.9.1 General-Purpose Inputs
        2. 35.2.9.2 General-Purpose Output
      10. 35.2.10 Distributed Clocks – Sync and Latch
        1. 35.2.10.1 Clock Synchronization
        2. 35.2.10.2 SYNC Signals
          1. 35.2.10.2.1 Seeking Host Intervention
        3. 35.2.10.3 LATCH Signals
          1. 35.2.10.3.1 Timestamping
        4. 35.2.10.4 Device Control and Synchronization
          1. 35.2.10.4.1 Synchronization of PWM
          2. 35.2.10.4.2 ECAP SYNC Inputs
          3. 35.2.10.4.3 SYNC Signal Conditioning and Rerouting
    3. 35.3 Software Initialization Sequence and Allocating Ownership
    4. 35.4 ESC Configuration Constants
    5. 35.5 Software
      1. 35.5.1 ECAT_SS Registers to Driverlib Functions
      2. 35.5.2 ETHERNET Examples
    6. 35.6 ETHERCAT Registers
      1. 35.6.1 ETHERCAT Base Address Table
      2. 35.6.2 ESCSS_REGS Registers
      3. 35.6.3 ESCSS_CONFIG_REGS Registers
  38. 36Fast Serial Interface (FSI)
    1. 36.1 Introduction
      1. 36.1.1 FSI Related Collateral
      2. 36.1.2 FSI Features
    2. 36.2 System-level Integration
      1. 36.2.1 CPU Interface
      2. 36.2.2 Signal Description
        1. 36.2.2.1 Configuring Device Pins
      3. 36.2.3 FSI Interrupts
        1. 36.2.3.1 Transmitter Interrupts
        2. 36.2.3.2 Receiver Interrupts
        3. 36.2.3.3 Configuring Interrupts
        4. 36.2.3.4 Handling Interrupts
      4. 36.2.4 RTDMA Interface
      5. 36.2.5 External Frame Trigger Mux
    3. 36.3 FSI Functional Description
      1. 36.3.1 Introduction to Operation
      2. 36.3.2 FSI Transmitter Module
        1. 36.3.2.1 Initialization
        2. 36.3.2.2 FSI_TX Clocking
        3. 36.3.2.3 Transmitting Frames
          1. 36.3.2.3.1 Software Triggered Frames
          2. 36.3.2.3.2 Externally Triggered Frames
          3. 36.3.2.3.3 Ping Frame Generation
            1. 36.3.2.3.3.1 Automatic Ping Frames
            2. 36.3.2.3.3.2 Software Triggered Ping Frame
            3. 36.3.2.3.3.3 Externally Triggered Ping Frame
          4. 36.3.2.3.4 Transmitting Frames with RTDMA
        4. 36.3.2.4 Transmit Buffer Management
        5. 36.3.2.5 CRC Submodule
        6. 36.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 36.3.2.7 Reset
      3. 36.3.3 FSI Receiver Module
        1. 36.3.3.1  Initialization
        2. 36.3.3.2  FSI_RX Clocking
        3. 36.3.3.3  Receiving Frames
          1. 36.3.3.3.1 Receiving Frames with RTDMA
        4. 36.3.3.4  Ping Frame Watchdog
        5. 36.3.3.5  Frame Watchdog
        6. 36.3.3.6  Delay Line Control
        7. 36.3.3.7  Buffer Management
        8. 36.3.3.8  CRC Submodule
        9. 36.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 36.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 36.3.3.11 FSI_RX Reset
      4. 36.3.4 Frame Format
        1. 36.3.4.1 FSI Frame Phases
        2. 36.3.4.2 Frame Types
          1. 36.3.4.2.1 Ping Frames
          2. 36.3.4.2.2 Error Frames
          3. 36.3.4.2.3 Data Frames
        3. 36.3.4.3 Multi-Lane Transmission
      5. 36.3.5 Flush Sequence
      6. 36.3.6 Internal Loopback
      7. 36.3.7 CRC Generation
      8. 36.3.8 ECC Module
      9. 36.3.9 FSI-SPI Compatibility Mode
        1. 36.3.9.1 Available SPI Modes
          1. 36.3.9.1.1 FSITX as SPI Controller, Transmit Only
            1. 36.3.9.1.1.1 Initialization
            2. 36.3.9.1.1.2 Operation
          2. 36.3.9.1.2 FSIRX as SPI Peripheral, Receive Only
            1. 36.3.9.1.2.1 Initialization
            2. 36.3.9.1.2.2 Operation
          3. 36.3.9.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
            1. 36.3.9.1.3.1 Initialization
            2. 36.3.9.1.3.2 Operation
    4. 36.4 FSI Programing Guide
      1. 36.4.1 Establishing the Communication Link
        1. 36.4.1.1 Establishing the Communication Link from the Main Device
        2. 36.4.1.2 Establishing the Communication Link from the Remote Device
      2. 36.4.2 Register Protection
      3. 36.4.3 Emulation Mode
    5. 36.5 Software
      1. 36.5.1 FSI Registers to Driverlib Functions
      2. 36.5.2 FSI Examples
        1. 36.5.2.1 FSI Loopback:CPU Control - SINGLE_CORE
        2. 36.5.2.2 FSI data transfers upon CPU Timer event - SINGLE_CORE
    6. 36.6 FSI Registers
      1. 36.6.1 FSI Base Address Table
      2. 36.6.2 FSI_TX_REGS Registers
      3. 36.6.3 FSI_RX_REGS Registers
  39. 37Inter-Integrated Circuit Module (I2C)
    1. 37.1 Introduction
      1. 37.1.1 I2C Related Collateral
      2. 37.1.2 Features
      3. 37.1.3 Features Not Supported
      4. 37.1.4 Functional Overview
      5. 37.1.5 Clock Generation
      6. 37.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 37.1.6.1 Formula for the Controller Clock Period
    2. 37.2 Configuring Device Pins
    3. 37.3 I2C Module Operational Details
      1. 37.3.1  Input and Output Voltage Levels
      2. 37.3.2  Selecting Pullup Resistors
      3. 37.3.3  Data Validity
      4. 37.3.4  Operating Modes
      5. 37.3.5  I2C Module START and STOP Conditions
      6. 37.3.6  Non-repeat Mode versus Repeat Mode
      7. 37.3.7  Serial Data Formats
        1. 37.3.7.1 7-Bit Addressing Format
        2. 37.3.7.2 10-Bit Addressing Format
        3. 37.3.7.3 Free Data Format
        4. 37.3.7.4 Using a Repeated START Condition
      8. 37.3.8  Clock Synchronization
      9. 37.3.9  Clock Stretching
      10. 37.3.10 Arbitration
      11. 37.3.11 Digital Loopback Mode
      12. 37.3.12 NACK Bit Generation
    4. 37.4 Interrupt Requests Generated by the I2C Module
      1. 37.4.1 Basic I2C Interrupt Requests
      2. 37.4.2 I2C FIFO Interrupts
    5. 37.5 Resetting or Disabling the I2C Module
    6. 37.6 Software
      1. 37.6.1 I2C Registers to Driverlib Functions
      2. 37.6.2 I2C Examples
        1. 37.6.2.1 I2C Digital Loopback with FIFO Interrupts - SINGLE_CORE
        2. 37.6.2.2 I2C EEPROM - SINGLE_CORE
        3. 37.6.2.3 I2C Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        4. 37.6.2.4 I2C Extended Clock Stretching Controller TX - SINGLE_CORE
        5. 37.6.2.5 I2C Extended Clock Stretching Target RX - SINGLE_CORE
    7. 37.7 I2C Registers
      1. 37.7.1 I2C Base Address Table
      2. 37.7.2 I2C_REGS Registers
  40. 38Power Management Bus Module (PMBus)
    1. 38.1 Introduction
      1. 38.1.1 PMBUS Related Collateral
      2. 38.1.2 Features
      3. 38.1.3 Block Diagram
    2. 38.2 Configuring Device Pins
    3. 38.3 Target Mode Operation
      1. 38.3.1 Configuration
      2. 38.3.2 Message Handling
        1. 38.3.2.1  Quick Command
        2. 38.3.2.2  Send Byte
        3. 38.3.2.3  Receive Byte
        4. 38.3.2.4  Write Byte and Write Word
        5. 38.3.2.5  Read Byte and Read Word
        6. 38.3.2.6  Process Call
        7. 38.3.2.7  Block Write
        8. 38.3.2.8  Block Read
        9. 38.3.2.9  Block Write-Block Read Process Call
        10. 38.3.2.10 Alert Response
        11. 38.3.2.11 Extended Command
        12. 38.3.2.12 Group Command
    4. 38.4 Controller Mode Operation
      1. 38.4.1 Configuration
      2. 38.4.2 Message Handling
        1. 38.4.2.1  Quick Command
        2. 38.4.2.2  Send Byte
        3. 38.4.2.3  Receive Byte
        4. 38.4.2.4  Write Byte and Write Word
        5. 38.4.2.5  Read Byte and Read Word
        6. 38.4.2.6  Process Call
        7. 38.4.2.7  Block Write
        8. 38.4.2.8  Block Read
        9. 38.4.2.9  Block Write-Block Read Process Call
        10. 38.4.2.10 Alert Response
        11. 38.4.2.11 Extended Command
        12. 38.4.2.12 Group Command
    5. 38.5 Software
      1. 38.5.1 PMBUS Registers to Driverlib Functions
    6. 38.6 PMBUS Registers
      1. 38.6.1 PMBUS Base Address Table
      2. 38.6.2 PMBUS_REGS Registers
  41. 39Universal Asynchronous Receiver/Transmitter (UART)
    1. 39.1 Introduction
      1. 39.1.1 Features
      2. 39.1.2 UART Related Collateral
      3. 39.1.3 Block Diagram
    2. 39.2 Functional Description
      1. 39.2.1 Transmit and Receive Logic
      2. 39.2.2 Baud-Rate Generation
      3. 39.2.3 Data Transmission
      4. 39.2.4 Serial IR (SIR)
      5. 39.2.5 9-Bit UART Mode
      6. 39.2.6 FIFO Operation
      7. 39.2.7 Interrupts
      8. 39.2.8 Loopback Operation
      9. 39.2.9 RTDMA Operation
        1. 39.2.9.1 Receiving Data Using UART with RTDMA
        2. 39.2.9.2 Transmitting Data Using UART with RTDMA
    3. 39.3 Initialization and Configuration
    4. 39.4 Software
      1. 39.4.1 UART Registers to Driverlib Functions
      2. 39.4.2 UART Examples
        1. 39.4.2.1 UART Loopback - SINGLE_CORE
        2. 39.4.2.2 UART Loopback with Interrupt - SINGLE_CORE
        3. 39.4.2.3 UART Loopback with DMA - SINGLE_CORE
        4. 39.4.2.4 UART Echoback - SINGLE_CORE
    5. 39.5 UART Registers
      1. 39.5.1 UART Base Address Table
      2. 39.5.2 UART_REGS Registers
      3. 39.5.3 UART_REGS_WRITE Registers
  42. 40Local Interconnect Network (LIN)
    1. 40.1 LIN Overview
      1. 40.1.1 LIN Mode Features
      2. 40.1.2 SCI Mode Features
      3. 40.1.3 Block Diagram
    2. 40.2 Serial Communications Interface Module
      1. 40.2.1 SCI Communication Formats
        1. 40.2.1.1 SCI Frame Formats
        2. 40.2.1.2 SCI Asynchronous Timing Mode
        3. 40.2.1.3 SCI Baud Rate
          1. 40.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 40.2.1.4 SCI Multiprocessor Communication Modes
          1. 40.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 40.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 40.2.1.5 SCI Multibuffered Mode
      2. 40.2.2 SCI Interrupts
        1. 40.2.2.1 Transmit Interrupt
        2. 40.2.2.2 Receive Interrupt
        3. 40.2.2.3 WakeUp Interrupt
        4. 40.2.2.4 Error Interrupts
      3. 40.2.3 SCI RTDMA Interface
        1. 40.2.3.1 Receive RTDMA Requests
        2. 40.2.3.2 Transmit RTDMA Requests
      4. 40.2.4 SCI Configurations
        1. 40.2.4.1 Receiving Data
          1. 40.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 40.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 40.2.4.2 Transmitting Data
          1. 40.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 40.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 40.2.5 SCI Low-Power Mode
        1. 40.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 40.3 Local Interconnect Network Module
      1. 40.3.1 LIN Communication Formats
        1. 40.3.1.1  LIN Standards
        2. 40.3.1.2  Message Frame
          1. 40.3.1.2.1 Message Header
          2. 40.3.1.2.2 Response
        3. 40.3.1.3  Synchronizer
        4. 40.3.1.4  Baud Rate
          1. 40.3.1.4.1 Fractional Divider
          2. 40.3.1.4.2 Superfractional Divider
            1. 40.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 40.3.1.5  Header Generation
          1. 40.3.1.5.1 Event Triggered Frame Handling
          2. 40.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 40.3.1.6  Extended Frames Handling
        7. 40.3.1.7  Timeout Control
          1. 40.3.1.7.1 No-Response Error (NRE)
          2. 40.3.1.7.2 Bus Idle Detection
          3. 40.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 40.3.1.8  TXRX Error Detector (TED)
          1. 40.3.1.8.1 Bit Errors
          2. 40.3.1.8.2 Physical Bus Errors
          3. 40.3.1.8.3 ID Parity Errors
          4. 40.3.1.8.4 Checksum Errors
        9. 40.3.1.9  Message Filtering and Validation
        10. 40.3.1.10 Receive Buffers
        11. 40.3.1.11 Transmit Buffers
      2. 40.3.2 LIN Interrupts
      3. 40.3.3 Servicing LIN Interrupts
      4. 40.3.4 LIN RTDMA Interface
        1. 40.3.4.1 LIN Receive RTDMA Requests
        2. 40.3.4.2 LIN Transmit RTDMA Requests
      5. 40.3.5 LIN Configurations
        1. 40.3.5.1 Receiving Data
          1. 40.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 40.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 40.3.5.2 Transmitting Data
          1. 40.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 40.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 40.4 Low-Power Mode
      1. 40.4.1 Entering Sleep Mode
      2. 40.4.2 Wakeup
      3. 40.4.3 Wakeup Timeouts
    5. 40.5 Emulation Mode
    6. 40.6 Software
      1. 40.6.1 LIN Registers to Driverlib Functions
      2. 40.6.2 LIN Examples
        1. 40.6.2.1 LIN Internal Loopback with Interrupts - SINGLE_CORE
        2. 40.6.2.2 LIN SCI Mode Internal Loopback with Interrupts - SINGLE_CORE
        3. 40.6.2.3 LIN SCI MODE Internal Loopback with DMA - SINGLE_CORE
        4. 40.6.2.4 LIN Internal Loopback without interrupts (polled mode) - SINGLE_CORE
        5. 40.6.2.5 LIN SCI MODE (Single Buffer) Internal Loopback with DMA - SINGLE_CORE
    7. 40.7 LIN Registers
      1. 40.7.1 LIN Base Address Table
      2. 40.7.2 LIN_REGS Registers
  43. 41Serial Peripheral Interface (SPI)
    1. 41.1 Introduction
      1. 41.1.1 Features
      2. 41.1.2 Block Diagram
    2. 41.2 System-Level Integration
      1. 41.2.1 SPI Module Signals
      2. 41.2.2 Configuring Device Pins
        1. 41.2.2.1 GPIOs Required for High-Speed Mode
      3. 41.2.3 SPI Interrupts
      4. 41.2.4 RTDMA Support
    3. 41.3 SPI Operation
      1. 41.3.1  Introduction to Operation
      2. 41.3.2  Controller Mode
      3. 41.3.3  Peripheral Mode
      4. 41.3.4  Data Format
        1. 41.3.4.1 Transmission of Bit from SPIRXBUF
      5. 41.3.5  Baud Rate Selection
        1. 41.3.5.1 Baud Rate Determination
        2. 41.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
        3. 41.3.5.3 Baud Rate Calculation
      6. 41.3.6  SPI Clocking Schemes
      7. 41.3.7  SPI FIFO Description
      8. 41.3.8  SPI RTDMA Transfers
        1. 41.3.8.1 Transmitting Data Using SPI with RTDMA
        2. 41.3.8.2 Receiving Data Using SPI with RTDMA
      9. 41.3.9  SPI High-Speed Mode
      10. 41.3.10 SPI 3-Wire Mode Description
    4. 41.4 Programming Procedure
      1. 41.4.1 Initialization Upon Reset
      2. 41.4.2 Configuring the SPI
      3. 41.4.3 Configuring the SPI for High-Speed Mode
      4. 41.4.4 Data Transfer Example
      5. 41.4.5 SPI 3-Wire Mode Code Examples
        1. 41.4.5.1 3-Wire Controller Mode Transmit
        2.       1703
          1. 41.4.5.2.1 3-Wire Controller Mode Receive
        3.       1705
          1. 41.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       1707
          1. 41.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 41.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 41.5 Software
      1. 41.5.1 SPI Registers to Driverlib Functions
      2. 41.5.2 SPI Examples
        1. 41.5.2.1 SPI Digital Loopback - SINGLE_CORE
        2. 41.5.2.2 SPI Digital Loopback with FIFO Interrupts - SINGLE_CORE
        3. 41.5.2.3 SPI Digital External Loopback without FIFO Interrupts - SINGLE_CORE
        4. 41.5.2.4 SPI Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        5. 41.5.2.5 SPI Digital Loopback with DMA - SINGLE_CORE
    6. 41.6 SPI Registers
      1. 41.6.1 SPI Base Address Table
      2. 41.6.2 SPI_REGS Registers
  44. 42Single Edge Nibble Transmission (SENT)
    1. 42.1 Introduction
      1. 42.1.1 Features
      2. 42.1.2 SENT Related Collateral
    2. 42.2 Advanced Topologies: MTPG
      1. 42.2.1 MTPG Features
      2. 42.2.2 MTPG Description
      3. 42.2.3 Channel Triggers
      4. 42.2.4 Timeout
    3. 42.3 Protocol Description
      1. 42.3.1 Nibble Frame Format
      2. 42.3.2 CRC
      3. 42.3.3 Short Serial Message Format
      4. 42.3.4 Enhanced Serial Message Format
      5. 42.3.5 Enhanced Serial Message Format CRC
      6. 42.3.6 Receive Modes
    4. 42.4 RTDMA Trigger
    5. 42.5 Interrupts Configuration
    6. 42.6 Glitch Filter
    7. 42.7 Software
      1. 42.7.1 SENT Registers to Driverlib Functions
      2. 42.7.2 SENT Examples
        1. 42.7.2.1 SENT Single Sensor - SINGLE_CORE
    8. 42.8 SENT Registers
      1. 42.8.1 SENT Base Address Table
      2. 42.8.2 SENT_CFG Registers
      3. 42.8.3 SENT_MEM Registers
      4. 42.8.4 SENT_MTPG Registers
  45. 43â–º SECURITY PERIPHERALS
    1.     Technical Reference Manual Overview
  46. 44Security Modules
    1. 44.1 Hardware Security Module (HSM)
      1. 44.1.1 HSM Related Collateral
    2. 44.2 Cryptographic Accelerators
  47. 45Revision History

20.5.9 XBAR_REGS Registers

Table 20-84 lists the memory-mapped registers for the XBAR_REGS registers. All register offset addresses not listed in Table 20-84 should be considered as reserved locations and the register contents should not be modified.

Table 20-84 XBAR_REGS Registers
OffsetAcronymRegister NameProtection
0hXBARFLG1X-Bar Input Flag Register 1
4hXBARFLG2X-Bar Input Flag Register 2
8hXBARFLG3X-Bar Input Flag Register 3
ChXBARFLG4X-Bar Input Flag Register 4
10hXBARFLG5X-Bar Input Flag Register 5
14hXBARFLG6X-Bar Input Flag Register 6
18hXBARFLG7X-Bar Input Flag Register 7
1ChXBARFLG8X-Bar Input Flag Register 8
20hXBARFLG9X-Bar Input Flag Register 9
24hXBARFLG10X-Bar Input Flag Register 10
28hXBARFLG11X-Bar Input Flag Register 11
2ChXBARFLG12X-Bar Input Flag Register 12
30hXBARFLG13X-Bar Input Flag Register 13
34hXBARFLG14X-Bar Input Flag Register 14
38hXBARFLG15X-Bar Input Flag Register 15
3ChXBARFLG16X-Bar Input Flag Register 16
40hXBARFLG17X-Bar Input Flag Register 16
44hXBARFLG18X-Bar Input Flag Register 16
100hXBARCLR1X-Bar Input Flag Clear Register 1
104hXBARCLR2X-Bar Input Flag Clear Register 2
108hXBARCLR3X-Bar Input Flag Clear Register 3
10ChXBARCLR4X-Bar Input Flag Clear Register 4
110hXBARCLR5X-Bar Input Flag Clear Register 5
114hXBARCLR6X-Bar Input Flag Clear Register 6
118hXBARCLR7X-Bar Input Flag Clear Register 7
11ChXBARCLR8X-Bar Input Flag Clear Register 8
120hXBARCLR9X-Bar Input Flag Clear Register 9
124hXBARCLR10X-Bar Input Flag Clear Register 10
128hXBARCLR11X-Bar Input Flag Clear Register 11
12ChXBARCLR12X-Bar Input Flag Clear Register 12
130hXBARCLR13X-Bar Input Flag Clear Register 13
134hXBARCLR14X-Bar Input Flag Clear Register 14
138hXBARCLR15X-Bar Input Flag Clear Register 15
13ChXBARCLR16X-Bar Input Flag Clear Register 15
140hXBARCLR17X-Bar Input Flag Clear Register 16
144hXBARCLR18X-Bar Input Flag Clear Register 16

Complex bit access types are encoded to fit into small table cells. Table 20-85 shows the codes that are used for access types in this section.

Table 20-85 XBAR_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

20.5.9.1 XBARFLG1 Register (Offset = 0h) [Reset = 00000000h]

XBARFLG1 is shown in Figure 20-63 and described in Table 20-86.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-63 XBARFLG1 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
CMPSS12_CTRIPLCMPSS12_CTRIPHCMPSS11_CTRIPLCMPSS11_CTRIPHCMPSS10_CTRIPLCMPSS10_CTRIPHCMPSS9_CTRIPLCMPSS9_CTRIPH
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
CMPSS8_CTRIPHCMPSS8_CTRIPLCMPSS7_CTRIPHCMPSS7_CTRIPLCMPSS6_CTRIPHCMPSS6_CTRIPLCMPSS5_CTRIPHCMPSS5_CTRIPL
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
CMPSS4_CTRIPHCMPSS4_CTRIPLCMPSS3_CTRIPHCMPSS3_CTRIPLCMPSS2_CTRIPHCMPSS2_CTRIPLCMPSS1_CTRIPHCMPSS1_CTRIPL
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-86 XBARFLG1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30RESERVEDR0hReserved
29RESERVEDR0hReserved
28RESERVEDR0hReserved
27RESERVEDR0hReserved
26RESERVEDR0hReserved
25RESERVEDR0hReserved
24RESERVEDR0hReserved
23CMPSS12_CTRIPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS12_CTRIPL input was triggered
0: CMPSS12_CTRIPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

22CMPSS12_CTRIPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS12_CTRIPH input was triggered
0: CMPSS12_CTRIPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

21CMPSS11_CTRIPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS11_CTRIPL input was triggered
0: CMPSS11_CTRIPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20CMPSS11_CTRIPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS11_CTRIPH input was triggered
0: CMPSS11_CTRIPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

19CMPSS10_CTRIPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS10_CTRIPL input was triggered
0: CMPSS10_CTRIPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

18CMPSS10_CTRIPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS10_CTRIPH input was triggered
0: CMPSS10_CTRIPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

17CMPSS9_CTRIPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS9_CTRIPL input was triggered
0: CMPSS9_CTRIPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16CMPSS9_CTRIPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS9_CTRIPH input was triggered
0: CMPSS9_CTRIPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15CMPSS8_CTRIPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS8_CTRIPH input was triggered
0: CMPSS8_CTRIPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14CMPSS8_CTRIPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS8_CTRIPL input was triggered
0: CMPSS8_CTRIPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13CMPSS7_CTRIPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS7_CTRIPH input was triggered
0: CMPSS7_CTRIPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12CMPSS7_CTRIPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS7_CTRIPL input was triggered
0: CMPSS7_CTRIPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11CMPSS6_CTRIPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS6_CTRIPH input was triggered
0: CMPSS6_CTRIPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10CMPSS6_CTRIPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS6_CTRIPL input was triggered
0: CMPSS6_CTRIPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9CMPSS5_CTRIPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS5_CTRIPH input was triggered
0: CMPSS5_CTRIPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8CMPSS5_CTRIPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS5_CTRIPL input was triggered
0: CMPSS5_CTRIPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7CMPSS4_CTRIPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS4_CTRIPH input was triggered
0: CMPSS4_CTRIPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6CMPSS4_CTRIPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS4_CTRIPL input was triggered
0: CMPSS4_CTRIPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5CMPSS3_CTRIPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS3_CTRIPH input was triggered
0: CMPSS3_CTRIPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4CMPSS3_CTRIPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS3_CTRIPL input was triggered
0: CMPSS3_CTRIPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3CMPSS2_CTRIPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS2_CTRIPH input was triggered
0: CMPSS2_CTRIPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2CMPSS2_CTRIPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS2_CTRIPL input was triggered
0: CMPSS2_CTRIPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1CMPSS1_CTRIPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS1_CTRIPH input was triggered
0: CMPSS1_CTRIPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0CMPSS1_CTRIPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS1_CTRIPL input was triggered
0: CMPSS1_CTRIPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.2 XBARFLG2 Register (Offset = 4h) [Reset = 00000000h]

XBARFLG2 is shown in Figure 20-64 and described in Table 20-87.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-64 XBARFLG2 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
CMPSS12_CTRIPOUTLCMPSS12_CTRIPOUTHCMPSS11_CTRIPOUTLCMPSS11_CTRIPOUTHCMPSS10_CTRIPOUTLCMPSS10_CTRIPOUTHCMPSS9_CTRIPOUTLCMPSS9_CTRIPOUTH
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
CMPSS8_CTRIPOUTHCMPSS8_CTRIPOUTLCMPSS7_CTRIPOUTHCMPSS7_CTRIPOUTLCMPSS6_CTRIPOUTHCMPSS6_CTRIPOUTLCMPSS5_CTRIPOUTHCMPSS5_CTRIPOUTL
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
CMPSS4_CTRIPOUTHCMPSS4_CTRIPOUTLCMPSS3_CTRIPOUTHCMPSS3_CTRIPOUTLCMPSS2_CTRIPOUTHCMPSS2_CTRIPOUTLCMPSS1_CTRIPOUTHCMPSS1_CTRIPOUTL
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-87 XBARFLG2 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30RESERVEDR0hReserved
29RESERVEDR0hReserved
28RESERVEDR0hReserved
27RESERVEDR0hReserved
26RESERVEDR0hReserved
25RESERVEDR0hReserved
24RESERVEDR0hReserved
23CMPSS12_CTRIPOUTLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS12_CTRIPOUTL input was triggered
0: CMPSS12_CTRIPOUTL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

22CMPSS12_CTRIPOUTHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS12_CTRIPOUTH input was triggered
0: CMPSS12_CTRIPOUTH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

21CMPSS11_CTRIPOUTLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS11_CTRIPOUTL input was triggered
0: CMPSS11_CTRIPOUTL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20CMPSS11_CTRIPOUTHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS11_CTRIPOUTH input was triggered
0: CMPSS11_CTRIPOUTH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

19CMPSS10_CTRIPOUTLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS10_CTRIPOUTL input was triggered
0: CMPSS10_CTRIPOUTL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

18CMPSS10_CTRIPOUTHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS10_CTRIPOUTH input was triggered
0: CMPSS10_CTRIPOUTH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

17CMPSS9_CTRIPOUTLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS9_CTRIPOUTL input was triggered
0: CMPSS9_CTRIPOUTL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16CMPSS9_CTRIPOUTHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS9_CTRIPOUTH input was triggered
0: CMPSS9_CTRIPOUTH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15CMPSS8_CTRIPOUTHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS8_CTRIPOUTH input was triggered
0: CMPSS8_CTRIPOUTH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14CMPSS8_CTRIPOUTLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS8_CTRIPOUTL input was triggered
0: CMPSS8_CTRIPOUTL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13CMPSS7_CTRIPOUTHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS7_CTRIPOUTH input was triggered
0: CMPSS7_CTRIPOUTH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12CMPSS7_CTRIPOUTLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS7_CTRIPOUTL input was triggered
0: CMPSS7_CTRIPOUTL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11CMPSS6_CTRIPOUTHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS6_CTRIPOUTH input was triggered
0: CMPSS6_CTRIPOUTH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10CMPSS6_CTRIPOUTLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS6_CTRIPOUTL input was triggered
0: CMPSS6_CTRIPOUTL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9CMPSS5_CTRIPOUTHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS5_CTRIPOUTH input was triggered
0: CMPSS5_CTRIPOUTH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8CMPSS5_CTRIPOUTLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS5_CTRIPOUTL input was triggered
0: CMPSS5_CTRIPOUTL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7CMPSS4_CTRIPOUTHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS4_CTRIPOUTH input was triggered
0: CMPSS4_CTRIPOUTH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6CMPSS4_CTRIPOUTLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS4_CTRIPOUTL input was triggered
0: CMPSS4_CTRIPOUTL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5CMPSS3_CTRIPOUTHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS3_CTRIPOUTH input was triggered
0: CMPSS3_CTRIPOUTH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4CMPSS3_CTRIPOUTLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS3_CTRIPOUTL input was triggered
0: CMPSS3_CTRIPOUTL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3CMPSS2_CTRIPOUTHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS2_CTRIPOUTH input was triggered
0: CMPSS2_CTRIPOUTH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2CMPSS2_CTRIPOUTLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS2_CTRIPOUTL input was triggered
0: CMPSS2_CTRIPOUTL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1CMPSS1_CTRIPOUTHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS1_CTRIPOUTH input was triggered
0: CMPSS1_CTRIPOUTH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0CMPSS1_CTRIPOUTLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CMPSS1_CTRIPOUTL input was triggered
0: CMPSS1_CTRIPOUTL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.3 XBARFLG3 Register (Offset = 8h) [Reset = 00000000h]

XBARFLG3 is shown in Figure 20-65 and described in Table 20-88.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-65 XBARFLG3 Register
3130292827262524
SD4FLT4_COMPLSD4FLT4_COMPHSD4FLT3_COMPLSD4FLT3_COMPHSD4FLT2_COMPLSD4FLT2_COMPHSD4FLT1_COMPLSD4FLT1_COMPH
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
SD3FLT4_COMPLSD3FLT4_COMPHSD3FLT3_COMPLSD3FLT3_COMPHSD3FLT2_COMPLSD3FLT2_COMPHSD3FLT1_COMPLSD3FLT1_COMPH
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
SD2FLT4_COMPHSD2FLT4_COMPLSD2FLT3_COMPHSD2FLT3_COMPLSD2FLT2_COMPHSD2FLT2_COMPLSD2FLT1_COMPHSD2FLT1_COMPL
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
SD1FLT4_COMPHSD1FLT4_COMPLSD1FLT3_COMPHSD1FLT3_COMPLSD1FLT2_COMPHSD1FLT2_COMPLSD1FLT1_COMPHSD1FLT1_COMPL
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-88 XBARFLG3 Register Field Descriptions
BitFieldTypeResetDescription
31SD4FLT4_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD4FLT4_COMPL input was triggered
0: SD4FLT4_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

30SD4FLT4_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD4FLT4_COMPH input was triggered
0: SD4FLT4_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

29SD4FLT3_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD4FLT3_COMPL input was triggered
0: SD4FLT3_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

28SD4FLT3_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD4FLT3_COMPH input was triggered
0: SD4FLT3_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

27SD4FLT2_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD4FLT2_COMPL input was triggered
0: SD4FLT2_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

26SD4FLT2_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD4FLT2_COMPH input was triggered
0: SD4FLT2_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

25SD4FLT1_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD4FLT1_COMPL input was triggered
0: SD4FLT1_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

24SD4FLT1_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD4FLT1_COMPH input was triggered
0: SD4FLT1_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

23SD3FLT4_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD3FLT4_COMPL input was triggered
0: SD3FLT4_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

22SD3FLT4_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD3FLT4_COMPH input was triggered
0: SD3FLT4_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

21SD3FLT3_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD3FLT3_COMPL input was triggered
0: SD3FLT3_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20SD3FLT3_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD3FLT3_COMPH input was triggered
0: SD3FLT3_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

19SD3FLT2_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD3FLT2_COMPL input was triggered
0: SD3FLT2_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

18SD3FLT2_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD3FLT2_COMPH input was triggered
0: SD3FLT2_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

17SD3FLT1_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD3FLT1_COMPL input was triggered
0: SD3FLT1_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16SD3FLT1_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD3FLT1_COMPH input was triggered
0: SD3FLT1_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15SD2FLT4_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD2FLT4_COMPH input was triggered
0: SD2FLT4_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14SD2FLT4_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD2FLT4_COMPL input was triggered
0: SD2FLT4_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13SD2FLT3_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD2FLT3_COMPH input was triggered
0: SD2FLT3_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12SD2FLT3_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD2FLT3_COMPL input was triggered
0: SD2FLT3_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11SD2FLT2_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD2FLT2_COMPH input was triggered
0: SD2FLT2_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10SD2FLT2_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD2FLT2_COMPL input was triggered
0: SD2FLT2_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9SD2FLT1_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD2FLT1_COMPH input was triggered
0: SD2FLT1_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8SD2FLT1_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD2FLT1_COMPL input was triggered
0: SD2FLT1_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7SD1FLT4_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD1FLT4_COMPH input was triggered
0: SD1FLT4_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6SD1FLT4_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD1FLT4_COMPL input was triggered
0: SD1FLT4_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5SD1FLT3_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD1FLT3_COMPH input was triggered
0: SD1FLT3_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4SD1FLT3_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD1FLT3_COMPL input was triggered
0: SD1FLT3_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3SD1FLT2_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD1FLT2_COMPH input was triggered
0: SD1FLT2_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2SD1FLT2_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD1FLT2_COMPL input was triggered
0: SD1FLT2_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1SD1FLT1_COMPHR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD1FLT1_COMPH input was triggered
0: SD1FLT1_COMPH Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0SD1FLT1_COMPLR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: SD1FLT1_COMPL input was triggered
0: SD1FLT1_COMPL Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.4 XBARFLG4 Register (Offset = Ch) [Reset = 00000000h]

XBARFLG4 is shown in Figure 20-66 and described in Table 20-89.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-66 XBARFLG4 Register
3130292827262524
INPUT32INPUT31INPUT30INPUT29INPUT28INPUT27INPUT26INPUT25
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
INPUT24INPUT23INPUT22INPUT21INPUT20INPUT19INPUT18INPUT17
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
INPUT16INPUT15INPUT14INPUT13INPUT12INPUT11INPUT10INPUT9
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
INPUT8INPUT7INPUT6INPUT5INPUT4INPUT3INPUT2INPUT1
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-89 XBARFLG4 Register Field Descriptions
BitFieldTypeResetDescription
31INPUT32R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT32 input was triggered
0: INPUT32 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

30INPUT31R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT31 input was triggered
0: INPUT31 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

29INPUT30R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT30 input was triggered
0: INPUT30 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

28INPUT29R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT29 input was triggered
0: INPUT29 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

27INPUT28R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT28 input was triggered
0: INPUT28 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

26INPUT27R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT27 input was triggered
0: INPUT27 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

25INPUT26R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT26 input was triggered
0: INPUT26 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

24INPUT25R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT25 input was triggered
0: INPUT25 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

23INPUT24R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT24 input was triggered
0: INPUT24 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

22INPUT23R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT23 input was triggered
0: INPUT23 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

21INPUT22R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT22 input was triggered
0: INPUT22 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20INPUT21R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT21 input was triggered
0: INPUT21 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

19INPUT20R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT20 input was triggered
0: INPUT20 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

18INPUT19R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT19 input was triggered
0: INPUT19 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

17INPUT18R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT18 input was triggered
0: INPUT18 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16INPUT17R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT17 input was triggered
0: INPUT17 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15INPUT16R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT16 input was triggered
0: INPUT16 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14INPUT15R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT15 input was triggered
0: INPUT15 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13INPUT14R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT14 input was triggered
0: INPUT14 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12INPUT13R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT13 input was triggered
0: INPUT13 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11INPUT12R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT12 input was triggered
0: INPUT12 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10INPUT11R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT11 input was triggered
0: INPUT11 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9INPUT10R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT10 input was triggered
0: INPUT10 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8INPUT9R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT9 input was triggered
0: INPUT9 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7INPUT8R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT8 input was triggered
0: INPUT8 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6INPUT7R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT7 input was triggered
0: INPUT7 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5INPUT6R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT6 input was triggered
0: INPUT6 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4INPUT5R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT5 input was triggered
0: INPUT5 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3INPUT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT4 input was triggered
0: INPUT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2INPUT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT3 input was triggered
0: INPUT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1INPUT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT2 input was triggered
0: INPUT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0INPUT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: INPUT1 input was triggered
0: INPUT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.5 XBARFLG5 Register (Offset = 10h) [Reset = 00000000h]

XBARFLG5 is shown in Figure 20-67 and described in Table 20-90.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-67 XBARFLG5 Register
3130292827262524
CPU3_ADCCHECKEVT4CPU3_ADCCHECKEVT3CPU3_ADCCHECKEVT2CPU3_ADCCHECKEVT1CPU2_ADCCHECKEVT4CPU2_ADCCHECKEVT3CPU2_ADCCHECKEVT2CPU2_ADCCHECKEVT1
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
CPU1_ADCCHECKEVT4CPU1_ADCCHECKEVT3CPU1_ADCCHECKEVT2CPU1_ADCCHECKEVT1ADCEEVT4ADCEEVT3ADCEEVT2ADCEEVT1
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
ADCDEVT4ADCDEVT3ADCDEVT2ADCDEVT1ADCCEVT4ADCCEVT3ADCCEVT2ADCCEVT1
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
ADCBEVT4ADCBEVT3ADCBEVT2ADCBEVT1ADCAEVT4ADCAEVT3ADCAEVT2ADCAEVT1
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-90 XBARFLG5 Register Field Descriptions
BitFieldTypeResetDescription
31CPU3_ADCCHECKEVT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU3_ADCCHECKEVT4 input was triggered
0: CPU3_ADCCHECKEVT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

30CPU3_ADCCHECKEVT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU3_ADCCHECKEVT3 input was triggered
0: CPU3_ADCCHECKEVT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

29CPU3_ADCCHECKEVT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU3_ADCCHECKEVT2 input was triggered
0: CPU3_ADCCHECKEVT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

28CPU3_ADCCHECKEVT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU3_ADCCHECKEVT1 input was triggered
0: CPU3_ADCCHECKEVT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

27CPU2_ADCCHECKEVT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU2_ADCCHECKEVT4 input was triggered
0: CPU2_ADCCHECKEVT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

26CPU2_ADCCHECKEVT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU2_ADCCHECKEVT3 input was triggered
0: CPU2_ADCCHECKEVT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

25CPU2_ADCCHECKEVT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU2_ADCCHECKEVT2 input was triggered
0: CPU2_ADCCHECKEVT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

24CPU2_ADCCHECKEVT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU2_ADCCHECKEVT1 input was triggered
0: CPU2_ADCCHECKEVT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

23CPU1_ADCCHECKEVT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU1_ADCCHECKEVT4 input was triggered
0: CPU1_ADCCHECKEVT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

22CPU1_ADCCHECKEVT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU1_ADCCHECKEVT3 input was triggered
0: CPU1_ADCCHECKEVT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

21CPU1_ADCCHECKEVT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU1_ADCCHECKEVT2 input was triggered
0: CPU1_ADCCHECKEVT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20CPU1_ADCCHECKEVT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU1_ADCCHECKEVT1 input was triggered
0: CPU1_ADCCHECKEVT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

19ADCEEVT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCEEVT4 input was triggered
0: ADCEEVT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

18ADCEEVT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCEEVT3 input was triggered
0: ADCEEVT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

17ADCEEVT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCEEVT2 input was triggered
0: ADCEEVT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16ADCEEVT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCEEVT1 input was triggered
0: ADCEEVT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15ADCDEVT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCDEVT4 input was triggered
0: ADCDEVT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14ADCDEVT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCDEVT3 input was triggered
0: ADCDEVT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13ADCDEVT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCDEVT2 input was triggered
0: ADCDEVT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12ADCDEVT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCDEVT1 input was triggered
0: ADCDEVT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11ADCCEVT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCCEVT4 input was triggered
0: ADCCEVT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10ADCCEVT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCCEVT3 input was triggered
0: ADCCEVT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9ADCCEVT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCCEVT2 input was triggered
0: ADCCEVT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8ADCCEVT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCCEVT1 input was triggered
0: ADCCEVT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7ADCBEVT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCBEVT4 input was triggered
0: ADCBEVT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6ADCBEVT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCBEVT3 input was triggered
0: ADCBEVT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5ADCBEVT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCBEVT2 input was triggered
0: ADCBEVT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4ADCBEVT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCBEVT1 input was triggered
0: ADCBEVT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3ADCAEVT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCAEVT4 input was triggered
0: ADCAEVT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2ADCAEVT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCAEVT3 input was triggered
0: ADCAEVT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1ADCAEVT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCAEVT2 input was triggered
0: ADCAEVT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0ADCAEVT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCAEVT1 input was triggered
0: ADCAEVT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.6 XBARFLG6 Register (Offset = 14h) [Reset = 00000000h]

XBARFLG6 is shown in Figure 20-68 and described in Table 20-91.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-68 XBARFLG6 Register
3130292827262524
ECATSYNC1ECATSYNC0WADI1OUT7WADI1OUT6WADI1OUT5WADI1OUT4WADI1OUT3WADI1OUT2
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
WADI1OUT1WADI1OUT0RESERVEDRESERVEDFSID_RX_TRIG1FSIC_RX_TRIG1FSIB_RX_TRIG1FSIA_RX_TRIG1
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDCLB6_OUT5CLB6_OUT4CLB5_OUT5CLB5_OUT4
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
CLB4_OUT5CLB4_OUT4CLB3_OUT5CLB3_OUT4CLB2_OUT5CLB2_OUT4CLB1_OUT5CLB1_OUT4
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-91 XBARFLG6 Register Field Descriptions
BitFieldTypeResetDescription
31ECATSYNC1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ECATSYNC1 input was triggered
0: ECATSYNC1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

30ECATSYNC0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ECATSYNC0 input was triggered
0: ECATSYNC0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

29WADI1OUT7R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI1OUT7 input was triggered
0: WADI1OUT7 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

28WADI1OUT6R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI1OUT6 input was triggered
0: WADI1OUT6 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

27WADI1OUT5R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI1OUT5 input was triggered
0: WADI1OUT5 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

26WADI1OUT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI1OUT4 input was triggered
0: WADI1OUT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

25WADI1OUT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI1OUT3 input was triggered
0: WADI1OUT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

24WADI1OUT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI1OUT2 input was triggered
0: WADI1OUT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

23WADI1OUT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI1OUT1 input was triggered
0: WADI1OUT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

22WADI1OUT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI1OUT0 input was triggered
0: WADI1OUT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

21RESERVEDR0hReserved
20RESERVEDR0hReserved
19FSID_RX_TRIG1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSID_RX_TRIG1 input was triggered
0: FSID_RX_TRIG1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

18FSIC_RX_TRIG1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIC_RX_TRIG1 input was triggered
0: FSIC_RX_TRIG1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

17FSIB_RX_TRIG1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIB_RX_TRIG1 input was triggered
0: FSIB_RX_TRIG1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16FSIA_RX_TRIG1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIA_RX_TRIG1 input was triggered
0: FSIA_RX_TRIG1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15RESERVEDR0hReserved
14RESERVEDR0hReserved
13RESERVEDR0hReserved
12RESERVEDR0hReserved
11CLB6_OUT5R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB6_OUT5 input was triggered
0: CLB6_OUT5 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10CLB6_OUT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB6_OUT4 input was triggered
0: CLB6_OUT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9CLB5_OUT5R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB5_OUT5 input was triggered
0: CLB5_OUT5 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8CLB5_OUT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB5_OUT4 input was triggered
0: CLB5_OUT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7CLB4_OUT5R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB4_OUT5 input was triggered
0: CLB4_OUT5 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6CLB4_OUT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB4_OUT4 input was triggered
0: CLB4_OUT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5CLB3_OUT5R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB3_OUT5 input was triggered
0: CLB3_OUT5 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4CLB3_OUT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB3_OUT4 input was triggered
0: CLB3_OUT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3CLB2_OUT5R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB2_OUT5 input was triggered
0: CLB2_OUT5 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2CLB2_OUT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB2_OUT4 input was triggered
0: CLB2_OUT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1CLB1_OUT5R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB1_OUT5 input was triggered
0: CLB1_OUT5 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0CLB1_OUT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB1_OUT4 input was triggered
0: CLB1_OUT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.7 XBARFLG7 Register (Offset = 18h) [Reset = 00000000h]

XBARFLG7 is shown in Figure 20-69 and described in Table 20-92.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-69 XBARFLG7 Register
3130292827262524
WADI2OUT7WADI2OUT6WADI2OUT5WADI2OUT4WADI2OUT3WADI2OUT2WADI2OUT1WADI2OUT0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDEXTSYNCOUTESMGENEVTADCSOCBADCSOCA
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVEDRESERVEDECAP6_TRIPOUTECAP5_TRIPOUTECAP4_TRIPOUTECAP3_TRIPOUTECAP2_TRIPOUTECAP1_TRIPOUT
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDRESERVEDECAP6_OUTECAP5_OUTECAP4_OUTECAP3_OUTECAP2_OUTECAP1_OUT
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-92 XBARFLG7 Register Field Descriptions
BitFieldTypeResetDescription
31WADI2OUT7R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI2OUT7 input was triggered
0: WADI2OUT7 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

30WADI2OUT6R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI2OUT6 input was triggered
0: WADI2OUT6 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

29WADI2OUT5R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI2OUT5 input was triggered
0: WADI2OUT5 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

28WADI2OUT4R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI2OUT4 input was triggered
0: WADI2OUT4 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

27WADI2OUT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI2OUT3 input was triggered
0: WADI2OUT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

26WADI2OUT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI2OUT2 input was triggered
0: WADI2OUT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

25WADI2OUT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI2OUT1 input was triggered
0: WADI2OUT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

24WADI2OUT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: WADI2OUT0 input was triggered
0: WADI2OUT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

23RESERVEDR0hReserved
22RESERVEDR0hReserved
21RESERVEDR0hReserved
20RESERVEDR0hReserved
19EXTSYNCOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EXTSYNCOUT input was triggered
0: EXTSYNCOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

18ESMGENEVTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ESMGENEVT input was triggered
0: ESMGENEVT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

17ADCSOCBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCSOCB input was triggered
0: ADCSOCB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16ADCSOCAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCSOCA input was triggered
0: ADCSOCA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15RESERVEDR0hReserved
14RESERVEDR0hReserved
13ECAP6_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ECAP6_TRIPOUT input was triggered
0: ECAP6_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12ECAP5_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ECAP5_TRIPOUT input was triggered
0: ECAP5_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11ECAP4_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ECAP4_TRIPOUT input was triggered
0: ECAP4_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10ECAP3_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ECAP3_TRIPOUT input was triggered
0: ECAP3_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9ECAP2_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ECAP2_TRIPOUT input was triggered
0: ECAP2_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8ECAP1_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ECAP1_TRIPOUT input was triggered
0: ECAP1_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7RESERVEDR0hReserved
6RESERVEDR0hReserved
5ECAP6_OUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ECAP6_OUT input was triggered
0: ECAP6_OUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4ECAP5_OUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ECAP5_OUT input was triggered
0: ECAP5_OUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3ECAP4_OUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ECAP4_OUT input was triggered
0: ECAP4_OUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2ECAP3_OUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ECAP3_OUT input was triggered
0: ECAP3_OUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1ECAP2_OUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ECAP2_OUT input was triggered
0: ECAP2_OUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0ECAP1_OUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ECAP1_OUT input was triggered
0: ECAP1_OUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.8 XBARFLG8 Register (Offset = 1Ch) [Reset = 00000000h]

XBARFLG8 is shown in Figure 20-70 and described in Table 20-93.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-70 XBARFLG8 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDEPWM18_TRIPOUTEPWM17_TRIPOUT
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
EPWM16_TRIPOUTEPWM15_TRIPOUTEPWM14_TRIPOUTEPWM13_TRIPOUTEPWM12_TRIPOUTEPWM11_TRIPOUTEPWM10_TRIPOUTEPWM9_TRIPOUT
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
EPWM8_TRIPOUTEPWM7_TRIPOUTEPWM6_TRIPOUTEPWM5_TRIPOUTEPWM4_TRIPOUTEPWM3_TRIPOUTEPWM2_TRIPOUTEPWM1_TRIPOUT
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-93 XBARFLG8 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30RESERVEDR0hReserved
29RESERVEDR0hReserved
28RESERVEDR0hReserved
27RESERVEDR0hReserved
26RESERVEDR0hReserved
25RESERVEDR0hReserved
24RESERVEDR0hReserved
23RESERVEDR0hReserved
22RESERVEDR0hReserved
21RESERVEDR0hReserved
20RESERVEDR0hReserved
19RESERVEDR0hReserved
18RESERVEDR0hReserved
17EPWM18_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM18_TRIPOUT input was triggered
0: EPWM18_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16EPWM17_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM17_TRIPOUT input was triggered
0: EPWM17_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15EPWM16_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM16_TRIPOUT input was triggered
0: EPWM16_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14EPWM15_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM15_TRIPOUT input was triggered
0: EPWM15_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13EPWM14_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM14_TRIPOUT input was triggered
0: EPWM14_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12EPWM13_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM13_TRIPOUT input was triggered
0: EPWM13_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11EPWM12_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM12_TRIPOUT input was triggered
0: EPWM12_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10EPWM11_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM11_TRIPOUT input was triggered
0: EPWM11_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9EPWM10_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM10_TRIPOUT input was triggered
0: EPWM10_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8EPWM9_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM9_TRIPOUT input was triggered
0: EPWM9_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7EPWM8_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM8_TRIPOUT input was triggered
0: EPWM8_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6EPWM7_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM7_TRIPOUT input was triggered
0: EPWM7_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5EPWM6_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM6_TRIPOUT input was triggered
0: EPWM6_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4EPWM5_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM5_TRIPOUT input was triggered
0: EPWM5_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3EPWM4_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM4_TRIPOUT input was triggered
0: EPWM4_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2EPWM3_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM3_TRIPOUT input was triggered
0: EPWM3_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1EPWM2_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM2_TRIPOUT input was triggered
0: EPWM2_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0EPWM1_TRIPOUTR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM1_TRIPOUT input was triggered
0: EPWM1_TRIPOUT Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.9 XBARFLG9 Register (Offset = 20h) [Reset = 00000000h]

XBARFLG9 is shown in Figure 20-71 and described in Table 20-94.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-71 XBARFLG9 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDEPWM18_DEL_TRIPEPWM17_DEL_TRIP
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
EPWM16_DEL_TRIPEPWM15_DEL_TRIPEPWM14_DEL_TRIPEPWM13_DEL_TRIPEPWM12_DEL_TRIPEPWM11_DEL_TRIPEPWM10_DEL_TRIPEPWM9_DEL_TRIP
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
EPWM8_DEL_TRIPEPWM7_DEL_TRIPEPWM6_DEL_TRIPEPWM5_DEL_TRIPEPWM4_DEL_TRIPEPWM3_DEL_TRIPEPWM2_DEL_TRIPEPWM1_DEL_TRIP
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-94 XBARFLG9 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30RESERVEDR0hReserved
29RESERVEDR0hReserved
28RESERVEDR0hReserved
27RESERVEDR0hReserved
26RESERVEDR0hReserved
25RESERVEDR0hReserved
24RESERVEDR0hReserved
23RESERVEDR0hReserved
22RESERVEDR0hReserved
21RESERVEDR0hReserved
20RESERVEDR0hReserved
19RESERVEDR0hReserved
18RESERVEDR0hReserved
17EPWM18_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM18_DEL_TRIP input was triggered
0: EPWM18_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16EPWM17_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM17_DEL_TRIP input was triggered
0: EPWM17_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15EPWM16_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM16_DEL_TRIP input was triggered
0: EPWM16_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14EPWM15_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM15_DEL_TRIP input was triggered
0: EPWM15_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13EPWM14_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM14_DEL_TRIP input was triggered
0: EPWM14_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12EPWM13_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM13_DEL_TRIP input was triggered
0: EPWM13_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11EPWM12_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM12_DEL_TRIP input was triggered
0: EPWM12_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10EPWM11_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM11_DEL_TRIP input was triggered
0: EPWM11_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9EPWM10_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM10_DEL_TRIP input was triggered
0: EPWM10_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8EPWM9_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM9_DEL_TRIP input was triggered
0: EPWM9_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7EPWM8_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM8_DEL_TRIP input was triggered
0: EPWM8_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6EPWM7_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM7_DEL_TRIP input was triggered
0: EPWM7_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5EPWM6_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM6_DEL_TRIP input was triggered
0: EPWM6_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4EPWM5_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM5_DEL_TRIP input was triggered
0: EPWM5_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3EPWM4_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM4_DEL_TRIP input was triggered
0: EPWM4_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2EPWM3_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM3_DEL_TRIP input was triggered
0: EPWM3_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1EPWM2_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM2_DEL_TRIP input was triggered
0: EPWM2_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0EPWM1_DEL_TRIPR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM1_DEL_TRIP input was triggered
0: EPWM1_DEL_TRIP Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.10 XBARFLG10 Register (Offset = 24h) [Reset = 00000000h]

XBARFLG10 is shown in Figure 20-72 and described in Table 20-95.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-72 XBARFLG10 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDEPWM18_DEL_ACTIVEEPWM17_DEL_ACTIVE
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
EPWM16_DEL_ACTIVEEPWM15_DEL_ACTIVEEPWM14_DEL_ACTIVEEPWM13_DEL_ACTIVEEPWM12_DEL_ACTIVEEPWM11_DEL_ACTIVEEPWM10_DEL_ACTIVEEPWM9_DEL_ACTIVE
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
EPWM8_DEL_ACTIVEEPWM7_DEL_ACTIVEEPWM6_DEL_ACTIVEEPWM5_DEL_ACTIVEEPWM4_DEL_ACTIVEEPWM3_DEL_ACTIVEEPWM2_DEL_ACTIVEEPWM1_DEL_ACTIVE
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-95 XBARFLG10 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30RESERVEDR0hReserved
29RESERVEDR0hReserved
28RESERVEDR0hReserved
27RESERVEDR0hReserved
26RESERVEDR0hReserved
25RESERVEDR0hReserved
24RESERVEDR0hReserved
23RESERVEDR0hReserved
22RESERVEDR0hReserved
21RESERVEDR0hReserved
20RESERVEDR0hReserved
19RESERVEDR0hReserved
18RESERVEDR0hReserved
17EPWM18_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM18_DEL_ACTIVE input was triggered
0: EPWM18_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16EPWM17_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM17_DEL_ACTIVE input was triggered
0: EPWM17_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15EPWM16_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM16_DEL_ACTIVE input was triggered
0: EPWM16_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14EPWM15_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM15_DEL_ACTIVE input was triggered
0: EPWM15_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13EPWM14_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM14_DEL_ACTIVE input was triggered
0: EPWM14_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12EPWM13_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM13_DEL_ACTIVE input was triggered
0: EPWM13_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11EPWM12_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM12_DEL_ACTIVE input was triggered
0: EPWM12_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10EPWM11_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM11_DEL_ACTIVE input was triggered
0: EPWM11_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9EPWM10_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM10_DEL_ACTIVE input was triggered
0: EPWM10_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8EPWM9_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM9_DEL_ACTIVE input was triggered
0: EPWM9_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7EPWM8_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM8_DEL_ACTIVE input was triggered
0: EPWM8_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6EPWM7_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM7_DEL_ACTIVE input was triggered
0: EPWM7_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5EPWM6_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM6_DEL_ACTIVE input was triggered
0: EPWM6_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4EPWM5_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM5_DEL_ACTIVE input was triggered
0: EPWM5_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3EPWM4_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM4_DEL_ACTIVE input was triggered
0: EPWM4_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2EPWM3_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM3_DEL_ACTIVE input was triggered
0: EPWM3_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1EPWM2_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM2_DEL_ACTIVE input was triggered
0: EPWM2_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0EPWM1_DEL_ACTIVER0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM1_DEL_ACTIVE input was triggered
0: EPWM1_DEL_ACTIVE Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.11 XBARFLG11 Register (Offset = 28h) [Reset = 00000000h]

XBARFLG11 is shown in Figure 20-73 and described in Table 20-96.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-73 XBARFLG11 Register
3130292827262524
EPWM16_B0_sclkEPWM16_A0_sclkEPWM15_B0_sclkEPWM15_A0_sclkEPWM14_B0_sclkEPWM14_A0_sclkEPWM13_B0_sclkEPWM13_A0_sclk
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
EPWM12_B0_sclkEPWM12_A0_sclkEPWM11_B0_sclkEPWM11_A0_sclkEPWM10_B0_sclkEPWM10_A0_sclkEPWM9_B0_sclkEPWM9_A0_sclk
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
EPWM8_B0_sclkEPWM8_A0_sclkEPWM7_B0_sclkEPWM7_A0_sclkEPWM6_B0_sclkEPWM6_A0_sclkEPWM5_B0_sclkEPWM5_A0_sclk
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
EPWM4_B0_sclkEPWM4_A0_sclkEPWM3_B0_sclkEPWM3_A0_sclkEPWM2_B0_sclkEPWM2_A0_sclkEPWM1_B0_sclkEPWM1_A0_sclk
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-96 XBARFLG11 Register Field Descriptions
BitFieldTypeResetDescription
31EPWM16_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM16_B0_sclk input was triggered
0: EPWM16_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

30EPWM16_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM16_A0_sclk input was triggered
0: EPWM16_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

29EPWM15_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM15_B0_sclk input was triggered
0: EPWM15_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

28EPWM15_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM15_A0_sclk input was triggered
0: EPWM15_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

27EPWM14_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM14_B0_sclk input was triggered
0: EPWM14_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

26EPWM14_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM14_A0_sclk input was triggered
0: EPWM14_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

25EPWM13_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM13_B0_sclk input was triggered
0: EPWM13_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

24EPWM13_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM13_A0_sclk input was triggered
0: EPWM13_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

23EPWM12_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM12_B0_sclk input was triggered
0: EPWM12_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

22EPWM12_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM12_A0_sclk input was triggered
0: EPWM12_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

21EPWM11_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM11_B0_sclk input was triggered
0: EPWM11_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20EPWM11_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM11_A0_sclk input was triggered
0: EPWM11_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

19EPWM10_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM10_B0_sclk input was triggered
0: EPWM10_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

18EPWM10_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM10_A0_sclk input was triggered
0: EPWM10_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

17EPWM9_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM9_B0_sclk input was triggered
0: EPWM9_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16EPWM9_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM9_A0_sclk input was triggered
0: EPWM9_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15EPWM8_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM8_B0_sclk input was triggered
0: EPWM8_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14EPWM8_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM8_A0_sclk input was triggered
0: EPWM8_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13EPWM7_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM7_B0_sclk input was triggered
0: EPWM7_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12EPWM7_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM7_A0_sclk input was triggered
0: EPWM7_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11EPWM6_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM6_B0_sclk input was triggered
0: EPWM6_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10EPWM6_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM6_A0_sclk input was triggered
0: EPWM6_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9EPWM5_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM5_B0_sclk input was triggered
0: EPWM5_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8EPWM5_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM5_A0_sclk input was triggered
0: EPWM5_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7EPWM4_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM4_B0_sclk input was triggered
0: EPWM4_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6EPWM4_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM4_A0_sclk input was triggered
0: EPWM4_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5EPWM3_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM3_B0_sclk input was triggered
0: EPWM3_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4EPWM3_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM3_A0_sclk input was triggered
0: EPWM3_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3EPWM2_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM2_B0_sclk input was triggered
0: EPWM2_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2EPWM2_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM2_A0_sclk input was triggered
0: EPWM2_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1EPWM1_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM1_B0_sclk input was triggered
0: EPWM1_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0EPWM1_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM1_A0_sclk input was triggered
0: EPWM1_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.12 XBARFLG12 Register (Offset = 2Ch) [Reset = 00000000h]

XBARFLG12 is shown in Figure 20-74 and described in Table 20-97.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-74 XBARFLG12 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDEPWM18_B0_sclkEPWM18_A0_sclkEPWM17_B0_sclkEPWM17_A0_sclk
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-97 XBARFLG12 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30RESERVEDR0hReserved
29RESERVEDR0hReserved
28RESERVEDR0hReserved
27RESERVEDR0hReserved
26RESERVEDR0hReserved
25RESERVEDR0hReserved
24RESERVEDR0hReserved
23RESERVEDR0hReserved
22RESERVEDR0hReserved
21RESERVEDR0hReserved
20RESERVEDR0hReserved
19RESERVEDR0hReserved
18RESERVEDR0hReserved
17RESERVEDR0hReserved
16RESERVEDR0hReserved
15RESERVEDR0hReserved
14RESERVEDR0hReserved
13RESERVEDR0hReserved
12RESERVEDR0hReserved
11RESERVEDR0hReserved
10RESERVEDR0hReserved
9RESERVEDR0hReserved
8RESERVEDR0hReserved
7RESERVEDR0hReserved
6RESERVEDR0hReserved
5RESERVEDR0hReserved
4RESERVEDR0hReserved
3EPWM18_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM18_B0_sclk input was triggered
0: EPWM18_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2EPWM18_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM18_A0_sclk input was triggered
0: EPWM18_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1EPWM17_B0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM17_B0_sclk input was triggered
0: EPWM17_B0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0EPWM17_A0_sclkR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPWM17_A0_sclk input was triggered
0: EPWM17_A0_sclk Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.13 XBARFLG13 Register (Offset = 30h) [Reset = 00000000h]

XBARFLG13 is shown in Figure 20-75 and described in Table 20-98.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-75 XBARFLG13 Register
3130292827262524
MDL16_OUTBMDL16_OUTAMDL15_OUTBMDL15_OUTAMDL14_OUTBMDL14_OUTAMDL13_OUTBMDL13_OUTA
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
MDL12_OUTBMDL12_OUTAMDL11_OUTBMDL11_OUTAMDL10_OUTBMDL10_OUTAMDL9_OUTBMDL9_OUTA
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
MDL8_OUTBMDL8_OUTAMDL7_OUTBMDL7_OUTAMDL6_OUTBMDL6_OUTAMDL5_OUTBMDL5_OUTA
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
MDL4_OUTBMDL4_OUTAMDL3_OUTBMDL3_OUTAMDL2_OUTBMDL2_OUTAMDL1_OUTBMDL1_OUTA
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-98 XBARFLG13 Register Field Descriptions
BitFieldTypeResetDescription
31MDL16_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL16_OUTB input was triggered
0: MDL16_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

30MDL16_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL16_OUTA input was triggered
0: MDL16_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

29MDL15_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL15_OUTB input was triggered
0: MDL15_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

28MDL15_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL15_OUTA input was triggered
0: MDL15_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

27MDL14_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL14_OUTB input was triggered
0: MDL14_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

26MDL14_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL14_OUTA input was triggered
0: MDL14_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

25MDL13_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL13_OUTB input was triggered
0: MDL13_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

24MDL13_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL13_OUTA input was triggered
0: MDL13_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

23MDL12_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL12_OUTB input was triggered
0: MDL12_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

22MDL12_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL12_OUTA input was triggered
0: MDL12_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

21MDL11_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL11_OUTB input was triggered
0: MDL11_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20MDL11_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL11_OUTA input was triggered
0: MDL11_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

19MDL10_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL10_OUTB input was triggered
0: MDL10_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

18MDL10_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL10_OUTA input was triggered
0: MDL10_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

17MDL9_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL9_OUTB input was triggered
0: MDL9_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16MDL9_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL9_OUTA input was triggered
0: MDL9_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15MDL8_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL8_OUTB input was triggered
0: MDL8_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14MDL8_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL8_OUTA input was triggered
0: MDL8_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13MDL7_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL7_OUTB input was triggered
0: MDL7_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12MDL7_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL7_OUTA input was triggered
0: MDL7_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11MDL6_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL6_OUTB input was triggered
0: MDL6_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10MDL6_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL6_OUTA input was triggered
0: MDL6_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9MDL5_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL5_OUTB input was triggered
0: MDL5_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8MDL5_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL5_OUTA input was triggered
0: MDL5_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7MDL4_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL4_OUTB input was triggered
0: MDL4_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6MDL4_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL4_OUTA input was triggered
0: MDL4_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5MDL3_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL3_OUTB input was triggered
0: MDL3_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4MDL3_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL3_OUTA input was triggered
0: MDL3_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3MDL2_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL2_OUTB input was triggered
0: MDL2_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2MDL2_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL2_OUTA input was triggered
0: MDL2_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1MDL1_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL1_OUTB input was triggered
0: MDL1_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0MDL1_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL1_OUTA input was triggered
0: MDL1_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.14 XBARFLG14 Register (Offset = 34h) [Reset = 00000000h]

XBARFLG14 is shown in Figure 20-76 and described in Table 20-99.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-76 XBARFLG14 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDMDL18_OUTBMDL18_OUTAMDL17_OUTBMDL17_OUTA
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-99 XBARFLG14 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30RESERVEDR0hReserved
29RESERVEDR0hReserved
28RESERVEDR0hReserved
27RESERVEDR0hReserved
26RESERVEDR0hReserved
25RESERVEDR0hReserved
24RESERVEDR0hReserved
23RESERVEDR0hReserved
22RESERVEDR0hReserved
21RESERVEDR0hReserved
20RESERVEDR0hReserved
19RESERVEDR0hReserved
18RESERVEDR0hReserved
17RESERVEDR0hReserved
16RESERVEDR0hReserved
15RESERVEDR0hReserved
14RESERVEDR0hReserved
13RESERVEDR0hReserved
12RESERVEDR0hReserved
11RESERVEDR0hReserved
10RESERVEDR0hReserved
9RESERVEDR0hReserved
8RESERVEDR0hReserved
7RESERVEDR0hReserved
6RESERVEDR0hReserved
5RESERVEDR0hReserved
4RESERVEDR0hReserved
3MDL18_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL18_OUTB input was triggered
0: MDL18_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2MDL18_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL18_OUTA input was triggered
0: MDL18_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1MDL17_OUTBR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL17_OUTB input was triggered
0: MDL17_OUTB Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0MDL17_OUTAR0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MDL17_OUTA input was triggered
0: MDL17_OUTA Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.15 XBARFLG15 Register (Offset = 38h) [Reset = 00000000h]

XBARFLG15 is shown in Figure 20-77 and described in Table 20-100.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-77 XBARFLG15 Register
3130292827262524
CLB6_OUT1CLB6_OUT0CLB5_OUT7CLB5_OUT6CLB5_OUT3CLB5_OUT2CLB5_OUT1CLB5_OUT0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
CLB4_OUT7CLB4_OUT6CLB4_OUT3CLB4_OUT2CLB4_OUT1CLB4_OUT0CLB3_OUT7CLB3_OUT6
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
CLB3_OUT3CLB3_OUT2CLB3_OUT1CLB3_OUT0CLB2_OUT7CLB2_OUT6CLB2_OUT3CLB2_OUT2
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
CLB2_OUT1CLB2_OUT0CLB1_OUT7CLB1_OUT6CLB1_OUT3CLB1_OUT2CLB1_OUT1CLB1_OUT0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-100 XBARFLG15 Register Field Descriptions
BitFieldTypeResetDescription
31CLB6_OUT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB6_OUT1 input was triggered
0: CLB6_OUT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

30CLB6_OUT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB6_OUT0 input was triggered
0: CLB6_OUT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

29CLB5_OUT7R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB5_OUT7 input was triggered
0: CLB5_OUT7 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

28CLB5_OUT6R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB5_OUT6 input was triggered
0: CLB5_OUT6 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

27CLB5_OUT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB5_OUT3 input was triggered
0: CLB5_OUT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

26CLB5_OUT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB5_OUT2 input was triggered
0: CLB5_OUT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

25CLB5_OUT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB5_OUT1 input was triggered
0: CLB5_OUT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

24CLB5_OUT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB5_OUT0 input was triggered
0: CLB5_OUT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

23CLB4_OUT7R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB4_OUT7 input was triggered
0: CLB4_OUT7 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

22CLB4_OUT6R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB4_OUT6 input was triggered
0: CLB4_OUT6 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

21CLB4_OUT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB4_OUT3 input was triggered
0: CLB4_OUT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20CLB4_OUT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB4_OUT2 input was triggered
0: CLB4_OUT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

19CLB4_OUT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB4_OUT1 input was triggered
0: CLB4_OUT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

18CLB4_OUT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB4_OUT0 input was triggered
0: CLB4_OUT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

17CLB3_OUT7R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB3_OUT7 input was triggered
0: CLB3_OUT7 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16CLB3_OUT6R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB3_OUT6 input was triggered
0: CLB3_OUT6 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15CLB3_OUT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB3_OUT3 input was triggered
0: CLB3_OUT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14CLB3_OUT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB3_OUT2 input was triggered
0: CLB3_OUT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13CLB3_OUT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB3_OUT1 input was triggered
0: CLB3_OUT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12CLB3_OUT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB3_OUT0 input was triggered
0: CLB3_OUT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11CLB2_OUT7R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB2_OUT7 input was triggered
0: CLB2_OUT7 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10CLB2_OUT6R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB2_OUT6 input was triggered
0: CLB2_OUT6 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9CLB2_OUT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB2_OUT3 input was triggered
0: CLB2_OUT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8CLB2_OUT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB2_OUT2 input was triggered
0: CLB2_OUT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7CLB2_OUT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB2_OUT1 input was triggered
0: CLB2_OUT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6CLB2_OUT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB2_OUT0 input was triggered
0: CLB2_OUT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5CLB1_OUT7R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB1_OUT7 input was triggered
0: CLB1_OUT7 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4CLB1_OUT6R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB1_OUT6 input was triggered
0: CLB1_OUT6 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3CLB1_OUT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB1_OUT3 input was triggered
0: CLB1_OUT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2CLB1_OUT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB1_OUT2 input was triggered
0: CLB1_OUT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1CLB1_OUT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB1_OUT1 input was triggered
0: CLB1_OUT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0CLB1_OUT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB1_OUT0 input was triggered
0: CLB1_OUT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.16 XBARFLG16 Register (Offset = 3Ch) [Reset = 00000000h]

XBARFLG16 is shown in Figure 20-78 and described in Table 20-101.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-78 XBARFLG16 Register
3130292827262524
EPG1_EPGOUT3EPG1_EPGOUT2EPG1_EPGOUT1EPG1_EPGOUT0RESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
ADCE_EXTMUXSEL3ADCE_EXTMUXSEL2ADCE_EXTMUXSEL1ADCE_EXTMUXSEL0ADCD_EXTMUXSEL3ADCD_EXTMUXSEL2ADCD_EXTMUXSEL1ADCD_EXTMUXSEL0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
ADCC_EXTMUXSEL3ADCC_EXTMUXSEL2ADCC_EXTMUXSEL1ADCC_EXTMUXSEL0ADCB_EXTMUXSEL3ADCB_EXTMUXSEL2ADCB_EXTMUXSEL1ADCB_EXTMUXSEL0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
ADCA_EXTMUXSEL3ADCA_EXTMUXSEL2ADCA_EXTMUXSEL1ADCA_EXTMUXSEL0CLB6_OUT7CLB6_OUT6CLB6_OUT3CLB6_OUT2
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-101 XBARFLG16 Register Field Descriptions
BitFieldTypeResetDescription
31EPG1_EPGOUT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPG1_EPGOUT3 input was triggered
0: EPG1_EPGOUT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

30EPG1_EPGOUT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPG1_EPGOUT2 input was triggered
0: EPG1_EPGOUT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

29EPG1_EPGOUT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPG1_EPGOUT1 input was triggered
0: EPG1_EPGOUT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

28EPG1_EPGOUT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: EPG1_EPGOUT0 input was triggered
0: EPG1_EPGOUT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

27RESERVEDR0hReserved
26RESERVEDR0hReserved
25RESERVEDR0hReserved
24RESERVEDR0hReserved
23ADCE_EXTMUXSEL3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCE_EXTMUXSEL3 input was triggered
0: ADCE_EXTMUXSEL3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

22ADCE_EXTMUXSEL2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCE_EXTMUXSEL2 input was triggered
0: ADCE_EXTMUXSEL2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

21ADCE_EXTMUXSEL1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCE_EXTMUXSEL1 input was triggered
0: ADCE_EXTMUXSEL1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20ADCE_EXTMUXSEL0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCE_EXTMUXSEL0 input was triggered
0: ADCE_EXTMUXSEL0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

19ADCD_EXTMUXSEL3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCD_EXTMUXSEL3 input was triggered
0: ADCD_EXTMUXSEL3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

18ADCD_EXTMUXSEL2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCD_EXTMUXSEL2 input was triggered
0: ADCD_EXTMUXSEL2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

17ADCD_EXTMUXSEL1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCD_EXTMUXSEL1 input was triggered
0: ADCD_EXTMUXSEL1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16ADCD_EXTMUXSEL0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCD_EXTMUXSEL0 input was triggered
0: ADCD_EXTMUXSEL0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15ADCC_EXTMUXSEL3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCC_EXTMUXSEL3 input was triggered
0: ADCC_EXTMUXSEL3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14ADCC_EXTMUXSEL2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCC_EXTMUXSEL2 input was triggered
0: ADCC_EXTMUXSEL2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13ADCC_EXTMUXSEL1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCC_EXTMUXSEL1 input was triggered
0: ADCC_EXTMUXSEL1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12ADCC_EXTMUXSEL0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCC_EXTMUXSEL0 input was triggered
0: ADCC_EXTMUXSEL0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11ADCB_EXTMUXSEL3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCB_EXTMUXSEL3 input was triggered
0: ADCB_EXTMUXSEL3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10ADCB_EXTMUXSEL2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCB_EXTMUXSEL2 input was triggered
0: ADCB_EXTMUXSEL2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9ADCB_EXTMUXSEL1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCB_EXTMUXSEL1 input was triggered
0: ADCB_EXTMUXSEL1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8ADCB_EXTMUXSEL0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCB_EXTMUXSEL0 input was triggered
0: ADCB_EXTMUXSEL0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7ADCA_EXTMUXSEL3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCA_EXTMUXSEL3 input was triggered
0: ADCA_EXTMUXSEL3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6ADCA_EXTMUXSEL2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCA_EXTMUXSEL2 input was triggered
0: ADCA_EXTMUXSEL2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5ADCA_EXTMUXSEL1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCA_EXTMUXSEL1 input was triggered
0: ADCA_EXTMUXSEL1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4ADCA_EXTMUXSEL0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: ADCA_EXTMUXSEL0 input was triggered
0: ADCA_EXTMUXSEL0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3CLB6_OUT7R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB6_OUT7 input was triggered
0: CLB6_OUT7 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2CLB6_OUT6R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB6_OUT6 input was triggered
0: CLB6_OUT6 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1CLB6_OUT3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB6_OUT3 input was triggered
0: CLB6_OUT3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0CLB6_OUT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CLB6_OUT2 input was triggered
0: CLB6_OUT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.17 XBARFLG17 Register (Offset = 40h) [Reset = 00000000h]

XBARFLG17 is shown in Figure 20-79 and described in Table 20-102.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-79 XBARFLG17 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMCANF_FEVT2MCANF_FEVT1
R-0hR-0hR-0h
15141312111098
MCANF_FEVT0MCANE_FEVT2MCANE_FEVT1MCANE_FEVT0MCAND_FEVT2MCAND_FEVT1MCAND_FEVT0MCANC_FEVT2
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
MCANC_FEVT1MCANC_FEVT0MCANB_FEVT2MCANB_FEVT1MCANB_FEVT0MCANA_FEVT2MCANA_FEVT1MCANA_FEVT0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-102 XBARFLG17 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17MCANF_FEVT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANF_FEVT2 input was triggered
0: MCANF_FEVT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16MCANF_FEVT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANF_FEVT1 input was triggered
0: MCANF_FEVT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15MCANF_FEVT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANF_FEVT0 input was triggered
0: MCANF_FEVT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14MCANE_FEVT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANE_FEVT2 input was triggered
0: MCANE_FEVT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13MCANE_FEVT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANE_FEVT1 input was triggered
0: MCANE_FEVT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12MCANE_FEVT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANE_FEVT0 input was triggered
0: MCANE_FEVT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11MCAND_FEVT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCAND_FEVT2 input was triggered
0: MCAND_FEVT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10MCAND_FEVT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCAND_FEVT1 input was triggered
0: MCAND_FEVT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9MCAND_FEVT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCAND_FEVT0 input was triggered
0: MCAND_FEVT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8MCANC_FEVT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANC_FEVT2 input was triggered
0: MCANC_FEVT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7MCANC_FEVT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANC_FEVT1 input was triggered
0: MCANC_FEVT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6MCANC_FEVT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANC_FEVT0 input was triggered
0: MCANC_FEVT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5MCANB_FEVT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANB_FEVT2 input was triggered
0: MCANB_FEVT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4MCANB_FEVT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANB_FEVT1 input was triggered
0: MCANB_FEVT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3MCANB_FEVT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANB_FEVT0 input was triggered
0: MCANB_FEVT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2MCANA_FEVT2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANA_FEVT2 input was triggered
0: MCANA_FEVT2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1MCANA_FEVT1R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANA_FEVT1 input was triggered
0: MCANA_FEVT1 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0MCANA_FEVT0R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: MCANA_FEVT0 input was triggered
0: MCANA_FEVT0 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.18 XBARFLG18 Register (Offset = 44h) [Reset = 00000000h]

XBARFLG18 is shown in Figure 20-80 and described in Table 20-103.

Return to the Summary Table.

This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: Corresponding Input was triggered
0: Corresponding Input was not triggered

Figure 20-80 XBARFLG18 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCPU3ERADEVT11CPU3ERADEVT10CPU3ERADEVT9CPU3ERADEVT8
R-0hR-0hR-0hR-0hR-0h
15141312111098
CPU2ERADEVT11CPU2ERADEVT10CPU2ERADEVT9CPU2ERADEVT8CPU1ERADEVT11CPU1ERADEVT10CPU1ERADEVT9CPU1ERADEVT8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
FSIRXD_TRIG_3FSIRXD_TRIG_2FSIRXC_TRIG_3FSIRXC_TRIG_2FSIRXB_TRIG_3FSIRXB_TRIG_2FSIRXA_TRIG_3FSIRXA_TRIG_2
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-103 XBARFLG18 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19CPU3ERADEVT11R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU3ERADEVT11 input was triggered
0: CPU3ERADEVT11 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

18CPU3ERADEVT10R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU3ERADEVT10 input was triggered
0: CPU3ERADEVT10 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

17CPU3ERADEVT9R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU3ERADEVT9 input was triggered
0: CPU3ERADEVT9 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16CPU3ERADEVT8R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU3ERADEVT8 input was triggered
0: CPU3ERADEVT8 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15CPU2ERADEVT11R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU2ERADEVT11 input was triggered
0: CPU2ERADEVT11 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14CPU2ERADEVT10R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU2ERADEVT10 input was triggered
0: CPU2ERADEVT10 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13CPU2ERADEVT9R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU2ERADEVT9 input was triggered
0: CPU2ERADEVT9 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12CPU2ERADEVT8R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU2ERADEVT8 input was triggered
0: CPU2ERADEVT8 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11CPU1ERADEVT11R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU1ERADEVT11 input was triggered
0: CPU1ERADEVT11 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10CPU1ERADEVT10R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU1ERADEVT10 input was triggered
0: CPU1ERADEVT10 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9CPU1ERADEVT9R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU1ERADEVT9 input was triggered
0: CPU1ERADEVT9 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8CPU1ERADEVT8R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU1ERADEVT8 input was triggered
0: CPU1ERADEVT8 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7FSIRXD_TRIG_3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXD_TRIG_3 input was triggered
0: FSIRXD_TRIG_3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6FSIRXD_TRIG_2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXD_TRIG_2 input was triggered
0: FSIRXD_TRIG_2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5FSIRXC_TRIG_3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXC_TRIG_3 input was triggered
0: FSIRXC_TRIG_3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4FSIRXC_TRIG_2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXC_TRIG_2 input was triggered
0: FSIRXC_TRIG_2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3FSIRXB_TRIG_3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXB_TRIG_3 input was triggered
0: FSIRXB_TRIG_3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2FSIRXB_TRIG_2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXB_TRIG_2 input was triggered
0: FSIRXB_TRIG_2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1FSIRXA_TRIG_3R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXA_TRIG_3 input was triggered
0: FSIRXA_TRIG_3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0FSIRXA_TRIG_2R0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXA_TRIG_2 input was triggered
0: FSIRXA_TRIG_2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

20.5.9.19 XBARCLR1 Register (Offset = 100h) [Reset = 00000000h]

XBARCLR1 is shown in Figure 20-81 and described in Table 20-104.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-81 XBARCLR1 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR-0-0hR-0-0hR-0-0hR-0-0hR-0-0hR-0-0hR-0-0h
2322212019181716
CMPSS12_CTRIPLCMPSS12_CTRIPHCMPSS11_CTRIPLCMPSS11_CTRIPHCMPSS10_CTRIPLCMPSS10_CTRIPHCMPSS9_CTRIPLCMPSS9_CTRIPH
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
CMPSS8_CTRIPHCMPSS8_CTRIPLCMPSS7_CTRIPHCMPSS7_CTRIPLCMPSS6_CTRIPHCMPSS6_CTRIPLCMPSS5_CTRIPHCMPSS5_CTRIPL
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
CMPSS4_CTRIPHCMPSS4_CTRIPLCMPSS3_CTRIPHCMPSS3_CTRIPLCMPSS2_CTRIPHCMPSS2_CTRIPLCMPSS1_CTRIPHCMPSS1_CTRIPL
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-104 XBARCLR1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR-00hReserved
30RESERVEDR-00hReserved
29RESERVEDR-00hReserved
28RESERVEDR-00hReserved
27RESERVEDR-00hReserved
26RESERVEDR-00hReserved
25RESERVEDR-00hReserved
24RESERVEDR-00hReserved
23CMPSS12_CTRIPLR-0/W1S0hWriting 1 to this bit clears the CMPSS12_CTRIPL bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

22CMPSS12_CTRIPHR-0/W1S0hWriting 1 to this bit clears the CMPSS12_CTRIPH bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

21CMPSS11_CTRIPLR-0/W1S0hWriting 1 to this bit clears the CMPSS11_CTRIPL bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20CMPSS11_CTRIPHR-0/W1S0hWriting 1 to this bit clears the CMPSS11_CTRIPH bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

19CMPSS10_CTRIPLR-0/W1S0hWriting 1 to this bit clears the CMPSS10_CTRIPL bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

18CMPSS10_CTRIPHR-0/W1S0hWriting 1 to this bit clears the CMPSS10_CTRIPH bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

17CMPSS9_CTRIPLR-0/W1S0hWriting 1 to this bit clears the CMPSS9_CTRIPL bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16CMPSS9_CTRIPHR-0/W1S0hWriting 1 to this bit clears the CMPSS9_CTRIPH bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15CMPSS8_CTRIPHR-0/W1S0hWriting 1 to this bit clears the CMPSS8_CTRIPH bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

14CMPSS8_CTRIPLR-0/W1S0hWriting 1 to this bit clears the CMPSS8_CTRIPL bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

13CMPSS7_CTRIPHR-0/W1S0hWriting 1 to this bit clears the CMPSS7_CTRIPH bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

12CMPSS7_CTRIPLR-0/W1S0hWriting 1 to this bit clears the CMPSS7_CTRIPL bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

11CMPSS6_CTRIPHR-0/W1S0hWriting 1 to this bit clears the CMPSS6_CTRIPH bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10CMPSS6_CTRIPLR-0/W1S0hWriting 1 to this bit clears the CMPSS6_CTRIPL bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9CMPSS5_CTRIPHR-0/W1S0hWriting 1 to this bit clears the CMPSS5_CTRIPH bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8CMPSS5_CTRIPLR-0/W1S0hWriting 1 to this bit clears the CMPSS5_CTRIPL bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7CMPSS4_CTRIPHR-0/W1S0hWriting 1 to this bit clears the CMPSS4_CTRIPH bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

6CMPSS4_CTRIPLR-0/W1S0hWriting 1 to this bit clears the CMPSS4_CTRIPL bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

5CMPSS3_CTRIPHR-0/W1S0hWriting 1 to this bit clears the CMPSS3_CTRIPH bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4CMPSS3_CTRIPLR-0/W1S0hWriting 1 to this bit clears the CMPSS3_CTRIPL bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3CMPSS2_CTRIPHR-0/W1S0hWriting 1 to this bit clears the CMPSS2_CTRIPH bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2CMPSS2_CTRIPLR-0/W1S0hWriting 1 to this bit clears the CMPSS2_CTRIPL bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1CMPSS1_CTRIPHR-0/W1S0hWriting 1 to this bit clears the CMPSS1_CTRIPH bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0CMPSS1_CTRIPLR-0/W1S0hWriting 1 to this bit clears the CMPSS1_CTRIPL bit in the XBARFLG1 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.20 XBARCLR2 Register (Offset = 104h) [Reset = 00000000h]

XBARCLR2 is shown in Figure 20-82 and described in Table 20-105.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-82 XBARCLR2 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR-0-0hR-0-0hR-0-0hR-0-0hR-0-0hR-0-0hR-0-0h
2322212019181716
CMPSS12_CTRIPOUTLCMPSS12_CTRIPOUTHCMPSS11_CTRIPOUTLCMPSS11_CTRIPOUTHCMPSS10_CTRIPOUTLCMPSS10_CTRIPOUTHCMPSS9_CTRIPOUTLCMPSS9_CTRIPOUTH
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
CMPSS8_CTRIPOUTHCMPSS8_CTRIPOUTLCMPSS7_CTRIPOUTHCMPSS7_CTRIPOUTLCMPSS6_CTRIPOUTHCMPSS6_CTRIPOUTLCMPSS5_CTRIPOUTHCMPSS5_CTRIPOUTL
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
CMPSS4_CTRIPOUTHCMPSS4_CTRIPOUTLCMPSS3_CTRIPOUTHCMPSS3_CTRIPOUTLCMPSS2_CTRIPOUTHCMPSS2_CTRIPOUTLCMPSS1_CTRIPOUTHCMPSS1_CTRIPOUTL
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-105 XBARCLR2 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR-00hReserved
30RESERVEDR-00hReserved
29RESERVEDR-00hReserved
28RESERVEDR-00hReserved
27RESERVEDR-00hReserved
26RESERVEDR-00hReserved
25RESERVEDR-00hReserved
24RESERVEDR-00hReserved
23CMPSS12_CTRIPOUTLR-0/W1S0hWriting 1 to this bit clears the CMPSS12_CTRIPOUTL bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

22CMPSS12_CTRIPOUTHR-0/W1S0hWriting 1 to this bit clears the CMPSS12_CTRIPOUTH bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

21CMPSS11_CTRIPOUTLR-0/W1S0hWriting 1 to this bit clears the CMPSS11_CTRIPOUTL bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20CMPSS11_CTRIPOUTHR-0/W1S0hWriting 1 to this bit clears the CMPSS11_CTRIPOUTH bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

19CMPSS10_CTRIPOUTLR-0/W1S0hWriting 1 to this bit clears the CMPSS10_CTRIPOUTL bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

18CMPSS10_CTRIPOUTHR-0/W1S0hWriting 1 to this bit clears the CMPSS10_CTRIPOUTH bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

17CMPSS9_CTRIPOUTLR-0/W1S0hWriting 1 to this bit clears the CMPSS9_CTRIPOUTL bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16CMPSS9_CTRIPOUTHR-0/W1S0hWriting 1 to this bit clears the CMPSS9_CTRIPOUTH bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15CMPSS8_CTRIPOUTHR-0/W1S0hWriting 1 to this bit clears the CMPSS8_CTRIPOUTH bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

14CMPSS8_CTRIPOUTLR-0/W1S0hWriting 1 to this bit clears the CMPSS8_CTRIPOUTL bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

13CMPSS7_CTRIPOUTHR-0/W1S0hWriting 1 to this bit clears the CMPSS7_CTRIPOUTH bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

12CMPSS7_CTRIPOUTLR-0/W1S0hWriting 1 to this bit clears the CMPSS7_CTRIPOUTL bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

11CMPSS6_CTRIPOUTHR-0/W1S0hWriting 1 to this bit clears the CMPSS6_CTRIPOUTH bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10CMPSS6_CTRIPOUTLR-0/W1S0hWriting 1 to this bit clears the CMPSS6_CTRIPOUTL bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9CMPSS5_CTRIPOUTHR-0/W1S0hWriting 1 to this bit clears the CMPSS5_CTRIPOUTH bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8CMPSS5_CTRIPOUTLR-0/W1S0hWriting 1 to this bit clears the CMPSS5_CTRIPOUTL bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7CMPSS4_CTRIPOUTHR-0/W1S0hWriting 1 to this bit clears the CMPSS4_CTRIPOUTH bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

6CMPSS4_CTRIPOUTLR-0/W1S0hWriting 1 to this bit clears the CMPSS4_CTRIPOUTL bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

5CMPSS3_CTRIPOUTHR-0/W1S0hWriting 1 to this bit clears the CMPSS3_CTRIPOUTH bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4CMPSS3_CTRIPOUTLR-0/W1S0hWriting 1 to this bit clears the CMPSS3_CTRIPOUTL bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3CMPSS2_CTRIPOUTHR-0/W1S0hWriting 1 to this bit clears the CMPSS2_CTRIPOUTH bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2CMPSS2_CTRIPOUTLR-0/W1S0hWriting 1 to this bit clears the CMPSS2_CTRIPOUTL bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1CMPSS1_CTRIPOUTHR-0/W1S0hWriting 1 to this bit clears the CMPSS1_CTRIPOUTH bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0CMPSS1_CTRIPOUTLR-0/W1S0hWriting 1 to this bit clears the CMPSS1_CTRIPOUTL bit in XBARFLG2 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.21 XBARCLR3 Register (Offset = 108h) [Reset = 00000000h]

XBARCLR3 is shown in Figure 20-83 and described in Table 20-106.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-83 XBARCLR3 Register
3130292827262524
SD4FLT4_COMPLSD4FLT4_COMPHSD4FLT3_COMPLSD4FLT3_COMPHSD4FLT2_COMPLSD4FLT2_COMPHSD4FLT1_COMPLSD4FLT1_COMPH
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
SD3FLT4_COMPLSD3FLT4_COMPHSD3FLT3_COMPLSD3FLT3_COMPHSD3FLT2_COMPLSD3FLT2_COMPHSD3FLT1_COMPLSD3FLT1_COMPH
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
SD2FLT4_COMPHSD2FLT4_COMPLSD2FLT3_COMPHSD2FLT3_COMPLSD2FLT2_COMPHSD2FLT2_COMPLSD2FLT1_COMPHSD2FLT1_COMPL
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
SD1FLT4_COMPHSD1FLT4_COMPLSD1FLT3_COMPHSD1FLT3_COMPLSD1FLT2_COMPHSD1FLT2_COMPLSD1FLT1_COMPHSD1FLT1_COMPL
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-106 XBARCLR3 Register Field Descriptions
BitFieldTypeResetDescription
31SD4FLT4_COMPLR-0/W1S0hWriting 1 to this bit clears the SD4FLT4_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

30SD4FLT4_COMPHR-0/W1S0hWriting 1 to this bit clears the SD4FLT4_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

29SD4FLT3_COMPLR-0/W1S0hWriting 1 to this bit clears the SD4FLT3_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

28SD4FLT3_COMPHR-0/W1S0hWriting 1 to this bit clears the SD4FLT3_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

27SD4FLT2_COMPLR-0/W1S0hWriting 1 to this bit clears the SD4FLT2_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

26SD4FLT2_COMPHR-0/W1S0hWriting 1 to this bit clears the SD4FLT2_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

25SD4FLT1_COMPLR-0/W1S0hWriting 1 to this bit clears the SD4FLT1_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

24SD4FLT1_COMPHR-0/W1S0hWriting 1 to this bit clears the SD4FLT1_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

23SD3FLT4_COMPLR-0/W1S0hWriting 1 to this bit clears the SD3FLT4_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

22SD3FLT4_COMPHR-0/W1S0hWriting 1 to this bit clears the SD3FLT4_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

21SD3FLT3_COMPLR-0/W1S0hWriting 1 to this bit clears the SD3FLT3_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20SD3FLT3_COMPHR-0/W1S0hWriting 1 to this bit clears the SD3FLT3_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

19SD3FLT2_COMPLR-0/W1S0hWriting 1 to this bit clears the SD3FLT2_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

18SD3FLT2_COMPHR-0/W1S0hWriting 1 to this bit clears the SD3FLT2_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

17SD3FLT1_COMPLR-0/W1S0hWriting 1 to this bit clears the SD3FLT1_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16SD3FLT1_COMPHR-0/W1S0hWriting 1 to this bit clears the SD3FLT1_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15SD2FLT4_COMPHR-0/W1S0hWriting 1 to this bit clears the SD2FLT4_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

14SD2FLT4_COMPLR-0/W1S0hWriting 1 to this bit clears the SD2FLT4_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

13SD2FLT3_COMPHR-0/W1S0hWriting 1 to this bit clears the SD2FLT3_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

12SD2FLT3_COMPLR-0/W1S0hWriting 1 to this bit clears the SD2FLT3_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

11SD2FLT2_COMPHR-0/W1S0hWriting 1 to this bit clears the SD2FLT2_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10SD2FLT2_COMPLR-0/W1S0hWriting 1 to this bit clears the SD2FLT2_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9SD2FLT1_COMPHR-0/W1S0hWriting 1 to this bit clears the SD2FLT1_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8SD2FLT1_COMPLR-0/W1S0hWriting 1 to this bit clears the SD2FLT1_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7SD1FLT4_COMPHR-0/W1S0hWriting 1 to this bit clears the SD1FLT4_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

6SD1FLT4_COMPLR-0/W1S0hWriting 1 to this bit clears the SD1FLT4_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

5SD1FLT3_COMPHR-0/W1S0hWriting 1 to this bit clears the SD1FLT3_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4SD1FLT3_COMPLR-0/W1S0hWriting 1 to this bit clears the SD1FLT3_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3SD1FLT2_COMPHR-0/W1S0hWriting 1 to this bit clears the SD1FLT2_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2SD1FLT2_COMPLR-0/W1S0hWriting 1 to this bit clears the SD1FLT2_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1SD1FLT1_COMPHR-0/W1S0hWriting 1 to this bit clears the SD1FLT1_COMPH bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0SD1FLT1_COMPLR-0/W1S0hWriting 1 to this bit clears the SD1FLT1_COMPL bit in the XBARFLG3 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.22 XBARCLR4 Register (Offset = 10Ch) [Reset = 00000000h]

XBARCLR4 is shown in Figure 20-84 and described in Table 20-107.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-84 XBARCLR4 Register
3130292827262524
INPUT32INPUT31INPUT30INPUT29INPUT28INPUT27INPUT26INPUT25
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
INPUT24INPUT23INPUT22INPUT21INPUT20INPUT19INPUT18INPUT17
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
INPUT16INPUT15INPUT14INPUT13INPUT12INPUT11INPUT10INPUT9
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
INPUT8INPUT7INPUT6INPUT5INPUT4INPUT3INPUT2INPUT1
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-107 XBARCLR4 Register Field Descriptions
BitFieldTypeResetDescription
31INPUT32R-0/W1S0hWriting 1 to this bit clears the INPUT32 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

30INPUT31R-0/W1S0hWriting 1 to this bit clears the INPUT31 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

29INPUT30R-0/W1S0hWriting 1 to this bit clears the INPUT30 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

28INPUT29R-0/W1S0hWriting 1 to this bit clears the INPUT29 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

27INPUT28R-0/W1S0hWriting 1 to this bit clears the INPUT28 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

26INPUT27R-0/W1S0hWriting 1 to this bit clears the INPUT27 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

25INPUT26R-0/W1S0hWriting 1 to this bit clears the INPUT26 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

24INPUT25R-0/W1S0hWriting 1 to this bit clears the INPUT25 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

23INPUT24R-0/W1S0hWriting 1 to this bit clears the INPUT24 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

22INPUT23R-0/W1S0hWriting 1 to this bit clears the INPUT23 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

21INPUT22R-0/W1S0hWriting 1 to this bit clears the INPUT22 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20INPUT21R-0/W1S0hWriting 1 to this bit clears the INPUT21 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

19INPUT20R-0/W1S0hWriting 1 to this bit clears the INPUT20 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

18INPUT19R-0/W1S0hWriting 1 to this bit clears the INPUT19 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

17INPUT18R-0/W1S0hWriting 1 to this bit clears the INPUT18 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16INPUT17R-0/W1S0hWriting 1 to this bit clears the INPUT17 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15INPUT16R-0/W1S0hWriting 1 to this bit clears the INPUT16 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

14INPUT15R-0/W1S0hWriting 1 to this bit clears the INPUT15 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

13INPUT14R-0/W1S0hWriting 1 to this bit clears the INPUT14 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

12INPUT13R-0/W1S0hWriting 1 to this bit clears the INPUT13 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

11INPUT12R-0/W1S0hWriting 1 to this bit clears the INPUT12 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10INPUT11R-0/W1S0hWriting 1 to this bit clears the INPUT11 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9INPUT10R-0/W1S0hWriting 1 to this bit clears the INPUT10 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8INPUT9R-0/W1S0hWriting 1 to this bit clears the INPUT9 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7INPUT8R-0/W1S0hWriting 1 to this bit clears the INPUT8 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

6INPUT7R-0/W1S0hWriting 1 to this bit clears the INPUT7 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

5INPUT6R-0/W1S0hWriting 1 to this bit clears the INPUT6 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4INPUT5R-0/W1S0hWriting 1 to this bit clears the INPUT5 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3INPUT4R-0/W1S0hWriting 1 to this bit clears the INPUT4 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2INPUT3R-0/W1S0hWriting 1 to this bit clears the INPUT3 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1INPUT2R-0/W1S0hWriting 1 to this bit clears the INPUT2 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0INPUT1R-0/W1S0hWriting 1 to this bit clears the INPUT1 bit in the XBARFLG4 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.23 XBARCLR5 Register (Offset = 110h) [Reset = 00000000h]

XBARCLR5 is shown in Figure 20-85 and described in Table 20-108.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-85 XBARCLR5 Register
3130292827262524
CPU3_ADCCHECKEVT4CPU3_ADCCHECKEVT3CPU3_ADCCHECKEVT2CPU3_ADCCHECKEVT1CPU2_ADCCHECKEVT4CPU2_ADCCHECKEVT3CPU2_ADCCHECKEVT2CPU2_ADCCHECKEVT1
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
CPU1_ADCCHECKEVT4CPU1_ADCCHECKEVT3CPU1_ADCCHECKEVT2CPU1_ADCCHECKEVT1ADCEEVT4ADCEEVT3ADCEEVT2ADCEEVT1
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
ADCDEVT4ADCDEVT3ADCDEVT2ADCDEVT1ADCCEVT4ADCCEVT3ADCCEVT2ADCCEVT1
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
ADCBEVT4ADCBEVT3ADCBEVT2ADCBEVT1ADCAEVT4ADCAEVT3ADCAEVT2ADCAEVT1
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-108 XBARCLR5 Register Field Descriptions
BitFieldTypeResetDescription
31CPU3_ADCCHECKEVT4R-0/W1S0hWriting 1 to this bit clears the CPU3_ADCCHECKEVT4 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

30CPU3_ADCCHECKEVT3R-0/W1S0hWriting 1 to this bit clears the CPU3_ADCCHECKEVT3 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

29CPU3_ADCCHECKEVT2R-0/W1S0hWriting 1 to this bit clears the CPU3_ADCCHECKEVT2 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

28CPU3_ADCCHECKEVT1R-0/W1S0hWriting 1 to this bit clears the CPU3_ADCCHECKEVT1 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

27CPU2_ADCCHECKEVT4R-0/W1S0hWriting 1 to this bit clears the CPU2_ADCCHECKEVT4 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

26CPU2_ADCCHECKEVT3R-0/W1S0hWriting 1 to this bit clears the CPU2_ADCCHECKEVT3 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

25CPU2_ADCCHECKEVT2R-0/W1S0hWriting 1 to this bit clears the CPU2_ADCCHECKEVT2 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

24CPU2_ADCCHECKEVT1R-0/W1S0hWriting 1 to this bit clears the CPU2_ADCCHECKEVT1 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

23CPU1_ADCCHECKEVT4R-0/W1S0hWriting 1 to this bit clears the CPU1_ADCCHECKEVT4 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

22CPU1_ADCCHECKEVT3R-0/W1S0hWriting 1 to this bit clears the CPU1_ADCCHECKEVT3 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

21CPU1_ADCCHECKEVT2R-0/W1S0hWriting 1 to this bit clears the CPU1_ADCCHECKEVT2 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20CPU1_ADCCHECKEVT1R-0/W1S0hWriting 1 to this bit clears the CPU1_ADCCHECKEVT1 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

19ADCEEVT4R-0/W1S0hWriting 1 to this bit clears the ADCEEVT4 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

18ADCEEVT3R-0/W1S0hWriting 1 to this bit clears the ADCEEVT3 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

17ADCEEVT2R-0/W1S0hWriting 1 to this bit clears the ADCEEVT2 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16ADCEEVT1R-0/W1S0hWriting 1 to this bit clears the ADCEEVT1 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15ADCDEVT4R-0/W1S0hWriting 1 to this bit clears the ADCDEVT4 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

14ADCDEVT3R-0/W1S0hWriting 1 to this bit clears the ADCDEVT3 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

13ADCDEVT2R-0/W1S0hWriting 1 to this bit clears the ADCDEVT2 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

12ADCDEVT1R-0/W1S0hWriting 1 to this bit clears the ADCDEVT1 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

11ADCCEVT4R-0/W1S0hWriting 1 to this bit clears the ADCCEVT4 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10ADCCEVT3R-0/W1S0hWriting 1 to this bit clears the ADCCEVT3 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9ADCCEVT2R-0/W1S0hWriting 1 to this bit clears the ADCCEVT2 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8ADCCEVT1R-0/W1S0hWriting 1 to this bit clears the ADCCEVT1 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7ADCBEVT4R-0/W1S0hWriting 1 to this bit clears the ADCBEVT4 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

6ADCBEVT3R-0/W1S0hWriting 1 to this bit clears the ADCBEVT3 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

5ADCBEVT2R-0/W1S0hWriting 1 to this bit clears the ADCBEVT2 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4ADCBEVT1R-0/W1S0hWriting 1 to this bit clears the ADCBEVT1 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3ADCAEVT4R-0/W1S0hWriting 1 to this bit clears the ADCAEVT4 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2ADCAEVT3R-0/W1S0hWriting 1 to this bit clears the ADCAEVT3 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1ADCAEVT2R-0/W1S0hWriting 1 to this bit clears the ADCAEVT2 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0ADCAEVT1R-0/W1S0hWriting 1 to this bit clears the ADCAEVT1 bit in the XBARFLG5 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.24 XBARCLR6 Register (Offset = 114h) [Reset = 00000000h]

XBARCLR6 is shown in Figure 20-86 and described in Table 20-109.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-86 XBARCLR6 Register
3130292827262524
ECATSYNC1ECATSYNC0WADI1OUT7WADI1OUT6WADI1OUT5WADI1OUT4WADI1OUT3WADI1OUT2
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
WADI1OUT1WADI1OUT0RESERVEDRESERVEDFSID_RX_TRIG1FSIC_RX_TRIG1FSIB_RX_TRIG1FSIA_RX_TRIG1
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDCLB6_OUT5CLB6_OUT4CLB5_OUT5CLB5_OUT4
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
CLB4_OUT5CLB4_OUT4CLB3_OUT5CLB3_OUT4CLB2_OUT5CLB2_OUT4CLB1_OUT5CLB1_OUT4
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-109 XBARCLR6 Register Field Descriptions
BitFieldTypeResetDescription
31ECATSYNC1R-0/W1S0hWriting 1 to this bit clears the ECATSYNC1 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

30ECATSYNC0R-0/W1S0hWriting 1 to this bit clears the ECATSYNC0 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

29WADI1OUT7R-0/W1S0hWriting 1 to this bit clears the WADI1OUT7 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

28WADI1OUT6R-0/W1S0hWriting 1 to this bit clears the WADI1OUT6 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

27WADI1OUT5R-0/W1S0hWriting 1 to this bit clears the WADI1OUT5 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

26WADI1OUT4R-0/W1S0hWriting 1 to this bit clears the WADI1OUT4 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

25WADI1OUT3R-0/W1S0hWriting 1 to this bit clears the WADI1OUT3 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

24WADI1OUT2R-0/W1S0hWriting 1 to this bit clears the WADI1OUT2 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

23WADI1OUT1R-0/W1S0hWriting 1 to this bit clears the WADI1OUT1 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

22WADI1OUT0R-0/W1S0hWriting 1 to this bit clears the WADI1OUT0 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

21RESERVEDR-0/W1S0hReserved
20RESERVEDR-0/W1S0hReserved
19FSID_RX_TRIG1R-0/W1S0hWriting 1 to this bit clears the FSID_RX_TRIG1 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

18FSIC_RX_TRIG1R-0/W1S0hWriting 1 to this bit clears the FSIC_RX_TRIG1 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

17FSIB_RX_TRIG1R-0/W1S0hWriting 1 to this bit clears the FSIB_RX_TRIG1 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16FSIA_RX_TRIG1R-0/W1S0hWriting 1 to this bit clears the FSIA_RX_TRIG1 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15RESERVEDR-0/W1S0hReserved
14RESERVEDR-0/W1S0hReserved
13RESERVEDR-0/W1S0hReserved
12RESERVEDR-0/W1S0hReserved
11CLB6_OUT5R-0/W1S0hWriting 1 to this bit clears the CLB6_OUT5 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10CLB6_OUT4R-0/W1S0hWriting 1 to this bit clears the CLB6_OUT4 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9CLB5_OUT5R-0/W1S0hWriting 1 to this bit clears the CLB5_OUT5 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8CLB5_OUT4R-0/W1S0hWriting 1 to this bit clears the CLB5_OUT4 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7CLB4_OUT5R-0/W1S0hWriting 1 to this bit clears the CLB4_OUT5 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

6CLB4_OUT4R-0/W1S0hWriting 1 to this bit clears the CLB4_OUT4 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

5CLB3_OUT5R-0/W1S0hWriting 1 to this bit clears the CLB3_OUT5 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4CLB3_OUT4R-0/W1S0hWriting 1 to this bit clears the CLB3_OUT4 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3CLB2_OUT5R-0/W1S0hWriting 1 to this bit clears the CLB2_OUT5 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2CLB2_OUT4R-0/W1S0hWriting 1 to this bit clears the CLB2_OUT4 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1CLB1_OUT5R-0/W1S0hWriting 1 to this bit clears the CLB1_OUT5 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0CLB1_OUT4R-0/W1S0hWriting 1 to this bit clears the CLB1_OUT4 bit in the XBARFLG6 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.25 XBARCLR7 Register (Offset = 118h) [Reset = 00000000h]

XBARCLR7 is shown in Figure 20-87 and described in Table 20-110.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-87 XBARCLR7 Register
3130292827262524
WADI2OUT7WADI2OUT6WADI2OUT5WADI2OUT4WADI2OUT3WADI2OUT2WADI2OUT1WADI2OUT0
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDEXTSYNCOUTESMGENEVTADCSOCBADCSOCA
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
RESERVEDRESERVEDECAP6_TRIPOUTECAP5_TRIPOUTECAP4_TRIPOUTECAP3_TRIPOUTECAP2_TRIPOUTECAP1_TRIPOUT
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
RESERVEDRESERVEDECAP6_OUTECAP5_OUTECAP4_OUTECAP3_OUTECAP2_OUTECAP1_OUT
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-110 XBARCLR7 Register Field Descriptions
BitFieldTypeResetDescription
31WADI2OUT7R-0/W1S0hWriting 1 to this bit clears the WADI2OUT7 bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

30WADI2OUT6R-0/W1S0hWriting 1 to this bit clears the WADI2OUT6 bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

29WADI2OUT5R-0/W1S0hWriting 1 to this bit clears the WADI2OUT5 bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

28WADI2OUT4R-0/W1S0hWriting 1 to this bit clears the WADI2OUT4 bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

27WADI2OUT3R-0/W1S0hWriting 1 to this bit clears the WADI2OUT3 bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

26WADI2OUT2R-0/W1S0hWriting 1 to this bit clears the WADI2OUT2 bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

25WADI2OUT1R-0/W1S0hWriting 1 to this bit clears the WADI2OUT1 bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

24WADI2OUT0R-0/W1S0hWriting 1 to this bit clears the WADI2OUT0 bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

23RESERVEDR-0/W1S0hReserved
22RESERVEDR-0/W1S0hReserved
21RESERVEDR-0/W1S0hReserved
20RESERVEDR-0/W1S0hReserved
19EXTSYNCOUTR-0/W1S0hWriting 1 to this bit clears the EXTSYNCOUT bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

18ESMGENEVTR-0/W1S0hWriting 1 to this bit clears the ESMGENEVT bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

17ADCSOCBR-0/W1S0hWriting 1 to this bit clears the ADCSOCB bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16ADCSOCAR-0/W1S0hWriting 1 to this bit clears the ADCSOCA bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15RESERVEDR-0/W1S0hReserved
14RESERVEDR-0/W1S0hReserved
13ECAP6_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the ECAP6_TRIPOUT bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

12ECAP5_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the ECAP5_TRIPOUT bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

11ECAP4_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the ECAP4_TRIPOUT bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10ECAP3_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the ECAP3_TRIPOUT bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9ECAP2_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the ECAP2_TRIPOUT bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8ECAP1_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the ECAP1_TRIPOUT bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7RESERVEDR-0/W1S0hReserved
6RESERVEDR-0/W1S0hReserved
5ECAP6_OUTR-0/W1S0hWriting 1 to this bit clears the ECAP6_OUT bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4ECAP5_OUTR-0/W1S0hWriting 1 to this bit clears the ECAP5_OUT bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3ECAP4_OUTR-0/W1S0hWriting 1 to this bit clears the ECAP4_OUT bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2ECAP3_OUTR-0/W1S0hWriting 1 to this bit clears the ECAP3_OUT bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1ECAP2_OUTR-0/W1S0hWriting 1 to this bit clears the ECAP2_OUT bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0ECAP1_OUTR-0/W1S0hWriting 1 to this bit clears the ECAP1_OUT bit in the XBARFLG7 register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.26 XBARCLR8 Register (Offset = 11Ch) [Reset = 00000000h]

XBARCLR8 is shown in Figure 20-88 and described in Table 20-111.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-88 XBARCLR8 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDEPWM18_TRIPOUTEPWM17_TRIPOUT
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
EPWM16_TRIPOUTEPWM15_TRIPOUTEPWM14_TRIPOUTEPWM13_TRIPOUTEPWM12_TRIPOUTEPWM11_TRIPOUTEPWM10_TRIPOUTEPWM9_TRIPOUT
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
EPWM8_TRIPOUTEPWM7_TRIPOUTEPWM6_TRIPOUTEPWM5_TRIPOUTEPWM4_TRIPOUTEPWM3_TRIPOUTEPWM2_TRIPOUTEPWM1_TRIPOUT
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-111 XBARCLR8 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR-0/W1S0hReserved
30RESERVEDR-0/W1S0hReserved
29RESERVEDR-0/W1S0hReserved
28RESERVEDR-0/W1S0hReserved
27RESERVEDR-0/W1S0hReserved
26RESERVEDR-0/W1S0hReserved
25RESERVEDR-0/W1S0hReserved
24RESERVEDR-0/W1S0hReserved
23RESERVEDR-0/W1S0hReserved
22RESERVEDR-0/W1S0hReserved
21RESERVEDR-0/W1S0hReserved
20RESERVEDR-0/W1S0hReserved
19RESERVEDR-0/W1S0hReserved
18RESERVEDR-0/W1S0hReserved
17EPWM18_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM18_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16EPWM17_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM17_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15EPWM16_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM16_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

14EPWM15_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM15_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

13EPWM14_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM14_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

12EPWM13_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM13_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

11EPWM12_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM12_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10EPWM11_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM11_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9EPWM10_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM10_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8EPWM9_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM9_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7EPWM8_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM8_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

6EPWM7_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM7_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

5EPWM6_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM6_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4EPWM5_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM5_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3EPWM4_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM4_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2EPWM3_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM3_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1EPWM2_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM2_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0EPWM1_TRIPOUTR-0/W1S0hWriting 1 to this bit clears the EPWM1_TRIPOUT bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.27 XBARCLR9 Register (Offset = 120h) [Reset = 00000000h]

XBARCLR9 is shown in Figure 20-89 and described in Table 20-112.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-89 XBARCLR9 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDEPWM18_DEL_TRIPEPWM17_DEL_TRIP
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
EPWM16_DEL_TRIPEPWM15_DEL_TRIPEPWM14_DEL_TRIPEPWM13_DEL_TRIPEPWM12_DEL_TRIPEPWM11_DEL_TRIPEPWM10_DEL_TRIPEPWM9_DEL_TRIP
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
EPWM8_DEL_TRIPEPWM7_DEL_TRIPEPWM6_DEL_TRIPEPWM5_DEL_TRIPEPWM4_DEL_TRIPEPWM3_DEL_TRIPEPWM2_DEL_TRIPEPWM1_DEL_TRIP
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-112 XBARCLR9 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR-0/W1S0hReserved
30RESERVEDR-0/W1S0hReserved
29RESERVEDR-0/W1S0hReserved
28RESERVEDR-0/W1S0hReserved
27RESERVEDR-0/W1S0hReserved
26RESERVEDR-0/W1S0hReserved
25RESERVEDR-0/W1S0hReserved
24RESERVEDR-0/W1S0hReserved
23RESERVEDR-0/W1S0hReserved
22RESERVEDR-0/W1S0hReserved
21RESERVEDR-0/W1S0hReserved
20RESERVEDR-0/W1S0hReserved
19RESERVEDR-0/W1S0hReserved
18RESERVEDR-0/W1S0hReserved
17EPWM18_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM18_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16EPWM17_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM17_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15EPWM16_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM16_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

14EPWM15_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM15_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

13EPWM14_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM14_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

12EPWM13_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM13_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

11EPWM12_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM12_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10EPWM11_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM11_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9EPWM10_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM10_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8EPWM9_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM9_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7EPWM8_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM8_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

6EPWM7_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM7_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

5EPWM6_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM6_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4EPWM5_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM5_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3EPWM4_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM4_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2EPWM3_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM3_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1EPWM2_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM2_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0EPWM1_DEL_TRIPR-0/W1S0hWriting 1 to this bit clears the EPWM1_DEL_TRIP bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.28 XBARCLR10 Register (Offset = 124h) [Reset = 00000000h]

XBARCLR10 is shown in Figure 20-90 and described in Table 20-113.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-90 XBARCLR10 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDEPWM18_DEL_ACTIVEEPWM17_DEL_ACTIVE
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
EPWM16_DEL_ACTIVEEPWM15_DEL_ACTIVEEPWM14_DEL_ACTIVEEPWM13_DEL_ACTIVEEPWM12_DEL_ACTIVEEPWM11_DEL_ACTIVEEPWM10_DEL_ACTIVEEPWM9_DEL_ACTIVE
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
EPWM8_DEL_ACTIVEEPWM7_DEL_ACTIVEEPWM6_DEL_ACTIVEEPWM5_DEL_ACTIVEEPWM4_DEL_ACTIVEEPWM3_DEL_ACTIVEEPWM2_DEL_ACTIVEEPWM1_DEL_ACTIVE
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-113 XBARCLR10 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR-0/W1S0hReserved
30RESERVEDR-0/W1S0hReserved
29RESERVEDR-0/W1S0hReserved
28RESERVEDR-0/W1S0hReserved
27RESERVEDR-0/W1S0hReserved
26RESERVEDR-0/W1S0hReserved
25RESERVEDR-0/W1S0hReserved
24RESERVEDR-0/W1S0hReserved
23RESERVEDR-0/W1S0hReserved
22RESERVEDR-0/W1S0hReserved
21RESERVEDR-0/W1S0hReserved
20RESERVEDR-0/W1S0hReserved
19RESERVEDR-0/W1S0hReserved
18RESERVEDR-0/W1S0hReserved
17EPWM18_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM18_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16EPWM17_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM17_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15EPWM16_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM16_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

14EPWM15_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM15_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

13EPWM14_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM14_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

12EPWM13_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM13_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

11EPWM12_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM12_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10EPWM11_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM11_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9EPWM10_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM10_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8EPWM9_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM9_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7EPWM8_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM8_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

6EPWM7_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM7_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

5EPWM6_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM6_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4EPWM5_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM5_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3EPWM4_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM4_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2EPWM3_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM3_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1EPWM2_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM2_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0EPWM1_DEL_ACTIVER-0/W1S0hWriting 1 to this bit clears the EPWM1_DEL_ACTIVE bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.29 XBARCLR11 Register (Offset = 128h) [Reset = 00000000h]

XBARCLR11 is shown in Figure 20-91 and described in Table 20-114.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-91 XBARCLR11 Register
3130292827262524
EPWM16_B0_sclkEPWM16_A0_sclkEPWM15_B0_sclkEPWM15_A0_sclkEPWM14_B0_sclkEPWM14_A0_sclkEPWM13_B0_sclkEPWM13_A0_sclk
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
EPWM12_B0_sclkEPWM12_A0_sclkEPWM11_B0_sclkEPWM11_A0_sclkEPWM10_B0_sclkEPWM10_A0_sclkEPWM9_B0_sclkEPWM9_A0_sclk
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
EPWM8_B0_sclkEPWM8_A0_sclkEPWM7_B0_sclkEPWM7_A0_sclkEPWM6_B0_sclkEPWM6_A0_sclkEPWM5_B0_sclkEPWM5_A0_sclk
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
EPWM4_B0_sclkEPWM4_A0_sclkEPWM3_B0_sclkEPWM3_A0_sclkEPWM2_B0_sclkEPWM2_A0_sclkEPWM1_B0_sclkEPWM1_A0_sclk
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-114 XBARCLR11 Register Field Descriptions
BitFieldTypeResetDescription
31EPWM16_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM16_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

30EPWM16_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM16_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

29EPWM15_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM15_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

28EPWM15_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM15_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

27EPWM14_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM14_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

26EPWM14_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM14_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

25EPWM13_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM13_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

24EPWM13_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM13_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

23EPWM12_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM12_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

22EPWM12_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM12_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

21EPWM11_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM11_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20EPWM11_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM11_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

19EPWM10_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM10_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

18EPWM10_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM10_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

17EPWM9_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM9_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16EPWM9_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM9_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15EPWM8_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM8_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

14EPWM8_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM8_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

13EPWM7_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM7_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

12EPWM7_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM7_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

11EPWM6_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM6_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10EPWM6_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM6_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9EPWM5_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM5_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8EPWM5_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM5_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7EPWM4_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM4_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

6EPWM4_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM4_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

5EPWM3_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM3_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4EPWM3_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM3_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3EPWM2_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM2_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2EPWM2_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM2_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1EPWM1_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM1_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0EPWM1_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM1_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.30 XBARCLR12 Register (Offset = 12Ch) [Reset = 00000000h]

XBARCLR12 is shown in Figure 20-92 and described in Table 20-115.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-92 XBARCLR12 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDEPWM18_B0_sclkEPWM18_A0_sclkEPWM17_B0_sclkEPWM17_A0_sclk
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-115 XBARCLR12 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR-0/W1S0hReserved
30RESERVEDR-0/W1S0hReserved
29RESERVEDR-0/W1S0hReserved
28RESERVEDR-0/W1S0hReserved
27RESERVEDR-0/W1S0hReserved
26RESERVEDR-0/W1S0hReserved
25RESERVEDR-0/W1S0hReserved
24RESERVEDR-0/W1S0hReserved
23RESERVEDR-0/W1S0hReserved
22RESERVEDR-0/W1S0hReserved
21RESERVEDR-0/W1S0hReserved
20RESERVEDR-0/W1S0hReserved
19RESERVEDR-0/W1S0hReserved
18RESERVEDR-0/W1S0hReserved
17RESERVEDR-0/W1S0hReserved
16RESERVEDR-0/W1S0hReserved
15RESERVEDR-0/W1S0hReserved
14RESERVEDR-0/W1S0hReserved
13RESERVEDR-0/W1S0hReserved
12RESERVEDR-0/W1S0hReserved
11RESERVEDR-0/W1S0hReserved
10RESERVEDR-0/W1S0hReserved
9RESERVEDR-0/W1S0hReserved
8RESERVEDR-0/W1S0hReserved
7RESERVEDR-0/W1S0hReserved
6RESERVEDR-0/W1S0hReserved
5RESERVEDR-0/W1S0hReserved
4RESERVEDR-0/W1S0hReserved
3EPWM18_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM18_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2EPWM18_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM18_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1EPWM17_B0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM17_B0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0EPWM17_A0_sclkR-0/W1S0hWriting 1 to this bit clears the EPWM17_A0_sclk bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.31 XBARCLR13 Register (Offset = 130h) [Reset = 00000000h]

XBARCLR13 is shown in Figure 20-93 and described in Table 20-116.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-93 XBARCLR13 Register
3130292827262524
MDL16_OUTBMDL16_OUTAMDL15_OUTBMDL15_OUTAMDL14_OUTBMDL14_OUTAMDL13_OUTBMDL13_OUTA
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
MDL12_OUTBMDL12_OUTAMDL11_OUTBMDL11_OUTAMDL10_OUTBMDL10_OUTAMDL9_OUTBMDL9_OUTA
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
MDL8_OUTBMDL8_OUTAMDL7_OUTBMDL7_OUTAMDL6_OUTBMDL6_OUTAMDL5_OUTBMDL5_OUTA
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
MDL4_OUTBMDL4_OUTAMDL3_OUTBMDL3_OUTAMDL2_OUTBMDL2_OUTAMDL1_OUTBMDL1_OUTA
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-116 XBARCLR13 Register Field Descriptions
BitFieldTypeResetDescription
31MDL16_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL16_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

30MDL16_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL16_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

29MDL15_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL15_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

28MDL15_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL15_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

27MDL14_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL14_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

26MDL14_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL14_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

25MDL13_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL13_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

24MDL13_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL13_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

23MDL12_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL12_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

22MDL12_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL12_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

21MDL11_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL11_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20MDL11_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL11_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

19MDL10_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL10_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

18MDL10_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL10_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

17MDL9_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL9_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16MDL9_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL9_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15MDL8_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL8_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

14MDL8_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL8_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

13MDL7_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL7_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

12MDL7_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL7_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

11MDL6_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL6_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10MDL6_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL6_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9MDL5_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL5_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8MDL5_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL5_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7MDL4_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL4_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

6MDL4_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL4_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

5MDL3_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL3_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4MDL3_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL3_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3MDL2_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL2_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2MDL2_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL2_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1MDL1_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL1_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0MDL1_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL1_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.32 XBARCLR14 Register (Offset = 134h) [Reset = 00000000h]

XBARCLR14 is shown in Figure 20-94 and described in Table 20-117.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-94 XBARCLR14 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDMDL18_OUTBMDL18_OUTAMDL17_OUTBMDL17_OUTA
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-117 XBARCLR14 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR-0/W1S0hReserved
30RESERVEDR-0/W1S0hReserved
29RESERVEDR-0/W1S0hReserved
28RESERVEDR-0/W1S0hReserved
27RESERVEDR-0/W1S0hReserved
26RESERVEDR-0/W1S0hReserved
25RESERVEDR-0/W1S0hReserved
24RESERVEDR-0/W1S0hReserved
23RESERVEDR-0/W1S0hReserved
22RESERVEDR-0/W1S0hReserved
21RESERVEDR-0/W1S0hReserved
20RESERVEDR-0/W1S0hReserved
19RESERVEDR-0/W1S0hReserved
18RESERVEDR-0/W1S0hReserved
17RESERVEDR-0/W1S0hReserved
16RESERVEDR-0/W1S0hReserved
15RESERVEDR-0/W1S0hReserved
14RESERVEDR-0/W1S0hReserved
13RESERVEDR-0/W1S0hReserved
12RESERVEDR-0/W1S0hReserved
11RESERVEDR-0/W1S0hReserved
10RESERVEDR-0/W1S0hReserved
9RESERVEDR-0/W1S0hReserved
8RESERVEDR-0/W1S0hReserved
7RESERVEDR-0/W1S0hReserved
6RESERVEDR-0/W1S0hReserved
5RESERVEDR-0/W1S0hReserved
4RESERVEDR-0/W1S0hReserved
3MDL18_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL18_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2MDL18_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL18_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1MDL17_OUTBR-0/W1S0hWriting 1 to this bit clears the MDL17_OUTB bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0MDL17_OUTAR-0/W1S0hWriting 1 to this bit clears the MDL17_OUTA bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.33 XBARCLR15 Register (Offset = 138h) [Reset = 00000000h]

XBARCLR15 is shown in Figure 20-95 and described in Table 20-118.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-95 XBARCLR15 Register
3130292827262524
CLB6_OUT1CLB6_OUT0CLB5_OUT7CLB5_OUT6CLB5_OUT3CLB5_OUT2CLB5_OUT1CLB5_OUT0
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
CLB4_OUT7CLB4_OUT6CLB4_OUT3CLB4_OUT2CLB4_OUT1CLB4_OUT0CLB3_OUT7CLB3_OUT6
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
CLB3_OUT3CLB3_OUT2CLB3_OUT1CLB3_OUT0CLB2_OUT7CLB2_OUT6CLB2_OUT3CLB2_OUT2
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
CLB2_OUT1CLB2_OUT0CLB1_OUT7CLB1_OUT6CLB1_OUT3CLB1_OUT2CLB1_OUT1CLB1_OUT0
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-118 XBARCLR15 Register Field Descriptions
BitFieldTypeResetDescription
31CLB6_OUT1R-0/W1S0hWriting 1 to this bit clears the CLB6_OUT1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

30CLB6_OUT0R-0/W1S0hWriting 1 to this bit clears the CLB6_OUT0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

29CLB5_OUT7R-0/W1S0hWriting 1 to this bit clears the CLB5_OUT7 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

28CLB5_OUT6R-0/W1S0hWriting 1 to this bit clears the CLB5_OUT6 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

27CLB5_OUT3R-0/W1S0hWriting 1 to this bit clears the CLB5_OUT3 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

26CLB5_OUT2R-0/W1S0hWriting 1 to this bit clears the CLB5_OUT2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

25CLB5_OUT1R-0/W1S0hWriting 1 to this bit clears the CLB5_OUT1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

24CLB5_OUT0R-0/W1S0hWriting 1 to this bit clears the CLB5_OUT0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

23CLB4_OUT7R-0/W1S0hWriting 1 to this bit clears the CLB4_OUT7 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

22CLB4_OUT6R-0/W1S0hWriting 1 to this bit clears the CLB4_OUT6 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

21CLB4_OUT3R-0/W1S0hWriting 1 to this bit clears the CLB4_OUT3 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20CLB4_OUT2R-0/W1S0hWriting 1 to this bit clears the CLB4_OUT2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

19CLB4_OUT1R-0/W1S0hWriting 1 to this bit clears the CLB4_OUT1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

18CLB4_OUT0R-0/W1S0hWriting 1 to this bit clears the CLB4_OUT0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

17CLB3_OUT7R-0/W1S0hWriting 1 to this bit clears the CLB3_OUT7 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16CLB3_OUT6R-0/W1S0hWriting 1 to this bit clears the CLB3_OUT6 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15CLB3_OUT3R-0/W1S0hWriting 1 to this bit clears the CLB3_OUT3 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

14CLB3_OUT2R-0/W1S0hWriting 1 to this bit clears the CLB3_OUT2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

13CLB3_OUT1R-0/W1S0hWriting 1 to this bit clears the CLB3_OUT1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

12CLB3_OUT0R-0/W1S0hWriting 1 to this bit clears the CLB3_OUT0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

11CLB2_OUT7R-0/W1S0hWriting 1 to this bit clears the CLB2_OUT7 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10CLB2_OUT6R-0/W1S0hWriting 1 to this bit clears the CLB2_OUT6 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9CLB2_OUT3R-0/W1S0hWriting 1 to this bit clears the CLB2_OUT3 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8CLB2_OUT2R-0/W1S0hWriting 1 to this bit clears the CLB2_OUT2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7CLB2_OUT1R-0/W1S0hWriting 1 to this bit clears the CLB2_OUT1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

6CLB2_OUT0R-0/W1S0hWriting 1 to this bit clears the CLB2_OUT0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

5CLB1_OUT7R-0/W1S0hWriting 1 to this bit clears the CLB1_OUT7 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4CLB1_OUT6R-0/W1S0hWriting 1 to this bit clears the CLB1_OUT6 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3CLB1_OUT3R-0/W1S0hWriting 1 to this bit clears the CLB1_OUT3 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2CLB1_OUT2R-0/W1S0hWriting 1 to this bit clears the CLB1_OUT2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1CLB1_OUT1R-0/W1S0hWriting 1 to this bit clears the CLB1_OUT1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0CLB1_OUT0R-0/W1S0hWriting 1 to this bit clears the CLB1_OUT0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.34 XBARCLR16 Register (Offset = 13Ch) [Reset = 00000000h]

XBARCLR16 is shown in Figure 20-96 and described in Table 20-119.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-96 XBARCLR16 Register
3130292827262524
EPG1_EPGOUT3EPG1_EPGOUT2EPG1_EPGOUT1EPG1_EPGOUT0RESERVEDRESERVEDRESERVEDRESERVED
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
ADCE_EXTMUXSEL3ADCE_EXTMUXSEL2ADCE_EXTMUXSEL1ADCE_EXTMUXSEL0ADCD_EXTMUXSEL3ADCD_EXTMUXSEL2ADCD_EXTMUXSEL1ADCD_EXTMUXSEL0
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
ADCC_EXTMUXSEL3ADCC_EXTMUXSEL2ADCC_EXTMUXSEL1ADCC_EXTMUXSEL0ADCB_EXTMUXSEL3ADCB_EXTMUXSEL2ADCB_EXTMUXSEL1ADCB_EXTMUXSEL0
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
ADCA_EXTMUXSEL3ADCA_EXTMUXSEL2ADCA_EXTMUXSEL1ADCA_EXTMUXSEL0CLB6_OUT7CLB6_OUT6CLB6_OUT3CLB6_OUT2
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-119 XBARCLR16 Register Field Descriptions
BitFieldTypeResetDescription
31EPG1_EPGOUT3R-0/W1S0hWriting 1 to this bit clears the EPG1_EPGOUT3 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

30EPG1_EPGOUT2R-0/W1S0hWriting 1 to this bit clears the EPG1_EPGOUT2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

29EPG1_EPGOUT1R-0/W1S0hWriting 1 to this bit clears the EPG1_EPGOUT1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

28EPG1_EPGOUT0R-0/W1S0hWriting 1 to this bit clears the EPG1_EPGOUT0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

27RESERVEDR-0/W1S0hReserved
26RESERVEDR-0/W1S0hReserved
25RESERVEDR-0/W1S0hReserved
24RESERVEDR-0/W1S0hReserved
23ADCE_EXTMUXSEL3R-0/W1S0hWriting 1 to this bit clears the ADCE_EXTMUXSEL3 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

22ADCE_EXTMUXSEL2R-0/W1S0hWriting 1 to this bit clears the ADCE_EXTMUXSEL2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

21ADCE_EXTMUXSEL1R-0/W1S0hWriting 1 to this bit clears the ADCE_EXTMUXSEL1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20ADCE_EXTMUXSEL0R-0/W1S0hWriting 1 to this bit clears the ADCE_EXTMUXSEL0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

19ADCD_EXTMUXSEL3R-0/W1S0hWriting 1 to this bit clears the ADCD_EXTMUXSEL3 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

18ADCD_EXTMUXSEL2R-0/W1S0hWriting 1 to this bit clears the ADCD_EXTMUXSEL2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

17ADCD_EXTMUXSEL1R-0/W1S0hWriting 1 to this bit clears the ADCD_EXTMUXSEL1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16ADCD_EXTMUXSEL0R-0/W1S0hWriting 1 to this bit clears the ADCD_EXTMUXSEL0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15ADCC_EXTMUXSEL3R-0/W1S0hWriting 1 to this bit clears the ADCC_EXTMUXSEL3 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

14ADCC_EXTMUXSEL2R-0/W1S0hWriting 1 to this bit clears the ADCC_EXTMUXSEL2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

13ADCC_EXTMUXSEL1R-0/W1S0hWriting 1 to this bit clears the ADCC_EXTMUXSEL1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

12ADCC_EXTMUXSEL0R-0/W1S0hWriting 1 to this bit clears the ADCC_EXTMUXSEL0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

11ADCB_EXTMUXSEL3R-0/W1S0hWriting 1 to this bit clears the ADCB_EXTMUXSEL3 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10ADCB_EXTMUXSEL2R-0/W1S0hWriting 1 to this bit clears the ADCB_EXTMUXSEL2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9ADCB_EXTMUXSEL1R-0/W1S0hWriting 1 to this bit clears the ADCB_EXTMUXSEL1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8ADCB_EXTMUXSEL0R-0/W1S0hWriting 1 to this bit clears the ADCB_EXTMUXSEL0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7ADCA_EXTMUXSEL3R-0/W1S0hWriting 1 to this bit clears the ADCA_EXTMUXSEL3 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

6ADCA_EXTMUXSEL2R-0/W1S0hWriting 1 to this bit clears the ADCA_EXTMUXSEL2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

5ADCA_EXTMUXSEL1R-0/W1S0hWriting 1 to this bit clears the ADCA_EXTMUXSEL1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4ADCA_EXTMUXSEL0R-0/W1S0hWriting 1 to this bit clears the ADCA_EXTMUXSEL0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3CLB6_OUT7R-0/W1S0hWriting 1 to this bit clears the CLB6_OUT7 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2CLB6_OUT6R-0/W1S0hWriting 1 to this bit clears the CLB6_OUT6 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1CLB6_OUT3R-0/W1S0hWriting 1 to this bit clears the CLB6_OUT3 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0CLB6_OUT2R-0/W1S0hWriting 1 to this bit clears the CLB6_OUT2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.35 XBARCLR17 Register (Offset = 140h) [Reset = 00000000h]

XBARCLR17 is shown in Figure 20-97 and described in Table 20-120.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-97 XBARCLR17 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMCANF_FEVT2MCANF_FEVT1
R-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
MCANF_FEVT0MCANE_FEVT2MCANE_FEVT1MCANE_FEVT0MCAND_FEVT2MCAND_FEVT1MCAND_FEVT0MCANC_FEVT2
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
MCANC_FEVT1MCANC_FEVT0MCANB_FEVT2MCANB_FEVT1MCANB_FEVT0MCANA_FEVT2MCANA_FEVT1MCANA_FEVT0
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-120 XBARCLR17 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17MCANF_FEVT2R-0/W1S0hWriting 1 to this bit clears the MCANF_FEVT2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

16MCANF_FEVT1R-0/W1S0hWriting 1 to this bit clears the MCANF_FEVT1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

15MCANF_FEVT0R-0/W1S0hWriting 1 to this bit clears the MCANF_FEVT0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

14MCANE_FEVT2R-0/W1S0hWriting 1 to this bit clears the MCANE_FEVT2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

13MCANE_FEVT1R-0/W1S0hWriting 1 to this bit clears the MCANE_FEVT1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

12MCANE_FEVT0R-0/W1S0hWriting 1 to this bit clears the MCANE_FEVT0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

11MCAND_FEVT2R-0/W1S0hWriting 1 to this bit clears the MCAND_FEVT2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

10MCAND_FEVT1R-0/W1S0hWriting 1 to this bit clears the MCAND_FEVT1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

9MCAND_FEVT0R-0/W1S0hWriting 1 to this bit clears the MCAND_FEVT0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

8MCANC_FEVT2R-0/W1S0hWriting 1 to this bit clears the MCANC_FEVT2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

7MCANC_FEVT1R-0/W1S0hWriting 1 to this bit clears the MCANC_FEVT1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

6MCANC_FEVT0R-0/W1S0hWriting 1 to this bit clears the MCANC_FEVT0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

5MCANB_FEVT2R-0/W1S0hWriting 1 to this bit clears the MCANB_FEVT2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

4MCANB_FEVT1R-0/W1S0hWriting 1 to this bit clears the MCANB_FEVT1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

3MCANB_FEVT0R-0/W1S0hWriting 1 to this bit clears the MCANB_FEVT0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

2MCANA_FEVT2R-0/W1S0hWriting 1 to this bit clears the MCANA_FEVT2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

1MCANA_FEVT1R-0/W1S0hWriting 1 to this bit clears the MCANA_FEVT1 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

0MCANA_FEVT0R-0/W1S0hWriting 1 to this bit clears the MCANA_FEVT0 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn

20.5.9.36 XBARCLR18 Register (Offset = 144h) [Reset = 00000000h]

XBARCLR18 is shown in Figure 20-98 and described in Table 20-121.

Return to the Summary Table.

This register is used to clear the flag(s) in the XBARFLG register.

1: Clears the corresponding bit in the XBARFLG register.
0: Writing 0 has no effect

Figure 20-98 XBARCLR18 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCPU3ERADEVT11CPU3ERADEVT10CPU3ERADEVT9CPU3ERADEVT8
R-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
CPU2ERADEVT11CPU2ERADEVT10CPU2ERADEVT9CPU2ERADEVT8CPU1ERADEVT11CPU1ERADEVT10CPU1ERADEVT9CPU1ERADEVT8
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
FSIRXD_TRIG_3FSIRXD_TRIG_2FSIRXC_TRIG_3FSIRXC_TRIG_2FSIRXB_TRIG_3FSIRXB_TRIG_2FSIRXA_TRIG_3FSIRXA_TRIG_2
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 20-121 XBARCLR18 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19CPU3ERADEVT11R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU3ERADEVT11 input was triggered
0: CPU3ERADEVT11 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

18CPU3ERADEVT10R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU3ERADEVT10 input was triggered
0: CPU3ERADEVT10 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

17CPU3ERADEVT9R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU3ERADEVT9 input was triggered
0: CPU3ERADEVT9 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

16CPU3ERADEVT8R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU3ERADEVT8 input was triggered
0: CPU3ERADEVT8 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

15CPU2ERADEVT11R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU2ERADEVT11 input was triggered
0: CPU2ERADEVT11 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

14CPU2ERADEVT10R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU2ERADEVT10 input was triggered
0: CPU2ERADEVT10 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

13CPU2ERADEVT9R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU2ERADEVT9 input was triggered
0: CPU2ERADEVT9 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

12CPU2ERADEVT8R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU2ERADEVT8 input was triggered
0: CPU2ERADEVT8 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

11CPU1ERADEVT11R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU1ERADEVT11 input was triggered
0: CPU1ERADEVT11 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

10CPU1ERADEVT10R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU1ERADEVT10 input was triggered
0: CPU1ERADEVT10 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

9CPU1ERADEVT9R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU1ERADEVT9 input was triggered
0: CPU1ERADEVT9 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

8CPU1ERADEVT8R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: CPU1ERADEVT8 input was triggered
0: CPU1ERADEVT8 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

7FSIRXD_TRIG_3R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXD_TRIG_3 input was triggered
0: FSIRXD_TRIG_3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

6FSIRXD_TRIG_2R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXD_TRIG_2 input was triggered
0: FSIRXD_TRIG_2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

5FSIRXC_TRIG_3R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXC_TRIG_3 input was triggered
0: FSIRXC_TRIG_3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

4FSIRXC_TRIG_2R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXC_TRIG_2 input was triggered
0: FSIRXC_TRIG_2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

3FSIRXB_TRIG_3R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXB_TRIG_3 input was triggered
0: FSIRXB_TRIG_3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

2FSIRXB_TRIG_2R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXB_TRIG_2 input was triggered
0: FSIRXB_TRIG_2 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

1FSIRXA_TRIG_3R-0/W1S0hThis register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.

1: FSIRXA_TRIG_3 input was triggered
0: FSIRXA_TRIG_3 Input was not triggered

Note:
[1] setting of this bit has priority over clear by software

Reset type: CPU1.SYSRSn

0FSIRXA_TRIG_2R-0/W1S0hWriting 1 to this bit clears the FSIRXA_TRIG_2 bit in this register.
Writing 0 has no effect

Reset type: CPU1.SYSRSn