SPRUJ79 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 â–º C29x SYSTEM RESOURCES
    1.     Technical Reference Manual Overview
  4. 2 F29x Processor
    1. 2.1 CPU Architecture
      1. 2.1.1 C29x Related Collateral
    2. 2.2 Lock and Commit Registers
    3. 2.3 C29x CPU Registers
      1. 2.3.1 C29CPU Base Address Table
      2. 2.3.2 C29_RTINT_STACK Registers
      3. 2.3.3 C29_SECCALL_STACK Registers
      4. 2.3.4 C29_SECURE_REGS Registers
      5. 2.3.5 C29_DIAG_REGS Registers
      6. 2.3.6 C29_SELFTEST_REGS Registers
  5. 3 System Control and Interrupts
    1. 3.1  C29x System Control Introduction
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
      2. 3.2.2 Device Configuration Registers
    3. 3.3  Resets
      1. 3.3.1 Reset Sources
      2. 3.3.2 External Reset (XRS)
      3. 3.3.3 Simulate External Reset
      4. 3.3.4 Power-On Reset (POR)
      5. 3.3.5 Debugger Reset (SYSRS)
      6. 3.3.6 Watchdog Reset (WDRS)
      7. 3.3.7 ESM NMI Watchdog Reset (NMIWDRS)
      8. 3.3.8 EtherCAT Slave Controller (ESC) Module Reset Output
    4. 3.4  Safety Features
      1. 3.4.1 Write Protection on Registers
        1. 3.4.1.1 LOCK Protection on System Configuration Registers
        2. 3.4.1.2 EALLOW Protection
      2. 3.4.2 PIPE Vector Address Validity Check
      3. 3.4.3 NMIWDs
      4. 3.4.4 System Control Registers Parity Protection
      5. 3.4.5 ECC Enabled RAMs, Shared RAMs Protection
      6. 3.4.6 ECC Enabled Flash Memory
      7. 3.4.7 ERRORSTS Pin
    5. 3.5  Clocking
      1. 3.5.1 Clock Sources
        1. 3.5.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.5.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.5.1.3 External Oscillator (XTAL)
        4. 3.5.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.5.2 Derived Clocks
        1. 3.5.2.1 Oscillator Clock (OSCCLK)
        2. 3.5.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.5.3 Device Clock Domains
        1. 3.5.3.1 System Clock (PLLSYSCLK)
        2. 3.5.3.2 CPU Clock (CPUCLK)
        3. 3.5.3.3 Peripheral Clock (PERx.SYSCLK)
        4. 3.5.3.4 MCAN Bit Clock
        5. 3.5.3.5 CPU Timer2 Clock (TIMER2CLK)
      4. 3.5.4 External Clock Output (XCLKOUT)
      5. 3.5.5 Clock Connectivity
      6. 3.5.6 Using an External Crystal or Resonator
        1. 3.5.6.1 X1/X2 Precondition Circuit
      7. 3.5.7 PLL
        1. 3.5.7.1 System Clock Setup
        2. 3.5.7.2 SYS PLL Bypass
      8. 3.5.8 Clock (OSCCLK) Failure Detection
        1. 3.5.8.1 Missing Clock Detection Logic
        2. 3.5.8.2 Dual Clock Comparator (DCC)
    6. 3.6  Bus Architecture
      1. 3.6.1 Safe Interconnect
        1. 3.6.1.1 Safe Interconnect for Read Operation
        2. 3.6.1.2 Safe Interconnect for Write Operation
      2. 3.6.2 Peripheral Access Configuration using FRAMESEL
      3. 3.6.3 Bus Arbitration
    7. 3.7  32-Bit CPU Timers 0/1/2
    8. 3.8  Watchdog Timers
      1. 3.8.1 Servicing the Watchdog Timer
      2. 3.8.2 Minimum Window Check
      3. 3.8.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.8.4 Watchdog Operation in Low-Power Modes
      5. 3.8.5 Emulation Considerations
    9. 3.9  Low-Power Modes
      1. 3.9.1 IDLE
      2. 3.9.2 STANDBY
    10. 3.10 Memory Subsystem (MEMSS)
      1. 3.10.1 Introduction
      2. 3.10.2 Features
      3. 3.10.3 Configuration Bits
        1. 3.10.3.1 Memory Initialization
      4. 3.10.4 RAM
        1. 3.10.4.1  MEMSS Architecture
        2. 3.10.4.2  RAM Memory Controller Overview
        3. 3.10.4.3  Memory Controllers
          1. 3.10.4.3.1 128-Bit LPx and CPx Memory Controller
          2. 3.10.4.3.2 64-Bit LDx and CDx Memory Controller
          3. 3.10.4.3.3 M0 Memory Controller
        4. 3.10.4.4  RTDMA Burst Support
        5. 3.10.4.5  Atomic Memory Operations
        6. 3.10.4.6  RAM ECC
        7. 3.10.4.7  Read-Modify-Write Operations
        8. 3.10.4.8  Dataline Buffer
        9. 3.10.4.9  HSM Sync Bridge
        10. 3.10.4.10 Access Bridges
          1. 3.10.4.10.1 Debug Access Bridge
          2. 3.10.4.10.2 Global Access Bridge
          3. 3.10.4.10.3 Program Access Bridge
      5. 3.10.5 ROM
        1. 3.10.5.1 ROM Dataline Buffer
        2. 3.10.5.2 ROM Prefetch
      6. 3.10.6 Arbitration
      7. 3.10.7 Test Modes
      8. 3.10.8 Emulation Mode
    11. 3.11 System Control Register Configuration Restrictions
    12. 3.12 Software
      1. 3.12.1  SYSCTL Registers to Driverlib Functions
      2. 3.12.2  MEMSS Registers to Driverlib Functions
      3. 3.12.3  CPU Registers to Driverlib Functions
      4. 3.12.4  WD Registers to Driverlib Functions
      5. 3.12.5  CPUTIMER Registers to Driverlib Functions
      6. 3.12.6  XINT Registers to Driverlib Functions
      7. 3.12.7  LPOST Registers to Driverlib Functions
      8. 3.12.8  SYSCTL Examples
        1. 3.12.8.1 Missing clock detection (MCD) - SINGLE_CORE
        2. 3.12.8.2 XCLKOUT (External Clock Output) Configuration - SINGLE_CORE
      9. 3.12.9  TIMER Examples
        1. 3.12.9.1 Timer Academy Lab - SINGLE_CORE
        2. 3.12.9.2 CPU Timers - SINGLE_CORE
        3. 3.12.9.3 CPU Timers - SINGLE_CORE
      10. 3.12.10 WATCHDOG Examples
        1. 3.12.10.1 Watchdog - SINGLE_CORE
      11. 3.12.11 LPM Examples
        1. 3.12.11.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO - SINGLE_CORE
        2. 3.12.11.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog - SINGLE_CORE
        3. 3.12.11.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO - SINGLE_CORE
        4. 3.12.11.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog - SINGLE_CORE
    13. 3.13 SYSCTRL Registers
      1. 3.13.1  SYSCTRL Base Address Table
      2. 3.13.2  DEV_CFG_REGS Registers
      3. 3.13.3  MEMSS_L_CONFIG_REGS Registers
      4. 3.13.4  MEMSS_C_CONFIG_REGS Registers
      5. 3.13.5  MEMSS_M_CONFIG_REGS Registers
      6. 3.13.6  MEMSS_MISCI_REGS Registers
      7. 3.13.7  CPU_SYS_REGS Registers
      8. 3.13.8  CPU_PER_CFG_REGS Registers
      9. 3.13.9  WD_REGS Registers
      10. 3.13.10 CPUTIMER_REGS Registers
      11. 3.13.11 XINT_REGS Registers
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Device Boot Flow
      2. 4.5.2 CPU1 Boot Flow
      3. 4.5.3 Emulation Boot Flow
      4. 4.5.4 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 MPOST and LPOST Configurations
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Memory Maps
        1. 4.7.4.1 Boot ROM Memory-Maps
        2. 4.7.4.2 Reserved RAM Memory-Maps
      5. 4.7.5  ROM Structure and Status Information
      6. 4.7.6  Boot Modes and Loaders
        1. 4.7.6.1 Boot Modes
          1. 4.7.6.1.1 Flash Boot
          2. 4.7.6.1.2 RAM Boot
          3. 4.7.6.1.3 Wait Boot
        2. 4.7.6.2 Bootloaders
          1. 4.7.6.2.1 SPI Boot Mode
          2. 4.7.6.2.2 I2C Boot Mode
          3. 4.7.6.2.3 Parallel Boot Mode
          4. 4.7.6.2.4 CAN Boot Mode
          5. 4.7.6.2.5 CAN-FD Boot Mode
          6. 4.7.6.2.6 UART Boot Mode
      7. 4.7.7  GPIO Assignments
      8. 4.7.8  HSM and C29 ROM Task Ownership and Interactions
        1. 4.7.8.1 Application Authentication by HSM
      9. 4.7.9  Boot Status Information
        1. 4.7.9.1 Booting Status
      10. 4.7.10 BootROM Timing
    8. 4.8 Software
      1. 4.8.1 BOOT Examples
  7. 5 Lockstep Compare Module (LCM)
    1. 5.1 Introduction
      1. 5.1.1 Features
      2. 5.1.2 Block Diagram
      3. 5.1.3 Lockstep Compare Modules
    2. 5.2 Enabling LCM Comparators
    3. 5.3 LCM Redundant Module Configuration
    4. 5.4 LCM Error Handling
    5. 5.5 Debug Mode with LCM
    6. 5.6 Register Parity Error Protection
    7. 5.7 Functional Logic
      1. 5.7.1 Comparator Logic
      2. 5.7.2 Self-Test Logic
        1. 5.7.2.1 Match Test Mode
        2. 5.7.2.2 Mismatch Test Mode
      3. 5.7.3 Error Injection Tests
        1. 5.7.3.1 Comparator Error Force Test
        2. 5.7.3.2 Register Parity Error Test
    8. 5.8 Software
      1. 5.8.1 LCM Registers to Driverlib Functions
    9. 5.9 LCM Registers
      1. 5.9.1 LCM Base Address Table
      2. 5.9.2 LCM_REGS Registers
  8. 6 Peripheral Interrupt Priority and Expansion (PIPE)
    1. 6.1 Introduction
      1. 6.1.1 Features
      2. 6.1.2 Interrupt Concepts
      3. 6.1.3 PIPE Related Collateral
    2. 6.2 Interrupt Architecture
      1. 6.2.1 Dynamic Priority Arbitration Block
      2. 6.2.2 Post Processing Block
      3. 6.2.3 Memory-Mapped Registers
    3. 6.3 Interrupt Propagation
    4. 6.4 Configuring Interrupts
      1. 6.4.1 Enabling and Disabling Interrupts
      2. 6.4.2 Prioritization
        1. 6.4.2.1 User-Configured Interrupt Priority
        2. 6.4.2.2 Index-Based Fixed Interrupt Priority
      3. 6.4.3 Nesting and Priority Grouping
      4. 6.4.4 Stack Protection
      5. 6.4.5 Context
    5. 6.5 Safety and Security
      1. 6.5.1 Access Control
      2. 6.5.2 PIPE Errors
      3. 6.5.3 Register Data Integrity and Safety
      4. 6.5.4 Self-Test and Diagnostics
    6. 6.6 Software
      1. 6.6.1 PIPE Registers to Driverlib Functions
      2. 6.6.2 INTERRUPT Examples
        1. 6.6.2.1 RTINT vs INT Latency example - SINGLE_CORE
        2. 6.6.2.2 INT and RTINT Nesting Example - SINGLE_CORE
    7. 6.7 PIPE Registers
      1. 6.7.1 PIPE Base Address Table
      2. 6.7.2 PIPE_REGS Registers
  9. 7  Error Signaling Module (ESM_C29)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 ESM Related Collateral
    2. 7.2 ESM Subsystem
      1. 7.2.1 System ESM
        1. 7.2.1.1 Error Pin Monitor Event
      2. 7.2.2 Safety Aggregator
        1. 7.2.2.1 EDC Controller Interface Description
          1. 7.2.2.1.1 EDC_REGS Registers
        2. 7.2.2.2 Read Operation on EDC Controller
        3. 7.2.2.3 Write Operation on EDC Controller
        4. 7.2.2.4 Safety Aggregator Error Injection
      3. 7.2.3 ESM Subsystem Integration View
    3. 7.3 ESM Functional Description
      1. 7.3.1 Error Event Inputs
      2. 7.3.2 Error Interrupt Outputs
        1. 7.3.2.1 High Priority Watchdog
        2. 7.3.2.2 Critical Priority Interrupt Output
      3. 7.3.3 Error Pin Output (ERR_O/ERRORSTS)
        1. 7.3.3.1 Minimum Time Interval
        2. 7.3.3.2 PWM Mode
      4. 7.3.4 Reset Type Information for ESM Registers
      5. 7.3.5 Clock Stop
      6. 7.3.6 Commit/Lock for MMRs
      7. 7.3.7 Safety Protection for MMRs
      8. 7.3.8 Register Configuration Tieoffs
        1. 7.3.8.1 Group0 High Priority Tieoff
        2. 7.3.8.2 High Priority Watchdog Enable Tieoff
    4. 7.4 ESM Configuration Guide
    5. 7.5 Interrupt Condition Control and Handling
      1. 7.5.1 ESM Low Priority Error Interrupt
      2. 7.5.2 ESM High Priority Error Interrupt
      3. 7.5.3 Critical Priority Error Interrupt
      4. 7.5.4 High Priority Watchdog Interrupt
      5. 7.5.5 Safety Aggregator Interrupt Control and Handling
    6. 7.6 Software
      1. 7.6.1 ESM_CPU Registers to Driverlib Functions
      2. 7.6.2 ESM_SYS Registers to Driverlib Functions
      3. 7.6.3 ESM_SAFETY_AGGREGATOR Registers to Driverlib Functions
      4. 7.6.4 ESM Examples
        1. 7.6.4.1 ESM Multicore Example (CPU1,CPU3) - MULTI_CORE
        2. 7.6.4.2 ESM Multicore Example (CPU1,CPU3) - MULTI_CORE
        3. 7.6.4.3 ESM - SINGLE_CORE
        4. 7.6.4.4 ESM - SINGLE_CORE
    7. 7.7 ESM Registers
      1. 7.7.1 ESM Base Address Table
      2. 7.7.2 ESM_CPU_REGS Registers
      3. 7.7.3 ESM_SYSTEM_REGS Registers
      4. 7.7.4 ESM_SAFETYAGG_REGS Registers
  10. 8  Error Aggregator
    1. 8.1 Introduction
    2. 8.2 Error Aggregator Modules
    3. 8.3 Error Propagation Path from Source to CPU
    4. 8.4 Error Aggregator Interface
      1. 8.4.1 Functional Description
    5. 8.5 Error Condition Handling User Guide
    6. 8.6 Error Type Information
    7. 8.7 Error Sources Information
    8. 8.8 Software
      1. 8.8.1 ERROR_AGGREGATOR Registers to Driverlib Functions
    9. 8.9 ERRORAGGREGATOR Registers
      1. 8.9.1 ERRORAGGREGATOR Base Address Table
      2. 8.9.2 HSM_ERROR_AGGREGATOR_CONFIG_REGS Registers
      3. 8.9.3 ERROR_AGGREGATOR_CONFIG_REGS Registers
  11. 9 Flash Module
    1. 9.1 Introduction to Flash Memory
      1. 9.1.1 FLASH Related Collateral
      2. 9.1.2 Features
      3. 9.1.3 Flash Tools
      4. 9.1.4 Block Diagram
    2. 9.2 Flash Subsystem Overview
    3. 9.3 Flash Banks and Pumps
    4. 9.4 Flash Read Interfaces
      1. 9.4.1 Bank Modes and Swapping
      2. 9.4.2 Flash Wait States
      3. 9.4.3 Buffer and Cache Mechanisms
        1. 9.4.3.1 Prefetch Mechanism and Block Cache
        2. 9.4.3.2 Data Line Buffer
        3. 9.4.3.3 Sequential Data Pre-read Mode
      4. 9.4.4 Flash Read Arbitration
      5. 9.4.5 Error Correction Code (ECC) Protection
      6. 9.4.6 Procedure to Change Flash Read Interface Registers
    5. 9.5 Flash Erase and Program
      1. 9.5.1 Flash Semaphore and Update Protection
      2. 9.5.2 Erase
      3. 9.5.3 Program
    6. 9.6 Migrating an Application from RAM to Flash
    7. 9.7 Flash Registers
      1. 9.7.1 FLASH Base Address Table
      2. 9.7.2 FLASH_CMD_REGS_FLC1 Registers
      3. 9.7.3 FLASH_CMD_REGS_FLC2 Registers
      4. 9.7.4 FRI_CTRL_REGS Registers
  12. 10Safety and Security Unit (SSU)
    1. 10.1  Introduction
      1. 10.1.1 SSU Related Collateral
      2. 10.1.2 Block Diagram
      3. 10.1.3 System SSU Configuration Example
    2. 10.2  Access Protection Ranges
      1. 10.2.1 Access Protection Inheritance
    3. 10.3  LINKs
    4. 10.4  STACKs
    5. 10.5  ZONEs
    6. 10.6  SSU-CPU Interface
      1. 10.6.1 SSU Operation in Lockstep Mode
    7. 10.7  SSU Operation Modes
    8. 10.8  Security Configuration and Flash Management
      1. 10.8.1 BANKMGMT Sectors
      2. 10.8.2 SECCFG Sectors
      3. 10.8.3 SECCFG Sector Address Mapping
      4. 10.8.4 SECCFG Sector Memory Map
      5. 10.8.5 SECCFG CRC
    9. 10.9  Flash Write/Erase Access Control
      1. 10.9.1 Permanent Flash Lock (Write/Erase Protection)
      2. 10.9.2 Updating Flash MAIN Sectors
      3. 10.9.3 Firmware-Over-The-Air Updates (FOTA)
      4. 10.9.4 Updating Flash SECCFG Sectors
      5. 10.9.5 Reading Flash SECCFG Sectors
    10. 10.10 RAMOPEN Feature
    11. 10.11 Debug Authorization
      1. 10.11.1 Global CPU Debug Enable
      2. 10.11.2 ZONE Debug
      3. 10.11.3 Authentication for Debug Access
        1. 10.11.3.1 Password-based Authentication
        2. 10.11.3.2 CPU-based Authentication
    12. 10.12 Hardcoded Protections
    13. 10.13 SSU Register Access Permissions
      1. 10.13.1 Permissions for SSU General Control Registers
      2. 10.13.2 Permissions for SSU CPU1 Configuration Registers
      3. 10.13.3 Permissions for SSU CPU2+ Configuration Registers
      4. 10.13.4 Permissions for CPU1 Access Protection Registers
      5. 10.13.5 Permissions for CPU2+ Access Protection Registers
    14. 10.14 SSU Fault Signals
    15. 10.15 Software
      1. 10.15.1 SSU Registers to Driverlib Functions
    16. 10.16 SSU Registers
      1. 10.16.1 SSU Base Address Table
      2. 10.16.2 SSU_GEN_REGS Registers
      3. 10.16.3 SSU_CPU1_CFG_REGS Registers
      4. 10.16.4 SSU_CPU2_CFG_REGS Registers
      5. 10.16.5 SSU_CPU3_CFG_REGS Registers
      6. 10.16.6 SSU_CPU1_AP_REGS Registers
      7. 10.16.7 SSU_CPU2_AP_REGS Registers
      8. 10.16.8 SSU_CPU3_AP_REGS Registers
  13. 11Configurable Logic Block (CLB)
    1. 11.1  Introduction
      1. 11.1.1 CLB Related Collateral
    2. 11.2  Description
      1. 11.2.1 CLB Clock
    3. 11.3  CLB Input/Output Connection
      1. 11.3.1 Overview
      2. 11.3.2 CLB Input Selection
      3. 11.3.3 CLB Output Selection
      4. 11.3.4 CLB Output Signal Multiplexer
    4. 11.4  CLB Tile
      1. 11.4.1 Static Switch Block
      2. 11.4.2 Counter Block
        1. 11.4.2.1 Counter Description
        2. 11.4.2.2 Counter Operation
        3. 11.4.2.3 Serializer Mode
        4. 11.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 11.4.3 FSM Block
      4. 11.4.4 LUT4 Block
      5. 11.4.5 Output LUT Block
      6. 11.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 11.4.7 High Level Controller (HLC)
        1. 11.4.7.1 High Level Controller Events
        2. 11.4.7.2 High Level Controller Instructions
        3. 11.4.7.3 <Src> and <Dest>
        4. 11.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 11.5  CPU Interface
      1. 11.5.1 Register Description
      2. 11.5.2 Non-Memory Mapped Registers
    6. 11.6  RTDMA Access
    7. 11.7  CLB Data Export Through SPI RX Buffer
    8. 11.8  CLB Pipeline Mode
    9. 11.9  Software
      1. 11.9.1 CLB Registers to Driverlib Functions
      2. 11.9.2 CLB Examples
    10. 11.10 CLB Registers
      1. 11.10.1 CLB Base Address Table
      2. 11.10.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 11.10.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 11.10.4 CLB_DATA_EXCHANGE_REGS Registers
  14. 12Dual-Clock Comparator (DCC)
    1. 12.1 Introduction
      1. 12.1.1 Features
      2. 12.1.2 Block Diagram
    2. 12.2 Module Operation
      1. 12.2.1 Configuring DCC Counters
      2. 12.2.2 Single-Shot Measurement Mode
      3. 12.2.3 Continuous Monitoring Mode
      4. 12.2.4 Error Conditions
    3. 12.3 Interrupts
    4. 12.4 Software
      1. 12.4.1 DCC Registers to Driverlib Functions
      2. 12.4.2 DCC Examples
        1. 12.4.2.1 DCC Single shot Clock verification - SINGLE_CORE
        2. 12.4.2.2 DCC Single shot Clock measurement - SINGLE_CORE
        3. 12.4.2.3 DCC Continuous clock monitoring - SINGLE_CORE
    5. 12.5 DCC Registers
      1. 12.5.1 DCC Base Address Table
      2. 12.5.2 DCC_REGS Registers
  15. 13Real-Time Direct Memory Access (RTDMA)
    1. 13.1  Introduction
      1. 13.1.1 Features
      2. 13.1.2 RTDMA Related Collateral
      3. 13.1.3 Block Diagram
    2. 13.2  RTDMA Trigger Source Options
    3. 13.3  RTDMA Bus
    4. 13.4  Address Pointer and Transfer Control
    5. 13.5  Pipeline Timing and Throughput
    6. 13.6  Channel Priority
      1. 13.6.1 Round-Robin Mode
      2. 13.6.2 Software Configurable Priority of Channels
    7. 13.7  Overrun Detection Feature
    8. 13.8  Burst Mode
    9. 13.9  Safety and Security
      1. 13.9.1 Safety
        1. 13.9.1.1 Lockstep Mode
        2. 13.9.1.2 Memory Protection Unit (MPU)
          1. 13.9.1.2.1 MPU Errors
      2. 13.9.2 Security
      3. 13.9.3 RTDMA Errors
      4. 13.9.4 Self-Test and Diagnostics
    10. 13.10 Software
      1. 13.10.1 RTDMA Registers to Driverlib Functions
      2. 13.10.2 RTDMA Examples
        1. 13.10.2.1 RTDMA Academy Lab - SINGLE_CORE
        2. 13.10.2.2 RTDMA Transfer - SINGLE_CORE
        3. 13.10.2.3 RTDMA Transfer with MPU - SINGLE_CORE
    11. 13.11 RTDMA Registers
      1. 13.11.1 RTDMA Base Address Table
      2. 13.11.2 RTDMA_REGS Registers
      3. 13.11.3 RTDMA_DIAG_REGS Registers
      4. 13.11.4 RTDMA_SELFTEST_REGS Registers
      5. 13.11.5 RTDMA_MPU_REGS Registers
      6. 13.11.6 RTDMA_CH_REGS Registers
  16. 14External Memory Interface (EMIF)
    1. 14.1 Introduction
      1. 14.1.1 Purpose of the Peripheral
      2. 14.1.2 Features
        1. 14.1.2.1 Asynchronous Memory Support
        2. 14.1.2.2 Synchronous DRAM Memory Support
      3. 14.1.3 Functional Block Diagram
      4. 14.1.4 Configuring Device Pins
    2. 14.2 EMIF Module Architecture
      1. 14.2.1  EMIF Clock Control
      2. 14.2.2  EMIF Requests
      3. 14.2.3  EMIF Signal Descriptions
      4. 14.2.4  EMIF Signal Multiplexing Control
      5. 14.2.5  SDRAM Controller and Interface
        1. 14.2.5.1  SDRAM Commands
        2. 14.2.5.2  Interfacing to SDRAM
        3. 14.2.5.3  SDRAM Configuration Registers
        4. 14.2.5.4  SDRAM Auto-Initialization Sequence
        5. 14.2.5.5  SDRAM Configuration Procedure
        6. 14.2.5.6  EMIF Refresh Controller
          1. 14.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 14.2.5.7  Self-Refresh Mode
        8. 14.2.5.8  Power-Down Mode
        9. 14.2.5.9  SDRAM Read Operation
        10. 14.2.5.10 SDRAM Write Operations
        11. 14.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 14.2.6  Asynchronous Controller and Interface
        1. 14.2.6.1 Interfacing to Asynchronous Memory
        2. 14.2.6.2 Accessing Larger Asynchronous Memories
        3. 14.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 14.2.6.4 Read and Write Operations in Normal Mode
          1. 14.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 14.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 14.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 14.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 14.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 14.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 14.2.7  Data Bus Parking
      8. 14.2.8  Reset and Initialization Considerations
      9. 14.2.9  Interrupt Support
        1. 14.2.9.1 Interrupt Events
      10. 14.2.10 RTDMA Event Support
      11. 14.2.11 EMIF Signal Multiplexing
      12. 14.2.12 Memory Map
      13. 14.2.13 Priority and Arbitration
      14. 14.2.14 System Considerations
        1. 14.2.14.1 Asynchronous Request Times
      15. 14.2.15 Power Management
        1. 14.2.15.1 Power Management Using Self-Refresh Mode
        2. 14.2.15.2 Power Management Using Power Down Mode
      16. 14.2.16 Emulation Considerations
    3. 14.3 EMIF Subsystem (EMIFSS)
      1. 14.3.1 Burst Support
      2. 14.3.2 EMIFSS Performance Improvement
      3. 14.3.3 Buffer Module
        1. 14.3.3.1 CPU Write FIFO
      4. 14.3.4 Emulation Mode
    4. 14.4 Example Configuration
      1. 14.4.1 Hardware Interface
      2. 14.4.2 Software Configuration
        1. 14.4.2.1 Configuring the SDRAM Interface
          1. 14.4.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 14.4.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 14.4.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 14.4.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 14.4.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 14.4.2.2 Configuring the Flash Interface
          1. 14.4.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    5. 14.5 Software
      1. 14.5.1 EMIF Registers to Driverlib Functions
      2. 14.5.2 EMIF Examples
    6. 14.6 EMIF Registers
      1. 14.6.1 EMIF Base Address Table
      2. 14.6.2 EMIF_REGS Registers
  17. 15General-Purpose Input/Output (GPIO)
    1. 15.1  Introduction
      1. 15.1.1 GPIO Related Collateral
    2. 15.2  Configuration Overview
    3. 15.3  Digital Inputs on ADC Pins (AIOs)
    4. 15.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 15.5  Digital General-Purpose I/O Control
    6. 15.6  Input Qualification
      1. 15.6.1 No Synchronization (Asynchronous Input)
      2. 15.6.2 Synchronization to SYSCLKOUT Only
      3. 15.6.3 Qualification Using a Sampling Window
    7. 15.7  PMBUS and I2C Signals
    8. 15.8  GPIO and Peripheral Muxing
      1. 15.8.1 GPIO Muxing
      2. 15.8.2 Peripheral Muxing
    9. 15.9  Internal Pullup Configuration Requirements
    10. 15.10 Software
      1. 15.10.1 GPIO Registers to Driverlib Functions
      2. 15.10.2 GPIO Examples
        1. 15.10.2.1 Device GPIO Toggle - SINGLE_CORE
        2. 15.10.2.2 XINT/XBAR example - SINGLE_CORE
      3. 15.10.3 LED Examples
        1. 15.10.3.1 LED Blinky Example - MULTI_CORE
        2. 15.10.3.2 LED Blinky Example (CPU1,CPU3) - MULTI_CORE
        3. 15.10.3.3 LED Blinky example - SINGLE_CORE
        4. 15.10.3.4 LED Blinky Example (CPU1|CPU2|CPU3) - MULTI_CORE
        5. 15.10.3.5 LED Blinky Example (CPU2) - MULTI_CORE
        6. 15.10.3.6 LED Blinky Example (CPU3) - MULTI_CORE
    11. 15.11 GPIO Registers
      1. 15.11.1 GPIO Base Address Table
      2. 15.11.2 GPIO_CTRL_REGS Registers
      3. 15.11.3 GPIO_DATA_REGS Registers
      4. 15.11.4 GPIO_DATA_READ_REGS Registers
  18. 16Interprocessor Communication (IPC)
    1. 16.1 Introduction
    2. 16.2 IPC Flags and Interrupts
    3. 16.3 IPC Command Registers
    4. 16.4 Free-Running Counter
    5. 16.5 IPC Communication Protocol
    6. 16.6 Software
      1. 16.6.1 IPC Registers to Driverlib Functions
      2. 16.6.2 IPC Examples
        1. 16.6.2.1 IPC basic message passing example with interrupt - MULTI_CORE
        2. 16.6.2.2 IPC basic message passing example with interrupt - MULTI_CORE
        3. 16.6.2.3 IPC basic message passing example with interrupt - MULTI_CORE
        4. 16.6.2.4 IPC basic message passing example with interrupt - MULTI_CORE
    7. 16.7 IPC Registers
      1. 16.7.1 IPC Base Address Table
      2. 16.7.2 IPC_COUNTER_REGS Registers
      3. 16.7.3 CPU1_IPC_SEND_REGS Registers
      4. 16.7.4 CPU2_IPC_SEND_REGS Registers
      5. 16.7.5 CPU3_IPC_SEND_REGS Registers
      6. 16.7.6 CPU1_IPC_RCV_REGS Registers
      7. 16.7.7 CPU2_IPC_RCV_REGS Registers
      8. 16.7.8 CPU3_IPC_RCV_REGS Registers
  19. 17Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 17.1 Introduction
    2. 17.2 Enhanced Bus Comparator Unit
      1. 17.2.1 Enhanced Bus Comparator Unit Operations
      2. 17.2.2 Stack Qualification
      3. 17.2.3 Event Masking and Exporting
    3. 17.3 System Event Counter Unit
      1. 17.3.1 System Event Counter Modes
        1. 17.3.1.1 Counting Active Levels Versus Edges
        2. 17.3.1.2 Max and Min Mode
        3. 17.3.1.3 Cumulative Mode
        4. 17.3.1.4 Input Signal Selection
      2. 17.3.2 Reset on Event
      3. 17.3.3 Operation Conditions
    4. 17.4 Program Counter Trace
      1. 17.4.1 Functional Block Diagram
      2. 17.4.2 Trace Qualification Modes
        1. 17.4.2.1 Trace Input Signal Conditioning
      3. 17.4.3 Trace Memory
      4. 17.4.4 PC Trace Software Operation
      5. 17.4.5 Trace Operation in Debug Mode
    5. 17.5 ERAD Ownership, Initialization, and Reset
      1. 17.5.1 Feature Level Ownership
      2. 17.5.2 Feature Access Security Mechanism
      3. 17.5.3 PC Trace Access Security Mechanism
    6. 17.6 ERAD Programming Sequence
      1. 17.6.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 17.6.2 Timer and Counter Programming Sequence
    7. 17.7 Software
      1. 17.7.1 ERAD Registers to Driverlib Functions
    8. 17.8 ERAD Registers
      1. 17.8.1 ERAD Base Address Table
        1. 17.8.1.1 ERAD_REGS Registers
  20. 18Data Logger and Trace (DLT)
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 DLT Related Collateral
      3. 18.1.3 Interfaces
        1. 18.1.3.1 Block Diagram
    2. 18.2 Functional Overview
      1. 18.2.1 DLT Configuration
        1. 18.2.1.1 LINK Filter
        2. 18.2.1.2 TAG Filter
        3. 18.2.1.3 ERAD Event Trigger
        4. 18.2.1.4 Concurrent FILTERING modes
      2. 18.2.2 Time-stamping
      3. 18.2.3 FIFO Construction
        1. 18.2.3.1 FIFO Interrupt
    3. 18.3 Software
      1. 18.3.1 DLT Registers to Driverlib Functions
      2. 18.3.2 DLT Examples
        1. 18.3.2.1 DLT TAG filter example - SINGLE_CORE
        2. 18.3.2.2 DLT TAG filter example - SINGLE_CORE
        3. 18.3.2.3 DLT ERAD filter example - SINGLE_CORE
    4. 18.4 DLT Registers
      1. 18.4.1 DLT Base Address Table
      2. 18.4.2 DLT_CORE_REGS Registers
      3. 18.4.3 DLT_FIFO_REGS Registers
  21. 19Waveform Analyzer Diagnostic (WADI)
    1. 19.1 WADI Overview
      1. 19.1.1 Features
      2. 19.1.2 WADI Related Collateral
      3. 19.1.3 Block Diagram
      4. 19.1.4 Description
    2. 19.2 Signal and Trigger Input Configuration
      1. 19.2.1 SIG1 and SIG2 Configuration
      2. 19.2.2 Trigger 1 and Trigger 2
    3. 19.3 WADI Block
      1. 19.3.1 Overview
      2. 19.3.2 Counters
      3. 19.3.3 Pulse Width
        1. 19.3.3.1 Pulse Width Single Measurement
        2. 19.3.3.2 Pulse Width Aggregation
        3. 19.3.3.3 Pulse Width Average and Peak
      4. 19.3.4 Edge Count
        1. 19.3.4.1 Edge Count with Fixed Window
        2. 19.3.4.2 Edge Count with Moving Window
      5. 19.3.5 Signal1 to Signal2 Comparison
      6. 19.3.6 Dead Band and Phase
      7. 19.3.7 Simultaneous Measurement
    4. 19.4 Safe State Sequencer (SSS)
      1. 19.4.1 SSS Configuration
    5. 19.5 Lock and Commit Registers
    6. 19.6 Interrupt and Error Handling
    7. 19.7 RTDMA Interfaces
      1. 19.7.1 RTDMA Trigger
    8. 19.8 Software
      1. 19.8.1 WADI Registers to Driverlib Functions
      2. 19.8.2 WADI Examples
        1. 19.8.2.1 WADI Duty and Frequency check - SINGLE_CORE
    9. 19.9 WADI Registers
      1. 19.9.1 WADI Base Address Table
      2. 19.9.2 WADI_CONFIG_REGS Registers
      3. 19.9.3 WADI_OPER_SSS_REGS Registers
  22. 20Crossbar (X-BAR)
    1. 20.1 X-BAR Related Collateral
    2. 20.2 Input X-BAR, ICL XBAR, MINDB XBAR,
      1. 20.2.1 ICL and MINDB X-BAR
    3. 20.3 ePWM , CLB, and GPIO Output X-BAR
      1. 20.3.1 ePWM X-BAR
        1. 20.3.1.1 ePWM X-BAR Architecture
      2. 20.3.2 CLB X-BAR
        1. 20.3.2.1 CLB X-BAR Architecture
      3. 20.3.3 GPIO Output X-BAR
        1. 20.3.3.1 GPIO Output X-BAR Architecture
      4. 20.3.4 X-BAR Flags
    4. 20.4 Software
      1. 20.4.1 INPUT_XBAR Registers to Driverlib Functions
      2. 20.4.2 EPWM_XBAR Registers to Driverlib Functions
      3. 20.4.3 CLB_XBAR Registers to Driverlib Functions
      4. 20.4.4 OUTPUT_XBAR Registers to Driverlib Functions
      5. 20.4.5 MDL_XBAR Registers to Driverlib Functions
      6. 20.4.6 ICL_XBAR Registers to Driverlib Functions
      7. 20.4.7 XBAR Registers to Driverlib Functions
      8. 20.4.8 XBAR Examples
        1. 20.4.8.1 Input XBAR to Output XBAR Connection - SINGLE_CORE
        2. 20.4.8.2 Output XBAR Pulse Stretch - SINGLE_CORE
    5. 20.5 XBAR Registers
      1. 20.5.1 XBAR Base Address Table
      2. 20.5.2 INPUT_XBAR_REGS Registers
      3. 20.5.3 EPWM_XBAR_REGS Registers
      4. 20.5.4 CLB_XBAR_REGS Registers
      5. 20.5.5 OUTPUTXBAR_REGS Registers
      6. 20.5.6 MDL_XBAR_REGS Registers
      7. 20.5.7 ICL_XBAR_REGS Registers
      8. 20.5.8 OUTPUTXBAR_FLAG_REGS Registers
      9. 20.5.9 XBAR_REGS Registers
  23. 21Embedded Pattern Generator (EPG)
    1. 21.1 Introduction
      1. 21.1.1 Features
      2. 21.1.2 EPG Block Diagram
      3. 21.1.3 EPG Related Collateral
    2. 21.2 Clock Generator Modules
      1. 21.2.1 DCLK (50% duty cycle clock)
      2. 21.2.2 Clock Stop
    3. 21.3 Signal Generator Module
    4. 21.4 EPG Peripheral Signal Mux Selection
    5. 21.5 Application Software Notes
    6. 21.6 EPG Example Use Cases
      1. 21.6.1 EPG Example: Synchronous Clocks with Offset
        1. 21.6.1.1 Synchronous Clocks with Offset Register Configuration
      2. 21.6.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 21.6.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 21.6.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 21.6.3.1 Serial Data Bit Stream (MSB first) Register Configuration
      4. 21.6.4 EPG Example: Clock and Data Pair
        1. 21.6.4.1 Clock and Data Pair Register Configuration
      5. 21.6.5 EPG Example: Clock and Skewed Data Pair
        1. 21.6.5.1 Clock and Skewed Data Pair Register Configuration
      6. 21.6.6 EPG Example: Capturing Serial Data with a Known Baud Rate
        1. 21.6.6.1 Capturing Serial Data with a Known Baud Rate Register Configuration
    7. 21.7 EPG Interrupt
    8. 21.8 Software
      1. 21.8.1 EPG Registers to Driverlib Functions
      2. 21.8.2 EPG Examples
        1. 21.8.2.1 EPG Generating Synchronous Clocks - SINGLE_CORE
        2. 21.8.2.2 EPG Generating Two Offset Clocks - SINGLE_CORE
        3. 21.8.2.3 EPG Generating Two Offset Clocks With SIGGEN - SINGLE_CORE
        4. 21.8.2.4 EPG Generate Serial Data - SINGLE_CORE
        5. 21.8.2.5 EPG Generate Serial Data Shift Mode - SINGLE_CORE
    9. 21.9 EPG Registers
      1. 21.9.1 EPG Base Address Table
      2. 21.9.2 EPG_REGS Registers
      3. 21.9.3 EPG_MUX_REGS Registers
  24. 22â–º ANALOG PERIPHERALS
    1.     Technical Reference Manual Overview
  25. 23Analog Subsystem
    1. 23.1 Introduction
      1. 23.1.1 Features
      2. 23.1.2 Block Diagram
    2. 23.2 Optimizing Power-Up Time
    3. 23.3 Digital Inputs on ADC Pins (AIOs)
    4. 23.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 23.5 Analog Pins and Internal Connections
    6. 23.6 Software
      1. 23.6.1 ASYSCTL Registers to Driverlib Functions
    7. 23.7 Lock Registers
    8. 23.8 ASBSYS Registers
      1. 23.8.1 ASBSYS Base Address Table
      2. 23.8.2 ANALOG_SUBSYS_REGS Registers
  26. 24Analog-to-Digital Converter (ADC)
    1. 24.1  Introduction
      1. 24.1.1 ADC Related Collateral
      2. 24.1.2 Features
      3. 24.1.3 Block Diagram
    2. 24.2  ADC Configurability
      1. 24.2.1 Clock Configuration
      2. 24.2.2 Resolution
      3. 24.2.3 Voltage Reference
        1. 24.2.3.1 External Reference Mode
        2. 24.2.3.2 Internal Reference Mode
        3. 24.2.3.3 Ganged References
        4. 24.2.3.4 Selecting Reference Mode
      4. 24.2.4 Signal Mode
      5. 24.2.5 Expected Conversion Results
      6. 24.2.6 Interpreting Conversion Results
    3. 24.3  SOC Principle of Operation
      1. 24.3.1 SOC Configuration
      2. 24.3.2 Trigger Operation
        1. 24.3.2.1 Global Software Trigger
        2. 24.3.2.2 Trigger Repeaters
          1. 24.3.2.2.1 Oversampling Mode
          2. 24.3.2.2.2 Undersampling Mode
          3. 24.3.2.2.3 Trigger Phase Delay
          4. 24.3.2.2.4 Re-trigger Spread
          5. 24.3.2.2.5 Trigger Repeater Configuration
            1. 24.3.2.2.5.1 Register Shadow Updates
          6. 24.3.2.2.6 Re-Trigger Logic
          7. 24.3.2.2.7 Multi-Path Triggering Behavior
      3. 24.3.3 ADC Acquisition (Sample and Hold) Window
      4. 24.3.4 ADC Input Models
      5. 24.3.5 Channel Selection
        1. 24.3.5.1 External Channel Selection
          1. 24.3.5.1.1 External Channel Selection Timing
    4. 24.4  SOC Configuration Examples
      1. 24.4.1 Single Conversion from ePWM Trigger
      2. 24.4.2 Oversampled Conversion from ePWM Trigger
      3. 24.4.3 Multiple Conversions from CPU Timer Trigger
      4. 24.4.4 Software Triggering of SOCs
    5. 24.5  ADC Conversion Priority
    6. 24.6  Burst Mode
      1. 24.6.1 Burst Mode Example
      2. 24.6.2 Burst Mode Priority Example
    7. 24.7  EOC and Interrupt Operation
      1. 24.7.1 Interrupt Overflow
      2. 24.7.2 Continue to Interrupt Mode
      3. 24.7.3 Early Interrupt Configuration Mode
    8. 24.8  Post-Processing Blocks
      1. 24.8.1 PPB Offset Correction
      2. 24.8.2 PPB Error Calculation
      3. 24.8.3 PPB Result Delta Calculation
      4. 24.8.4 PPB Limit Detection and Zero-Crossing Detection
        1. 24.8.4.1 PPB Digital Trip Filter
      5. 24.8.5 PPB Sample Delay Capture
      6. 24.8.6 PPB Oversampling
        1. 24.8.6.1 Accumulation, Minimum, Maximum, and Average Functions
        2. 24.8.6.2 Outlier Rejection
    9. 24.9  Result Safety Checker
      1. 24.9.1 Result Safety Checker Operation
      2. 24.9.2 Result Safety Checker Interrupts and Events
    10. 24.10 Opens/Shorts Detection Circuit (OSDETECT)
      1. 24.10.1 Implementation
      2. 24.10.2 Detecting an Open Input Pin
      3. 24.10.3 Detecting a Shorted Input Pin
    11. 24.11 Power-Up Sequence
    12. 24.12 ADC Calibration
      1. 24.12.1 ADC Zero Offset Calibration
    13. 24.13 ADC Timings
      1. 24.13.1 ADC Timing Diagrams
      2. 24.13.2 Post-Processing Block Timings
    14. 24.14 Additional Information
      1. 24.14.1 Ensuring Synchronous Operation
        1. 24.14.1.1 Basic Synchronous Operation
        2. 24.14.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 24.14.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 24.14.1.4 Synchronous Operation with Different Resolutions
        5. 24.14.1.5 Non-overlapping Conversions
      2. 24.14.2 Choosing an Acquisition Window Duration
      3. 24.14.3 Achieving Simultaneous Sampling
      4. 24.14.4 Result Register Mapping
      5. 24.14.5 Internal Temperature Sensor
      6. 24.14.6 Designing an External Reference Circuit
      7. 24.14.7 Internal Test Mode
      8. 24.14.8 ADC Gain and Offset Calibration
    15. 24.15 Software
      1. 24.15.1 ADC Registers to Driverlib Functions
      2. 24.15.2 ADC Examples
        1. 24.15.2.1  ADC Software Triggering - SINGLE_CORE
        2. 24.15.2.2  ADC ePWM Triggering - SINGLE_CORE
        3. 24.15.2.3  ADC Temperature Sensor Conversion - SINGLE_CORE
        4. 24.15.2.4  ADC Synchronous SOC Software Force (adc_soc_software_sync) - SINGLE_CORE
        5. 24.15.2.5  ADC Continuous Triggering (adc_soc_continuous) - SINGLE_CORE
        6. 24.15.2.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma) - SINGLE_CORE
        7. 24.15.2.7  ADC PPB Offset (adc_ppb_offset) - SINGLE_CORE
        8. 24.15.2.8  ADC PPB Limits (adc_ppb_limits) - SINGLE_CORE
        9. 24.15.2.9  ADC PPB Delay Capture (adc_ppb_delay) - SINGLE_CORE
        10. 24.15.2.10 ADC ePWM Triggering Multiple SOC - SINGLE_CORE
        11. 24.15.2.11 ADC Burst Mode - SINGLE_CORE
        12. 24.15.2.12 ADC Burst Mode Oversampling - SINGLE_CORE
        13. 24.15.2.13 ADC SOC Oversampling - SINGLE_CORE
        14. 24.15.2.14 ADC PPB PWM trip (adc_ppb_pwm_trip) - SINGLE_CORE
        15. 24.15.2.15 ADC Trigger Repeater Oversampling - SINGLE_CORE
        16. 24.15.2.16 ADC Trigger Repeater Undersampling - SINGLE_CORE
        17. 24.15.2.17 ADC Safety Checker - SINGLE_CORE
    16. 24.16 ADC Registers
      1. 24.16.1 ADC Base Address Table
      2. 24.16.2 ADC_RESULT_REGS Registers
      3. 24.16.3 ADC_REGS Registers
      4. 24.16.4 ADC_SAFECHECK_REGS Registers
      5. 24.16.5 ADC_SAFECHECK_INTEVT_REGS Registers
      6. 24.16.6 ADC_GLOBAL_REGS Registers
  27. 25Buffered Digital-to-Analog Converter (DAC)
    1. 25.1 Introduction
      1. 25.1.1 DAC Related Collateral
      2. 25.1.2 Features
      3. 25.1.3 Block Diagram
    2. 25.2 Using the DAC
      1. 25.2.1 Initialization Sequence
      2. 25.2.2 DAC Offset Adjustment
      3. 25.2.3 EPWMSYNCPER Signal
    3. 25.3 Lock Registers
    4. 25.4 Software
      1. 25.4.1 DAC Registers to Driverlib Functions
      2. 25.4.2 DAC Examples
        1. 25.4.2.1 Buffered DAC Enable - SINGLE_CORE
        2. 25.4.2.2 Buffered DAC Random - SINGLE_CORE
    5. 25.5 DAC Registers
      1. 25.5.1 DAC Base Address Table
      2. 25.5.2 DAC_REGS Registers
  28. 26Comparator Subsystem (CMPSS)
    1. 26.1 Introduction
      1. 26.1.1 CMPSS Related Collateral
      2. 26.1.2 Features
      3. 26.1.3 Block Diagram
    2. 26.2 Comparator
    3. 26.3 Reference DAC
    4. 26.4 Ramp Generator
      1. 26.4.1 Ramp Generator Overview
      2. 26.4.2 Ramp Generator Behavior
      3. 26.4.3 Ramp Generator Behavior at Corner Cases
    5. 26.5 Digital Filter
      1. 26.5.1 Filter Initialization Sequence
    6. 26.6 Using the CMPSS
      1. 26.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 26.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 26.6.3 Calibrating the CMPSS
      4. 26.6.4 Enabling and Disabling the CMPSS Clock
    7. 26.7 Software
      1. 26.7.1 CMPSS Registers to Driverlib Functions
      2. 26.7.2 CMPSS Examples
        1. 26.7.2.1 CMPSS Asynchronous Trip - SINGLE_CORE
        2. 26.7.2.2 CMPSS Digital Filter Configuration - SINGLE_CORE
    8. 26.8 CMPSS Registers
      1. 26.8.1 CMPSS Base Address Table
      2. 26.8.2 CMPSS_REGS Registers
  29. 27â–º CONTROL PERIPHERALS
    1.     Technical Reference Manual Overview
  30. 28Enhanced Capture (eCAP)
    1. 28.1 Introduction
      1. 28.1.1 Features
      2. 28.1.2 ECAP Related Collateral
    2. 28.2 Description
    3. 28.3 Configuring Device Pins for the eCAP
    4. 28.4 Capture and APWM Operating Mode
    5. 28.5 Capture Mode Description
      1. 28.5.1  Event Prescaler
      2. 28.5.2  Glitch Filter
      3. 28.5.3  Edge Polarity Select and Qualifier
      4. 28.5.4  Continuous/One-Shot Control
      5. 28.5.5  32-Bit Counter and Phase Control
      6. 28.5.6  CAP1-CAP4 Registers
      7. 28.5.7  eCAP Synchronization
        1. 28.5.7.1 Example 1 - Using SWSYNC with ECAP Module
      8. 28.5.8  Interrupt Control
      9. 28.5.9  RTDMA Interrupt
      10. 28.5.10 ADC SOC Event
      11. 28.5.11 Shadow Load and Lockout Control
      12. 28.5.12 APWM Mode Operation
      13. 28.5.13 Signal Monitoring Unit
        1. 28.5.13.1 Pulse Width and Period Monitoring
        2. 28.5.13.2 Edge Monitoring
    6. 28.6 Application of the eCAP Module
      1. 28.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 28.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 28.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 28.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 28.7 Application of the APWM Mode
      1. 28.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 28.8 Software
      1. 28.8.1 ECAP Registers to Driverlib Functions
      2. 28.8.2 ECAP Examples
        1. 28.8.2.1 eCAP APWM Example - SINGLE_CORE
        2. 28.8.2.2 eCAP Capture PWM Example - SINGLE_CORE
        3. 28.8.2.3 eCAP APWM Phase-shift Example - SINGLE_CORE
    9. 28.9 ECAP Registers
      1. 28.9.1 ECAP Base Address Table
      2. 28.9.2 ECAP_REGS Registers
      3. 28.9.3 ECAP_SIGNAL_MONITORING Registers
      4. 28.9.4 HRCAP_REGS Registers
  31. 29High Resolution Capture (HRCAP)
    1. 29.1 Introduction
      1. 29.1.1 HRCAP Related Collateral
      2. 29.1.2 Features
      3. 29.1.3 Description
    2. 29.2 Operational Details
      1. 29.2.1 HRCAP Clocking
      2. 29.2.2 HRCAP Initialization Sequence
      3. 29.2.3 HRCAP Interrupts
      4. 29.2.4 HRCAP Calibration
        1. 29.2.4.1 Applying the Scale Factor
    3. 29.3 Known Exceptions
    4. 29.4 Software
      1. 29.4.1 HRCAP Examples
        1. 29.4.1.1 HRCAP Capture and Calibration Example - SINGLE_CORE
    5. 29.5 HRCAP Registers
      1. 29.5.1 HRCAP Base Address Table
      2. 29.5.2 HRCAP_REGS Registers
  32. 30Enhanced Pulse Width Modulator (ePWM)
    1. 30.1  Introduction
      1. 30.1.1 EPWM Related Collateral
      2. 30.1.2 Submodule Overview
    2. 30.2  Configuring Device Pins
    3. 30.3  ePWM Modules Overview
    4. 30.4  Time-Base (TB) Submodule
      1. 30.4.1 Purpose of the Time-Base Submodule
      2. 30.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 30.4.3 Calculating PWM Period and Frequency
        1. 30.4.3.1 Time-Base Period Shadow Register
        2. 30.4.3.2 Time-Base Clock Synchronization
        3. 30.4.3.3 Time-Base Counter Synchronization
        4. 30.4.3.4 ePWM SYNC Selection
      4. 30.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 30.4.5 Simultaneous Writes Between ePWM Register Instances
      6. 30.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 30.4.7 Global Load
        1. 30.4.7.1 Global Load Pulse Pre-Scalar
        2. 30.4.7.2 One-Shot Load Mode
        3. 30.4.7.3 One-Shot Sync Mode
    5. 30.5  Counter-Compare (CC) Submodule
      1. 30.5.1 Purpose of the Counter-Compare Submodule
      2. 30.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 30.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 30.5.4 Count Mode Timing Waveforms
    6. 30.6  Action-Qualifier (AQ) Submodule
      1. 30.6.1 Purpose of the Action-Qualifier Submodule
      2. 30.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 30.6.3 Action-Qualifier Event Priority
      4. 30.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 30.6.5 Configuration Requirements for Common Waveforms
    7. 30.7  XCMP Complex Waveform Generator Mode
      1. 30.7.1 XCMP Allocation to CMPA and CMPB
      2. 30.7.2 XCMP Shadow Buffers
      3. 30.7.3 XCMP Operation
    8. 30.8  Dead-Band Generator (DB) Submodule
      1. 30.8.1 Purpose of the Dead-Band Submodule
      2. 30.8.2 Dead-band Submodule Additional Operating Modes
      3. 30.8.3 Operational Highlights for the Dead-Band Submodule
    9. 30.9  PWM Chopper (PC) Submodule
      1. 30.9.1 Purpose of the PWM Chopper Submodule
      2. 30.9.2 Operational Highlights for the PWM Chopper Submodule
      3. 30.9.3 Waveforms
        1. 30.9.3.1 One-Shot Pulse
        2. 30.9.3.2 Duty Cycle Control
    10. 30.10 Trip-Zone (TZ) Submodule
      1. 30.10.1 Purpose of the Trip-Zone Submodule
      2. 30.10.2 Operational Highlights for the Trip-Zone Submodule
        1. 30.10.2.1 Trip-Zone Configurations
      3. 30.10.3 Generating Trip Event Interrupts
    11. 30.11 Diode Emulation (DE) Submodule
      1. 30.11.1 DEACTIVE Mode
      2. 30.11.2 Exiting DE Mode
      3. 30.11.3 Re-Entering DE Mode
      4. 30.11.4 DE Monitor
    12. 30.12 Minimum Dead-Band (MINDB) + Illegal Combination Logic (ICL) Submodules
      1. 30.12.1 Minimum Dead-Band (MINDB)
      2. 30.12.2 Illegal Combo Logic (ICL)
    13. 30.13 Event-Trigger (ET) Submodule
      1. 30.13.1 Operational Overview of the ePWM Event-Trigger Submodule
    14. 30.14 Digital Compare (DC) Submodule
      1. 30.14.1 Purpose of the Digital Compare Submodule
      2. 30.14.2 Enhanced Trip Action Using CMPSS
      3. 30.14.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 30.14.4 Operation Highlights of the Digital Compare Submodule
        1. 30.14.4.1 Digital Compare Events
        2. 30.14.4.2 Event Filtering
        3. 30.14.4.3 Valley Switching
        4. 30.14.4.4 Event Detection
          1. 30.14.4.4.1 Input Signal Detection
          2. 30.14.4.4.2 MIN and MAX Detection Circuit
    15. 30.15 ePWM Crossbar (X-BAR)
    16. 30.16 Applications to Power Topologies
      1. 30.16.1  Overview of Multiple Modules
      2. 30.16.2  Key Configuration Capabilities
      3. 30.16.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 30.16.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 30.16.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 30.16.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 30.16.7  Practical Applications Using Phase Control Between PWM Modules
      8. 30.16.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 30.16.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 30.16.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 30.16.11 Controlling H-Bridge LLC Resonant Converter
    17. 30.17 Register Lock Protection
    18. 30.18 High-Resolution Pulse Width Modulator (HRPWM)
      1. 30.18.1 Operational Description of HRPWM
        1. 30.18.1.1 Controlling the HRPWM Capabilities
        2. 30.18.1.2 HRPWM Source Clock
        3. 30.18.1.3 Configuring the HRPWM
        4. 30.18.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 30.18.1.5 Principle of Operation
          1. 30.18.1.5.1 Edge Positioning
          2. 30.18.1.5.2 Scaling Considerations
          3. 30.18.1.5.3 Duty Cycle Range Limitation
          4. 30.18.1.5.4 High-Resolution Period
            1. 30.18.1.5.4.1 High-Resolution Period Configuration
        6. 30.18.1.6 Deadband High-Resolution Operation
        7. 30.18.1.7 Scale Factor Optimizing Software (SFO)
        8. 30.18.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 30.18.1.8.1 #Defines for HRPWM Header Files
          2. 30.18.1.8.2 Implementing a Simple Buck Converter
            1. 30.18.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 30.18.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 30.18.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 30.18.1.8.3.1 PWM DAC Function Initialization Code
            2. 30.18.1.8.3.2 PWM DAC Function Run-Time Code
      2. 30.18.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 30.18.2.1 Scale Factor Optimizer Function - int SFO()
        2. 30.18.2.2 Software Usage
          1. 30.18.2.2.1 A Sample of How to Add "Include" Files
          2.        1131
          3. 30.18.2.2.2 Declaring an Element
          4.        1133
          5. 30.18.2.2.3 Initializing With a Scale Factor Value
          6.        1135
          7. 30.18.2.2.4 SFO Function Calls
    19. 30.19 Software
      1. 30.19.1 EPWM Registers to Driverlib Functions
      2. 30.19.2 HRPWMCAL Registers to Driverlib Functions
      3. 30.19.3 EPWM Examples
        1. 30.19.3.1  ePWM Trip Zone - SINGLE_CORE
        2. 30.19.3.2  ePWM Up Down Count Action Qualifier - SINGLE_CORE
        3. 30.19.3.3  ePWM Synchronization - SINGLE_CORE
        4. 30.19.3.4  ePWM Digital Compare - SINGLE_CORE
        5. 30.19.3.5  ePWM Digital Compare Event Filter Blanking Window - SINGLE_CORE
        6. 30.19.3.6  ePWM Valley Switching - SINGLE_CORE
        7. 30.19.3.7  ePWM Digital Compare Edge Filter - SINGLE_CORE
        8. 30.19.3.8  ePWM Deadband - SINGLE_CORE
        9. 30.19.3.9  ePWM DMA - SINGLE_CORE
        10. 30.19.3.10 ePWM Chopper - SINGLE_CORE
        11. 30.19.3.11 EPWM Configure Signal - SINGLE_CORE
        12. 30.19.3.12 Realization of Monoshot mode - SINGLE_CORE
        13. 30.19.3.13 EPWM Action Qualifier (epwm_up_aq) - SINGLE_CORE
        14. 30.19.3.14 ePWM XCMP Mode - SINGLE_CORE
        15. 30.19.3.15 ePWM Event Detection - SINGLE_CORE
    20. 30.20 EPWM Registers
      1. 30.20.1 EPWM Base Address Table
      2. 30.20.2 EPWM_REGS Registers
      3. 30.20.3 EPWM_XCMP_REGS Registers
      4. 30.20.4 DE_REGS Registers
      5. 30.20.5 MINDB_LUT_REGS Registers
      6. 30.20.6 HRPWMCAL_REGS Registers
  33. 31Enhanced Quadrature Encoder Pulse (eQEP)
    1. 31.1  Introduction
      1. 31.1.1 EQEP Related Collateral
    2. 31.2  Configuring Device Pins
    3. 31.3  Description
      1. 31.3.1 EQEP Inputs
      2. 31.3.2 Functional Description
      3. 31.3.3 eQEP Memory Map
    4. 31.4  Quadrature Decoder Unit (QDU)
      1. 31.4.1 Position Counter Input Modes
        1. 31.4.1.1 Quadrature Count Mode
        2. 31.4.1.2 Direction-Count Mode
        3. 31.4.1.3 Up-Count Mode
        4. 31.4.1.4 Down-Count Mode
      2. 31.4.2 eQEP Input Polarity Selection
      3. 31.4.3 Position-Compare Sync Output
    5. 31.5  Position Counter and Control Unit (PCCU)
      1. 31.5.1 Position Counter Operating Modes
        1. 31.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 31.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 31.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 31.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 31.5.2 Position Counter Latch
        1. 31.5.2.1 Index Event Latch
        2. 31.5.2.2 Strobe Event Latch
      3. 31.5.3 Position Counter Initialization
      4. 31.5.4 eQEP Position-compare Unit
    6. 31.6  eQEP Edge Capture Unit
    7. 31.7  eQEP Watchdog
    8. 31.8  eQEP Unit Timer Base
    9. 31.9  QMA Module
      1. 31.9.1 Modes of Operation
        1. 31.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 31.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 31.9.2 Interrupt and Error Generation
    10. 31.10 eQEP Interrupt Structure
    11. 31.11 Software
      1. 31.11.1 EQEP Registers to Driverlib Functions
      2. 31.11.2 EQEP Examples
        1. 31.11.2.1 Frequency Measurement Using eQEP via unit timeout interrupt - SINGLE_CORE
        2. 31.11.2.2 Motor speed and direction measurement using eQEP via unit timeout interrupt - SINGLE_CORE
    12. 31.12 EQEP Registers
      1. 31.12.1 EQEP Base Address Table
      2. 31.12.2 EQEP_REGS Registers
  34. 32Sigma Delta Filter Module (SDFM)
    1. 32.1  Introduction
      1. 32.1.1 SDFM Related Collateral
      2. 32.1.2 Features
      3. 32.1.3 Block Diagram
    2. 32.2  Configuring Device Pins
    3. 32.3  Input Qualification
    4. 32.4  Input Control Unit
    5. 32.5  SDFM Clock Control
    6. 32.6  Sinc Filter
      1. 32.6.1 Data Rate and Latency of the Sinc Filter
    7. 32.7  Data (Primary) Filter Unit
      1. 32.7.1 32-bit or 16-bit Data Filter Output Representation
      2. 32.7.2 Data FIFO
      3. 32.7.3 SDSYNC Event
    8. 32.8  Comparator (Secondary) Filter Unit
      1. 32.8.1 Higher Threshold (HLT) Comparators
      2. 32.8.2 Lower Threshold (LLT) Comparators
      3. 32.8.3 Digital Filter
    9. 32.9  Theoretical SDFM Filter Output
    10. 32.10 Interrupt Unit
      1. 32.10.1 SDFM (SDyERR) Interrupt Sources
      2. 32.10.2 Data Ready (DRINT) Interrupt Sources
    11. 32.11 Software
      1. 32.11.1 SDFM Registers to Driverlib Functions
      2. 32.11.2 SDFM Examples
    12. 32.12 SDFM Registers
      1. 32.12.1 SDFM Base Address Table
      2. 32.12.2 SDFM_REGS Registers
  35. 33â–º COMMUNICATION PERIPHERALS
    1.     Technical Reference Manual Overview
  36. 34Modular Controller Area Network (MCAN)
    1. 34.1 MCAN Introduction
      1. 34.1.1 MCAN Related Collateral
      2. 34.1.2 MCAN Features
    2. 34.2 MCAN Environment
    3. 34.3 CAN Network Basics
    4. 34.4 MCAN Integration
    5. 34.5 MCAN Functional Description
      1. 34.5.1  Module Clocking Requirements
      2. 34.5.2  Interrupt Requests
      3. 34.5.3  Operating Modes
        1. 34.5.3.1 Software Initialization
        2. 34.5.3.2 Normal Operation
        3. 34.5.3.3 CAN FD Operation
      4. 34.5.4  Transmitter Delay Compensation
        1. 34.5.4.1 Description
        2. 34.5.4.2 Transmitter Delay Compensation Measurement
      5. 34.5.5  Restricted Operation Mode
      6. 34.5.6  Bus Monitoring Mode
      7. 34.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 34.5.7.1 Frame Transmission in DAR Mode
      8. 34.5.8  Clock Stop Mode
        1. 34.5.8.1 Suspend Mode
        2. 34.5.8.2 Wakeup Request
      9. 34.5.9  Test Modes
        1. 34.5.9.1 External Loop Back Mode
        2. 34.5.9.2 Internal Loop Back Mode
      10. 34.5.10 Timestamp Generation
        1. 34.5.10.1 External Timestamp Counter
      11. 34.5.11 Timeout Counter
      12. 34.5.12 Safety
        1. 34.5.12.1 ECC Wrapper
        2. 34.5.12.2 ECC Aggregator
          1. 34.5.12.2.1 ECC Aggregator Overview
          2. 34.5.12.2.2 ECC Aggregator Registers
        3. 34.5.12.3 Reads to ECC Control and Status Registers
        4. 34.5.12.4 ECC Interrupts
      13. 34.5.13 Rx Handling
        1. 34.5.13.1 Acceptance Filtering
          1. 34.5.13.1.1 Range Filter
          2. 34.5.13.1.2 Filter for Specific IDs
          3. 34.5.13.1.3 Classic Bit Mask Filter
          4. 34.5.13.1.4 Standard Message ID Filtering
          5. 34.5.13.1.5 Extended Message ID Filtering
        2. 34.5.13.2 Rx FIFOs
          1. 34.5.13.2.1 Rx FIFO Blocking Mode
          2. 34.5.13.2.2 Rx FIFO Overwrite Mode
        3. 34.5.13.3 Dedicated Rx Buffers
          1. 34.5.13.3.1 Rx Buffer Handling
      14. 34.5.14 Tx Handling
        1. 34.5.14.1 Transmit Pause
        2. 34.5.14.2 Dedicated Tx Buffers
        3. 34.5.14.3 Tx FIFO
        4. 34.5.14.4 Tx Queue
        5. 34.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 34.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 34.5.14.7 Transmit Cancellation
        8. 34.5.14.8 Tx Event Handling
      15. 34.5.15 FIFO Acknowledge Handling
      16. 34.5.16 Message RAM
        1. 34.5.16.1 Message RAM Configuration
        2. 34.5.16.2 Rx Buffer and FIFO Element
        3. 34.5.16.3 Tx Buffer Element
        4. 34.5.16.4 Tx Event FIFO Element
        5. 34.5.16.5 Standard Message ID Filter Element
        6. 34.5.16.6 Extended Message ID Filter Element
    6. 34.6 Software
      1. 34.6.1 MCAN Examples
        1. 34.6.1.1 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
        2. 34.6.1.2 MCAN Loopback with Polling Example Using SYSCONFIG Tool - SINGLE_CORE
        3. 34.6.1.3 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
    7. 34.7 MCAN Registers
      1. 34.7.1 MCAN Base Address Table
      2. 34.7.2 MCANSS_REGS Registers
      3. 34.7.3 MCAN_REGS Registers
      4. 34.7.4 MCAN_ERROR_REGS Registers
  37. 35EtherCAT® SubordinateDevice Controller (ESC)
    1. 35.1 Introduction
      1. 35.1.1  EtherCAT Related Collateral
      2. 35.1.2  ESC Features
      3. 35.1.3  ESC Subsystem Integrated Features
      4. 35.1.4  ESC versus Beckhoff ET1100
      5. 35.1.5  EtherCAT IP Block Diagram
      6. 35.1.6  ESC Functional Blocks
        1. 35.1.6.1  Interface to EtherCAT MainDevice
        2. 35.1.6.2  Process Data Interface
        3. 35.1.6.3  General-Purpose Inputs and Outputs
        4. 35.1.6.4  EtherCAT Processing Unit (EPU)
        5. 35.1.6.5  Fieldbus Memory Management Unit (FMMU)
        6. 35.1.6.6  Sync Manager
        7. 35.1.6.7  Monitoring
        8. 35.1.6.8  Reset Controller
        9. 35.1.6.9  PHY Management
        10. 35.1.6.10 Distributed Clock (DC)
        11. 35.1.6.11 EEPROM
        12. 35.1.6.12 Status / LEDs
      7. 35.1.7  EtherCAT Physical Layer
        1. 35.1.7.1 MII Interface
        2. 35.1.7.2 PHY Management Interface
          1. 35.1.7.2.1 PHY Address Configuration
          2. 35.1.7.2.2 PHY Reset Signal
          3. 35.1.7.2.3 PHY Clock
      8. 35.1.8  EtherCAT Protocol
      9. 35.1.9  EtherCAT State Machine (ESM)
      10. 35.1.10 More Information on EtherCAT
      11. 35.1.11 Beckhoff® Automation EtherCAT IP Errata
    2. 35.2 ESC and ESCSS Description
      1. 35.2.1  ESC RAM Parity and Memory Address Maps
        1. 35.2.1.1 ESC RAM Parity Logic
        2. 35.2.1.2 CPU1 ESC Memory Address Map
        3. 35.2.1.3 CPU2 ESC Memory Address Map
      2. 35.2.2  Local Host Communication
        1. 35.2.2.1 Byte Accessibility Through PDI
        2. 35.2.2.2 Software Details for Operation Across Clock Domains
      3. 35.2.3  Debug Emulation Mode Operation
      4. 35.2.4  ESC SubSystem
        1. 35.2.4.1 CPU1 Bus Interface
        2. 35.2.4.2 CPU2/CPU3 Bus Interface
      5. 35.2.5  Interrupts and Interrupt Mapping
      6. 35.2.6  Power, Clocks, and Resets
        1. 35.2.6.1 Power
        2. 35.2.6.2 Clocking
        3. 35.2.6.3 Resets
          1. 35.2.6.3.1 Chip-Level Reset
          2. 35.2.6.3.2 EtherCAT Soft Resets
          3. 35.2.6.3.3 Reset Out (RESET_OUT)
      7. 35.2.7  LED Controls
      8. 35.2.8  SubordinateDevice Node Configuration and EEPROM
      9. 35.2.9  General-Purpose Inputs and Outputs
        1. 35.2.9.1 General-Purpose Inputs
        2. 35.2.9.2 General-Purpose Output
      10. 35.2.10 Distributed Clocks – Sync and Latch
        1. 35.2.10.1 Clock Synchronization
        2. 35.2.10.2 SYNC Signals
          1. 35.2.10.2.1 Seeking Host Intervention
        3. 35.2.10.3 LATCH Signals
          1. 35.2.10.3.1 Timestamping
        4. 35.2.10.4 Device Control and Synchronization
          1. 35.2.10.4.1 Synchronization of PWM
          2. 35.2.10.4.2 ECAP SYNC Inputs
          3. 35.2.10.4.3 SYNC Signal Conditioning and Rerouting
    3. 35.3 Software Initialization Sequence and Allocating Ownership
    4. 35.4 ESC Configuration Constants
    5. 35.5 Software
      1. 35.5.1 ECAT_SS Registers to Driverlib Functions
      2. 35.5.2 ETHERNET Examples
    6. 35.6 ETHERCAT Registers
      1. 35.6.1 ETHERCAT Base Address Table
      2. 35.6.2 ESCSS_REGS Registers
      3. 35.6.3 ESCSS_CONFIG_REGS Registers
  38. 36Fast Serial Interface (FSI)
    1. 36.1 Introduction
      1. 36.1.1 FSI Related Collateral
      2. 36.1.2 FSI Features
    2. 36.2 System-level Integration
      1. 36.2.1 CPU Interface
      2. 36.2.2 Signal Description
        1. 36.2.2.1 Configuring Device Pins
      3. 36.2.3 FSI Interrupts
        1. 36.2.3.1 Transmitter Interrupts
        2. 36.2.3.2 Receiver Interrupts
        3. 36.2.3.3 Configuring Interrupts
        4. 36.2.3.4 Handling Interrupts
      4. 36.2.4 RTDMA Interface
      5. 36.2.5 External Frame Trigger Mux
    3. 36.3 FSI Functional Description
      1. 36.3.1 Introduction to Operation
      2. 36.3.2 FSI Transmitter Module
        1. 36.3.2.1 Initialization
        2. 36.3.2.2 FSI_TX Clocking
        3. 36.3.2.3 Transmitting Frames
          1. 36.3.2.3.1 Software Triggered Frames
          2. 36.3.2.3.2 Externally Triggered Frames
          3. 36.3.2.3.3 Ping Frame Generation
            1. 36.3.2.3.3.1 Automatic Ping Frames
            2. 36.3.2.3.3.2 Software Triggered Ping Frame
            3. 36.3.2.3.3.3 Externally Triggered Ping Frame
          4. 36.3.2.3.4 Transmitting Frames with RTDMA
        4. 36.3.2.4 Transmit Buffer Management
        5. 36.3.2.5 CRC Submodule
        6. 36.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 36.3.2.7 Reset
      3. 36.3.3 FSI Receiver Module
        1. 36.3.3.1  Initialization
        2. 36.3.3.2  FSI_RX Clocking
        3. 36.3.3.3  Receiving Frames
          1. 36.3.3.3.1 Receiving Frames with RTDMA
        4. 36.3.3.4  Ping Frame Watchdog
        5. 36.3.3.5  Frame Watchdog
        6. 36.3.3.6  Delay Line Control
        7. 36.3.3.7  Buffer Management
        8. 36.3.3.8  CRC Submodule
        9. 36.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 36.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 36.3.3.11 FSI_RX Reset
      4. 36.3.4 Frame Format
        1. 36.3.4.1 FSI Frame Phases
        2. 36.3.4.2 Frame Types
          1. 36.3.4.2.1 Ping Frames
          2. 36.3.4.2.2 Error Frames
          3. 36.3.4.2.3 Data Frames
        3. 36.3.4.3 Multi-Lane Transmission
      5. 36.3.5 Flush Sequence
      6. 36.3.6 Internal Loopback
      7. 36.3.7 CRC Generation
      8. 36.3.8 ECC Module
      9. 36.3.9 FSI-SPI Compatibility Mode
        1. 36.3.9.1 Available SPI Modes
          1. 36.3.9.1.1 FSITX as SPI Controller, Transmit Only
            1. 36.3.9.1.1.1 Initialization
            2. 36.3.9.1.1.2 Operation
          2. 36.3.9.1.2 FSIRX as SPI Peripheral, Receive Only
            1. 36.3.9.1.2.1 Initialization
            2. 36.3.9.1.2.2 Operation
          3. 36.3.9.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
            1. 36.3.9.1.3.1 Initialization
            2. 36.3.9.1.3.2 Operation
    4. 36.4 FSI Programing Guide
      1. 36.4.1 Establishing the Communication Link
        1. 36.4.1.1 Establishing the Communication Link from the Main Device
        2. 36.4.1.2 Establishing the Communication Link from the Remote Device
      2. 36.4.2 Register Protection
      3. 36.4.3 Emulation Mode
    5. 36.5 Software
      1. 36.5.1 FSI Registers to Driverlib Functions
      2. 36.5.2 FSI Examples
        1. 36.5.2.1 FSI Loopback:CPU Control - SINGLE_CORE
        2. 36.5.2.2 FSI data transfers upon CPU Timer event - SINGLE_CORE
    6. 36.6 FSI Registers
      1. 36.6.1 FSI Base Address Table
      2. 36.6.2 FSI_TX_REGS Registers
      3. 36.6.3 FSI_RX_REGS Registers
  39. 37Inter-Integrated Circuit Module (I2C)
    1. 37.1 Introduction
      1. 37.1.1 I2C Related Collateral
      2. 37.1.2 Features
      3. 37.1.3 Features Not Supported
      4. 37.1.4 Functional Overview
      5. 37.1.5 Clock Generation
      6. 37.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 37.1.6.1 Formula for the Controller Clock Period
    2. 37.2 Configuring Device Pins
    3. 37.3 I2C Module Operational Details
      1. 37.3.1  Input and Output Voltage Levels
      2. 37.3.2  Selecting Pullup Resistors
      3. 37.3.3  Data Validity
      4. 37.3.4  Operating Modes
      5. 37.3.5  I2C Module START and STOP Conditions
      6. 37.3.6  Non-repeat Mode versus Repeat Mode
      7. 37.3.7  Serial Data Formats
        1. 37.3.7.1 7-Bit Addressing Format
        2. 37.3.7.2 10-Bit Addressing Format
        3. 37.3.7.3 Free Data Format
        4. 37.3.7.4 Using a Repeated START Condition
      8. 37.3.8  Clock Synchronization
      9. 37.3.9  Clock Stretching
      10. 37.3.10 Arbitration
      11. 37.3.11 Digital Loopback Mode
      12. 37.3.12 NACK Bit Generation
    4. 37.4 Interrupt Requests Generated by the I2C Module
      1. 37.4.1 Basic I2C Interrupt Requests
      2. 37.4.2 I2C FIFO Interrupts
    5. 37.5 Resetting or Disabling the I2C Module
    6. 37.6 Software
      1. 37.6.1 I2C Registers to Driverlib Functions
      2. 37.6.2 I2C Examples
        1. 37.6.2.1 I2C Digital Loopback with FIFO Interrupts - SINGLE_CORE
        2. 37.6.2.2 I2C EEPROM - SINGLE_CORE
        3. 37.6.2.3 I2C Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        4. 37.6.2.4 I2C Extended Clock Stretching Controller TX - SINGLE_CORE
        5. 37.6.2.5 I2C Extended Clock Stretching Target RX - SINGLE_CORE
    7. 37.7 I2C Registers
      1. 37.7.1 I2C Base Address Table
      2. 37.7.2 I2C_REGS Registers
  40. 38Power Management Bus Module (PMBus)
    1. 38.1 Introduction
      1. 38.1.1 PMBUS Related Collateral
      2. 38.1.2 Features
      3. 38.1.3 Block Diagram
    2. 38.2 Configuring Device Pins
    3. 38.3 Target Mode Operation
      1. 38.3.1 Configuration
      2. 38.3.2 Message Handling
        1. 38.3.2.1  Quick Command
        2. 38.3.2.2  Send Byte
        3. 38.3.2.3  Receive Byte
        4. 38.3.2.4  Write Byte and Write Word
        5. 38.3.2.5  Read Byte and Read Word
        6. 38.3.2.6  Process Call
        7. 38.3.2.7  Block Write
        8. 38.3.2.8  Block Read
        9. 38.3.2.9  Block Write-Block Read Process Call
        10. 38.3.2.10 Alert Response
        11. 38.3.2.11 Extended Command
        12. 38.3.2.12 Group Command
    4. 38.4 Controller Mode Operation
      1. 38.4.1 Configuration
      2. 38.4.2 Message Handling
        1. 38.4.2.1  Quick Command
        2. 38.4.2.2  Send Byte
        3. 38.4.2.3  Receive Byte
        4. 38.4.2.4  Write Byte and Write Word
        5. 38.4.2.5  Read Byte and Read Word
        6. 38.4.2.6  Process Call
        7. 38.4.2.7  Block Write
        8. 38.4.2.8  Block Read
        9. 38.4.2.9  Block Write-Block Read Process Call
        10. 38.4.2.10 Alert Response
        11. 38.4.2.11 Extended Command
        12. 38.4.2.12 Group Command
    5. 38.5 Software
      1. 38.5.1 PMBUS Registers to Driverlib Functions
    6. 38.6 PMBUS Registers
      1. 38.6.1 PMBUS Base Address Table
      2. 38.6.2 PMBUS_REGS Registers
  41. 39Universal Asynchronous Receiver/Transmitter (UART)
    1. 39.1 Introduction
      1. 39.1.1 Features
      2. 39.1.2 UART Related Collateral
      3. 39.1.3 Block Diagram
    2. 39.2 Functional Description
      1. 39.2.1 Transmit and Receive Logic
      2. 39.2.2 Baud-Rate Generation
      3. 39.2.3 Data Transmission
      4. 39.2.4 Serial IR (SIR)
      5. 39.2.5 9-Bit UART Mode
      6. 39.2.6 FIFO Operation
      7. 39.2.7 Interrupts
      8. 39.2.8 Loopback Operation
      9. 39.2.9 RTDMA Operation
        1. 39.2.9.1 Receiving Data Using UART with RTDMA
        2. 39.2.9.2 Transmitting Data Using UART with RTDMA
    3. 39.3 Initialization and Configuration
    4. 39.4 Software
      1. 39.4.1 UART Registers to Driverlib Functions
      2. 39.4.2 UART Examples
        1. 39.4.2.1 UART Loopback - SINGLE_CORE
        2. 39.4.2.2 UART Loopback with Interrupt - SINGLE_CORE
        3. 39.4.2.3 UART Loopback with DMA - SINGLE_CORE
        4. 39.4.2.4 UART Echoback - SINGLE_CORE
    5. 39.5 UART Registers
      1. 39.5.1 UART Base Address Table
      2. 39.5.2 UART_REGS Registers
      3. 39.5.3 UART_REGS_WRITE Registers
  42. 40Local Interconnect Network (LIN)
    1. 40.1 LIN Overview
      1. 40.1.1 LIN Mode Features
      2. 40.1.2 SCI Mode Features
      3. 40.1.3 Block Diagram
    2. 40.2 Serial Communications Interface Module
      1. 40.2.1 SCI Communication Formats
        1. 40.2.1.1 SCI Frame Formats
        2. 40.2.1.2 SCI Asynchronous Timing Mode
        3. 40.2.1.3 SCI Baud Rate
          1. 40.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 40.2.1.4 SCI Multiprocessor Communication Modes
          1. 40.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 40.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 40.2.1.5 SCI Multibuffered Mode
      2. 40.2.2 SCI Interrupts
        1. 40.2.2.1 Transmit Interrupt
        2. 40.2.2.2 Receive Interrupt
        3. 40.2.2.3 WakeUp Interrupt
        4. 40.2.2.4 Error Interrupts
      3. 40.2.3 SCI RTDMA Interface
        1. 40.2.3.1 Receive RTDMA Requests
        2. 40.2.3.2 Transmit RTDMA Requests
      4. 40.2.4 SCI Configurations
        1. 40.2.4.1 Receiving Data
          1. 40.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 40.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 40.2.4.2 Transmitting Data
          1. 40.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 40.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 40.2.5 SCI Low-Power Mode
        1. 40.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 40.3 Local Interconnect Network Module
      1. 40.3.1 LIN Communication Formats
        1. 40.3.1.1  LIN Standards
        2. 40.3.1.2  Message Frame
          1. 40.3.1.2.1 Message Header
          2. 40.3.1.2.2 Response
        3. 40.3.1.3  Synchronizer
        4. 40.3.1.4  Baud Rate
          1. 40.3.1.4.1 Fractional Divider
          2. 40.3.1.4.2 Superfractional Divider
            1. 40.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 40.3.1.5  Header Generation
          1. 40.3.1.5.1 Event Triggered Frame Handling
          2. 40.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 40.3.1.6  Extended Frames Handling
        7. 40.3.1.7  Timeout Control
          1. 40.3.1.7.1 No-Response Error (NRE)
          2. 40.3.1.7.2 Bus Idle Detection
          3. 40.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 40.3.1.8  TXRX Error Detector (TED)
          1. 40.3.1.8.1 Bit Errors
          2. 40.3.1.8.2 Physical Bus Errors
          3. 40.3.1.8.3 ID Parity Errors
          4. 40.3.1.8.4 Checksum Errors
        9. 40.3.1.9  Message Filtering and Validation
        10. 40.3.1.10 Receive Buffers
        11. 40.3.1.11 Transmit Buffers
      2. 40.3.2 LIN Interrupts
      3. 40.3.3 Servicing LIN Interrupts
      4. 40.3.4 LIN RTDMA Interface
        1. 40.3.4.1 LIN Receive RTDMA Requests
        2. 40.3.4.2 LIN Transmit RTDMA Requests
      5. 40.3.5 LIN Configurations
        1. 40.3.5.1 Receiving Data
          1. 40.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 40.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 40.3.5.2 Transmitting Data
          1. 40.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 40.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 40.4 Low-Power Mode
      1. 40.4.1 Entering Sleep Mode
      2. 40.4.2 Wakeup
      3. 40.4.3 Wakeup Timeouts
    5. 40.5 Emulation Mode
    6. 40.6 Software
      1. 40.6.1 LIN Registers to Driverlib Functions
      2. 40.6.2 LIN Examples
        1. 40.6.2.1 LIN Internal Loopback with Interrupts - SINGLE_CORE
        2. 40.6.2.2 LIN SCI Mode Internal Loopback with Interrupts - SINGLE_CORE
        3. 40.6.2.3 LIN SCI MODE Internal Loopback with DMA - SINGLE_CORE
        4. 40.6.2.4 LIN Internal Loopback without interrupts (polled mode) - SINGLE_CORE
        5. 40.6.2.5 LIN SCI MODE (Single Buffer) Internal Loopback with DMA - SINGLE_CORE
    7. 40.7 LIN Registers
      1. 40.7.1 LIN Base Address Table
      2. 40.7.2 LIN_REGS Registers
  43. 41Serial Peripheral Interface (SPI)
    1. 41.1 Introduction
      1. 41.1.1 Features
      2. 41.1.2 Block Diagram
    2. 41.2 System-Level Integration
      1. 41.2.1 SPI Module Signals
      2. 41.2.2 Configuring Device Pins
        1. 41.2.2.1 GPIOs Required for High-Speed Mode
      3. 41.2.3 SPI Interrupts
      4. 41.2.4 RTDMA Support
    3. 41.3 SPI Operation
      1. 41.3.1  Introduction to Operation
      2. 41.3.2  Controller Mode
      3. 41.3.3  Peripheral Mode
      4. 41.3.4  Data Format
        1. 41.3.4.1 Transmission of Bit from SPIRXBUF
      5. 41.3.5  Baud Rate Selection
        1. 41.3.5.1 Baud Rate Determination
        2. 41.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
        3. 41.3.5.3 Baud Rate Calculation
      6. 41.3.6  SPI Clocking Schemes
      7. 41.3.7  SPI FIFO Description
      8. 41.3.8  SPI RTDMA Transfers
        1. 41.3.8.1 Transmitting Data Using SPI with RTDMA
        2. 41.3.8.2 Receiving Data Using SPI with RTDMA
      9. 41.3.9  SPI High-Speed Mode
      10. 41.3.10 SPI 3-Wire Mode Description
    4. 41.4 Programming Procedure
      1. 41.4.1 Initialization Upon Reset
      2. 41.4.2 Configuring the SPI
      3. 41.4.3 Configuring the SPI for High-Speed Mode
      4. 41.4.4 Data Transfer Example
      5. 41.4.5 SPI 3-Wire Mode Code Examples
        1. 41.4.5.1 3-Wire Controller Mode Transmit
        2.       1703
          1. 41.4.5.2.1 3-Wire Controller Mode Receive
        3.       1705
          1. 41.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       1707
          1. 41.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 41.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 41.5 Software
      1. 41.5.1 SPI Registers to Driverlib Functions
      2. 41.5.2 SPI Examples
        1. 41.5.2.1 SPI Digital Loopback - SINGLE_CORE
        2. 41.5.2.2 SPI Digital Loopback with FIFO Interrupts - SINGLE_CORE
        3. 41.5.2.3 SPI Digital External Loopback without FIFO Interrupts - SINGLE_CORE
        4. 41.5.2.4 SPI Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        5. 41.5.2.5 SPI Digital Loopback with DMA - SINGLE_CORE
    6. 41.6 SPI Registers
      1. 41.6.1 SPI Base Address Table
      2. 41.6.2 SPI_REGS Registers
  44. 42Single Edge Nibble Transmission (SENT)
    1. 42.1 Introduction
      1. 42.1.1 Features
      2. 42.1.2 SENT Related Collateral
    2. 42.2 Advanced Topologies: MTPG
      1. 42.2.1 MTPG Features
      2. 42.2.2 MTPG Description
      3. 42.2.3 Channel Triggers
      4. 42.2.4 Timeout
    3. 42.3 Protocol Description
      1. 42.3.1 Nibble Frame Format
      2. 42.3.2 CRC
      3. 42.3.3 Short Serial Message Format
      4. 42.3.4 Enhanced Serial Message Format
      5. 42.3.5 Enhanced Serial Message Format CRC
      6. 42.3.6 Receive Modes
    4. 42.4 RTDMA Trigger
    5. 42.5 Interrupts Configuration
    6. 42.6 Glitch Filter
    7. 42.7 Software
      1. 42.7.1 SENT Registers to Driverlib Functions
      2. 42.7.2 SENT Examples
        1. 42.7.2.1 SENT Single Sensor - SINGLE_CORE
    8. 42.8 SENT Registers
      1. 42.8.1 SENT Base Address Table
      2. 42.8.2 SENT_CFG Registers
      3. 42.8.3 SENT_MEM Registers
      4. 42.8.4 SENT_MTPG Registers
  45. 43â–º SECURITY PERIPHERALS
    1.     Technical Reference Manual Overview
  46. 44Security Modules
    1. 44.1 Hardware Security Module (HSM)
      1. 44.1.1 HSM Related Collateral
    2. 44.2 Cryptographic Accelerators
  47. 45Revision History

8.9.3 ERROR_AGGREGATOR_CONFIG_REGS Registers

Table 8-24 lists the memory-mapped registers for the ERROR_AGGREGATOR_CONFIG_REGS registers. All register offset addresses not listed in Table 8-24 should be considered as reserved locations and the register contents should not be modified.

Table 8-24 ERROR_AGGREGATOR_CONFIG_REGS Registers
OffsetAcronymRegister NameProtection
0hCPU1_PR_HIGHPRIO_ERROR_ADDRESSCPU1 PR Error aggregator High Priority Error address register
4hCPU1_PR_LOWPRIO_ERROR_ADDRESSCPU1 PR Error aggregator Low Priority Error address register
8hCPU1_PR_ERROR_TYPECPU1 PR Error aggregator Error Type Register
ChCPU1_PR_ERROR_TYPE_FRCCPU1 PR Error aggregator Error Type Force Register
10hCPU1_PR_ERROR_TYPE_CLRCPU1 PR Error aggregator Error Type Clear Register
14hCPU1_PR_PCCPU1 PR Error aggregator Register to store PC value at the first High priority error event
40hCPU1_DR1_HIGHPRIO_ERROR_ADDRESSCPU1 DR1 Error aggregator High Priority Error address register
44hCPU1_DR1_LOWPRIO_ERROR_ADDRESSCPU1 DR1 Error aggregator Low Priority Error address register
48hCPU1_DR1_ERROR_TYPECPU1 DR1 Error aggregator Error Type Register
4ChCPU1_DR1_ERROR_TYPE_FRCCPU1 DR1 Error aggregator Error Type Force Register
50hCPU1_DR1_ERROR_TYPE_CLRCPU1 DR1 Error aggregator Error Type Clear Register
54hCPU1_DR1_PCCPU1 DR1 Error aggregator Register to store PC value at the first High priority error event
80hCPU1_DR2_HIGHPRIO_ERROR_ADDRESSCPU1 DR2 Error aggregator High Priority Error address register
84hCPU1_DR2_LOWPRIO_ERROR_ADDRESSCPU1 DR2 Error aggregator Low Priority Error address register
88hCPU1_DR2_ERROR_TYPECPU1 DR2 Error aggregator Error Type Register
8ChCPU1_DR2_ERROR_TYPE_FRCCPU1 DR2 Error aggregator Error Type Force Register
90hCPU1_DR2_ERROR_TYPE_CLRCPU1 DR2 Error aggregator Error Type Clear Register
94hCPU1_DR2_PCCPU1 DR2 Error aggregator Register to store PC value at the first High priority error event
C0hCPU1_DW_HIGHPRIO_ERROR_ADDRESSCPU1 DW Error aggregator High Priority Error address register
C4hCPU1_DW_LOWPRIO_ERROR_ADDRESSCPU1 DW Error aggregator Low Priority Error address register
C8hCPU1_DW_ERROR_TYPECPU1 DW Error aggregator Error Type Register
CChCPU1_DW_ERROR_TYPE_FRCCPU1 DW Error aggregator Error Type Force Register
D0hCPU1_DW_ERROR_TYPE_CLRCPU1 DW Error aggregator Error Type Clear Register
D4hCPU1_DW_PCCPU1 DW Error aggregator Register to store PC value at the first High priority error event
100hCPU1_INT_HIGHPRIO_ERROR_ADDRESSCPU1 INT Error aggregator High Priority Error address register
104hCPU1_INT_LOWPRIO_ERROR_ADDRESSCPU1 INT Error aggregator Low Priority Error address register
108hCPU1_INT_ERROR_TYPECPU1 INT Error aggregator Error Type Register
10ChCPU1_INT_ERROR_TYPE_FRCCPU1 INT Error aggregator Error Type Force Register
110hCPU1_INT_ERROR_TYPE_CLRCPU1 INT Error aggregator Error Type Clear Register
114hCPU1_INT_PCCPU1 INT Error aggregator Register to store PC value at the first High priority error event
140hCPU2_PR_HIGHPRIO_ERROR_ADDRESSCPU2 PR Error aggregator High Priority Error address register
144hCPU2_PR_LOWPRIO_ERROR_ADDRESSCPU2 PR Error aggregator Low Priority Error address register
148hCPU2_PR_ERROR_TYPECPU2 PR Error aggregator Error Type Register
14ChCPU2_PR_ERROR_TYPE_FRCCPU2 PR Error aggregator Error Type Force Register
150hCPU2_PR_ERROR_TYPE_CLRCPU2 PR Error aggregator Error Type Clear Register
154hCPU2_PR_PCCPU2 PR Error aggregator Register to store PC value at the first High priority error event
180hCPU2_DR1_HIGHPRIO_ERROR_ADDRESSCPU2 DR1 Error aggregator High Priority Error address register
184hCPU2_DR1_LOWPRIO_ERROR_ADDRESSCPU2 DR1 Error aggregator Low Priority Error address register
188hCPU2_DR1_ERROR_TYPECPU2 DR1 Error aggregator Error Type Register
18ChCPU2_DR1_ERROR_TYPE_FRCCPU2 DR1 Error aggregator Error Type Force Register
190hCPU2_DR1_ERROR_TYPE_CLRCPU2 DR1 Error aggregator Error Type Clear Register
194hCPU2_DR1_PCCPU2 DR1 Error aggregator Register to store PC value at the first High priority error event
1C0hCPU2_DR2_HIGHPRIO_ERROR_ADDRESSCPU2 DR2 Error aggregator High Priority Error address register
1C4hCPU2_DR2_LOWPRIO_ERROR_ADDRESSCPU2 DR2 Error aggregator Low Priority Error address register
1C8hCPU2_DR2_ERROR_TYPECPU2 DR2 Error aggregator Error Type Register
1CChCPU2_DR2_ERROR_TYPE_FRCCPU2 DR2 Error aggregator Error Type Force Register
1D0hCPU2_DR2_ERROR_TYPE_CLRCPU2 DR2 Error aggregator Error Type Clear Register
1D4hCPU2_DR2_PCCPU2 DR2 Error aggregator Register to store PC value at the first High priority error event
200hCPU2_DW_HIGHPRIO_ERROR_ADDRESSCPU2 DW Error aggregator High Priority Error address register
204hCPU2_DW_LOWPRIO_ERROR_ADDRESSCPU2 DW Error aggregator Low Priority Error address register
208hCPU2_DW_ERROR_TYPECPU2 DW Error aggregator Error Type Register
20ChCPU2_DW_ERROR_TYPE_FRCCPU2 DW Error aggregator Error Type Force Register
210hCPU2_DW_ERROR_TYPE_CLRCPU2 DW Error aggregator Error Type Clear Register
214hCPU2_DW_PCCPU2 DW Error aggregator Register to store PC value at the first High priority error event
240hCPU2_INT_HIGHPRIO_ERROR_ADDRESSCPU2 INT Error aggregator High Priority Error address register
244hCPU2_INT_LOWPRIO_ERROR_ADDRESSCPU2 INT Error aggregator Low Priority Error address register
248hCPU2_INT_ERROR_TYPECPU2 INT Error aggregator Error Type Register
24ChCPU2_INT_ERROR_TYPE_FRCCPU2 INT Error aggregator Error Type Force Register
250hCPU2_INT_ERROR_TYPE_CLRCPU2 INT Error aggregator Error Type Clear Register
254hCPU2_INT_PCCPU2 INT Error aggregator Register to store PC value at the first High priority error event
280hCPU3_PR_HIGHPRIO_ERROR_ADDRESSCPU3 PR Error aggregator High Priority Error address register
284hCPU3_PR_LOWPRIO_ERROR_ADDRESSCPU3 PR Error aggregator Low Priority Error address register
288hCPU3_PR_ERROR_TYPECPU3 PR Error aggregator Error Type Register
28ChCPU3_PR_ERROR_TYPE_FRCCPU3 PR Error aggregator Error Type Force Register
290hCPU3_PR_ERROR_TYPE_CLRCPU3 PR Error aggregator Error Type Clear Register
294hCPU3_PR_PCCPU3 PR Error aggregator Register to store PC value at the first High priority error event
2C0hCPU3_DR1_HIGHPRIO_ERROR_ADDRESSCPU3 DR1 Error aggregator High Priority Error address register
2C4hCPU3_DR1_LOWPRIO_ERROR_ADDRESSCPU3 DR1 Error aggregator Low Priority Error address register
2C8hCPU3_DR1_ERROR_TYPECPU3 DR1 Error aggregator Error Type Register
2CChCPU3_DR1_ERROR_TYPE_FRCCPU3 DR1 Error aggregator Error Type Force Register
2D0hCPU3_DR1_ERROR_TYPE_CLRCPU3 DR1 Error aggregator Error Type Clear Register
2D4hCPU3_DR1_PCCPU3 DR1 Error aggregator Register to store PC value at the first High priority error event
300hCPU3_DR2_HIGHPRIO_ERROR_ADDRESSCPU3 DR2 Error aggregator High Priority Error address register
304hCPU3_DR2_LOWPRIO_ERROR_ADDRESSCPU3 DR2 Error aggregator Low Priority Error address register
308hCPU3_DR2_ERROR_TYPECPU3 DR2 Error aggregator Error Type Register
30ChCPU3_DR2_ERROR_TYPE_FRCCPU3 DR2 Error aggregator Error Type Force Register
310hCPU3_DR2_ERROR_TYPE_CLRCPU3 DR2 Error aggregator Error Type Clear Register
314hCPU3_DR2_PCCPU3 DR2 Error aggregator Register to store PC value at the first High priority error event
340hCPU3_DW_HIGHPRIO_ERROR_ADDRESSCPU3 DW Error aggregator High Priority Error address register
344hCPU3_DW_LOWPRIO_ERROR_ADDRESSCPU3 DW Error aggregator Low Priority Error address register
348hCPU3_DW_ERROR_TYPECPU3 DW Error aggregator Error Type Register
34ChCPU3_DW_ERROR_TYPE_FRCCPU3 DW Error aggregator Error Type Force Register
350hCPU3_DW_ERROR_TYPE_CLRCPU3 DW Error aggregator Error Type Clear Register
354hCPU3_DW_PCCPU3 DW Error aggregator Register to store PC value at the first High priority error event
380hCPU3_INT_HIGHPRIO_ERROR_ADDRESSCPU3 INT Error aggregator High Priority Error address register
384hCPU3_INT_LOWPRIO_ERROR_ADDRESSCPU3 INT Error aggregator Low Priority Error address register
388hCPU3_INT_ERROR_TYPECPU3 INT Error aggregator Error Type Register
38ChCPU3_INT_ERROR_TYPE_FRCCPU3 INT Error aggregator Error Type Force Register
390hCPU3_INT_ERROR_TYPE_CLRCPU3 INT Error aggregator Error Type Clear Register
394hCPU3_INT_PCCPU3 INT Error aggregator Register to store PC value at the first High priority error event
780hRTDMA1_DR_HIGHPRIO_ERROR_ADDRESSRTDMA1 DR Error aggregator High Priority Error address register
784hRTDMA1_DR_LOWPRIO_ERROR_ADDRESSRTDMA1 DR Error aggregator Low Priority Error address register
788hRTDMA1_DR_ERROR_TYPERTDMA1 DR Error aggregator Error Type Register
78ChRTDMA1_DR_ERROR_TYPE_FRCRTDMA1 DR Error aggregator Error Type Force Register
790hRTDMA1_DR_ERROR_TYPE_CLRRTDMA1 DR Error aggregator Error Type Clear Register
7C0hRTDMA1_DW_HIGHPRIO_ERROR_ADDRESSRTDMA1 DW Error aggregator High Priority Error address register
7C4hRTDMA1_DW_LOWPRIO_ERROR_ADDRESSRTDMA1 DW Error aggregator Low Priority Error address register
7C8hRTDMA1_DW_ERROR_TYPERTDMA1 DW Error aggregator Error Type Register
7CChRTDMA1_DW_ERROR_TYPE_FRCRTDMA1 DW Error aggregator Error Type Force Register
7D0hRTDMA1_DW_ERROR_TYPE_CLRRTDMA1 DW Error aggregator Error Type Clear Register
800hRTDMA2_DR_HIGHPRIO_ERROR_ADDRESSRTDMA2 DR Error aggregator High Priority Error address register
804hRTDMA2_DR_LOWPRIO_ERROR_ADDRESSRTDMA2 DR Error aggregator Low Priority Error address register
808hRTDMA2_DR_ERROR_TYPERTDMA2 DR Error aggregator Error Type Register
80ChRTDMA2_DR_ERROR_TYPE_FRCRTDMA2 DR Error aggregator Error Type Force Register
810hRTDMA2_DR_ERROR_TYPE_CLRRTDMA2 DR Error aggregator Error Type Clear Register
840hRTDMA2_DW_HIGHPRIO_ERROR_ADDRESSRTDMA2 DW Error aggregator High Priority Error address register
844hRTDMA2_DW_LOWPRIO_ERROR_ADDRESSRTDMA2 DW Error aggregator Low Priority Error address register
848hRTDMA2_DW_ERROR_TYPERTDMA2 DW Error aggregator Error Type Register
84ChRTDMA2_DW_ERROR_TYPE_FRCRTDMA2 DW Error aggregator Error Type Force Register
850hRTDMA2_DW_ERROR_TYPE_CLRRTDMA2 DW Error aggregator Error Type Clear Register
880hSSU_HIGHPRIO_ERROR_ADDRESSSSU Error aggregator High Priority Error address register
888hSSU_ERROR_TYPESSU Error aggregator Error Type Register
88ChSSU_ERROR_TYPE_FRCSSU Error aggregator Error Type Force Register
890hSSU_ERROR_TYPE_CLRSSU Error aggregator Error Type Clear Register
8C0hETHERCAT_HIGHPRIO_ERROR_ADDRESSETHERCAT Error aggregator High Priority Error address register
8C8hETHERCAT_ERROR_TYPEETHERCAT Error aggregator Error Type Register
8CChETHERCAT_ERROR_TYPE_FRCETHERCAT Error aggregator Error Type Force Register
8D0hETHERCAT_ERROR_TYPE_CLRETHERCAT Error aggregator Error Type Clear Register

Complex bit access types are encoded to fit into small table cells. Table 8-25 shows the codes that are used for access types in this section.

Table 8-25 ERROR_AGGREGATOR_CONFIG_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

8.9.3.1 CPU1_PR_HIGHPRIO_ERROR_ADDRESS Register (Offset = 0h) [Reset = 00000000h]

CPU1_PR_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-9 and described in Table 8-26.

Return to the Summary Table.

CPU1 PR Error aggregator High Priority Error address register

Figure 8-9 CPU1_PR_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU1_PR_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-26 CPU1_PR_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_PR_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU1_PR access

Reset type: PORESETn

8.9.3.2 CPU1_PR_LOWPRIO_ERROR_ADDRESS Register (Offset = 4h) [Reset = 00000000h]

CPU1_PR_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-10 and described in Table 8-27.

Return to the Summary Table.

CPU1 PR Error aggregator Low Priority Error address register

Figure 8-10 CPU1_PR_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU1_PR_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-27 CPU1_PR_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_PR_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU1_PR access

Reset type: PORESETn

8.9.3.3 CPU1_PR_ERROR_TYPE Register (Offset = 8h) [Reset = 00000000h]

CPU1_PR_ERROR_TYPE is shown in Figure 8-11 and described in Table 8-28.

Return to the Summary Table.

CPU1 PR Error aggregator Error Type Register

Figure 8-11 CPU1_PR_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDINSTRUCTION_TIMEOUTILLEGAL_INSTRUCTIONSW_BREAKPOINT_ERRWARN_PSP_ERR
R-0hR-0hR-0hR-0hR-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRMAX_PSP_ERRSEC_EXIT_VIOSEC_ENTRY_VIOINSTR_SECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-28 CPU1_PR_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority set by software

Reset type: PORESETn

29-12RESERVEDR0hReserved
11INSTRUCTION_TIMEOUTR0hInstruction timeout error

Reset type: PORESETn

10ILLEGAL_INSTRUCTIONR0hIllegal instruction error

Reset type: PORESETn

9SW_BREAKPOINT_ERRR0hSoftware brakepoint error

Reset type: PORESETn

8WARN_PSP_ERRR0hWarn PSP error

Reset type: PORESETn

7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0h Uncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0h Access timeout error

Reset type: PORESETn

3MAX_PSP_ERRR0h MAX PSP error

Reset type: PORESETn

2SEC_EXIT_VIOR0hSecure exit error

Reset type: PORESETn

1SEC_ENTRY_VIOR0hSecure entry and linear code crossing LINK, STACK, ZONE error.

Reset type: PORESETn

0INSTR_SECURITY_VIOR0hInstruction packet security violation. Instruction packet crossed LINK, STACK, ZONE boundary.

Reset type: PORESETn

8.9.3.4 CPU1_PR_ERROR_TYPE_FRC Register (Offset = Ch) [Reset = 00000000h]

CPU1_PR_ERROR_TYPE_FRC is shown in Figure 8-12 and described in Table 8-29.

Return to the Summary Table.

CPU1 PR Error aggregator Error Type Force Register

Figure 8-12 CPU1_PR_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDINSTRUCTION_TIMEOUTILLEGAL_INSTRUCTIONSW_BREAKPOINT_ERRWARN_PSP_ERR
R-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRMAX_PSP_ERRSEC_EXIT_VIOSEC_ENTRY_VIOINSTR_SECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 8-29 CPU1_PR_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hForce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-12RESERVEDR0hReserved
11INSTRUCTION_TIMEOUTR-0/W1S0hInstruction timeout error flag force register
0 - No action
1 - force Instruction timeout flag

Reset type: PORESETn

10ILLEGAL_INSTRUCTIONR-0/W1S0hIllegal instruction error flag force register
0 - No action
1 - Illegal instruction error flag

Reset type: PORESETn

9SW_BREAKPOINT_ERRR-0/W1S0hSoftware brakepoint error flag force register
0 - No action
1 - force Software brakepoint error flag

Reset type: PORESETn

8WARN_PSP_ERRR-0/W1S0hWARN PSP violation flag force register
0 - No action
1 - force WARN PSP violation flag

Reset type: PORESETn

7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3MAX_PSP_ERRR-0/W1S0hMAX PSP violation flag force register
0 - No action
1 - force MAX PSP violation flag

Reset type: PORESETn

2SEC_EXIT_VIOR-0/W1S0hSecure exit violation flag force register
0 - No action
1 - force Secure exit violation flag

Reset type: PORESETn

1SEC_ENTRY_VIOR-0/W1S0hSecure entry violation flag force register
0 - No action
1 - force Secure entry violation flag

Reset type: PORESETn

0INSTR_SECURITY_VIOR-0/W1S0hInstruction packet security violation flag force register
0 - No action
1 - force Instruction packet security violation flag

Reset type: PORESETn

8.9.3.5 CPU1_PR_ERROR_TYPE_CLR Register (Offset = 10h) [Reset = 00000000h]

CPU1_PR_ERROR_TYPE_CLR is shown in Figure 8-13 and described in Table 8-30.

Return to the Summary Table.

CPU1 PR Error aggregator Error Type Clear Register

Figure 8-13 CPU1_PR_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDINSTRUCTION_TIMEOUTILLEGAL_INSTRUCTIONSW_BREAKPOINT_ERRWARN_PSP_ERR
R-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRMAX_PSP_ERRSEC_EXIT_VIOSEC_ENTRY_VIOINSTR_SECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 8-30 CPU1_PR_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-12RESERVEDR0hReserved
11INSTRUCTION_TIMEOUTR-0/W1C0hInstruction timeout error flag clear register
0 - No action
1 - clear Instruction timeout flag

Reset type: PORESETn

10ILLEGAL_INSTRUCTIONR-0/W1C0hIllegal instruction error flag clear register
0 - No action
1 - Illegal instruction error flag

Reset type: PORESETn

9SW_BREAKPOINT_ERRR-0/W1C0hSoftware brakepoint error flag clear register
0 - No action
1 - clear Software brakepoint error flag

Reset type: PORESETn

8WARN_PSP_ERRR-0/W1C0hWARN PSP violation flag clear register
0 - No action
1 - Clear WARN PSP violation flag

Reset type: PORESETn

7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3MAX_PSP_ERRR-0/W1C0hMAX PSP violation flag clear register
0 - No action
1 - Clear MAX PSP violation flag

Reset type: PORESETn

2SEC_EXIT_VIOR-0/W1C0hSecure exit violation flag clear register
0 - No action
1 - Clear Secure exit violation flag

Reset type: PORESETn

1SEC_ENTRY_VIOR-0/W1C0hSecure entry violation flag clear register
0 - No action
1 - Clear Secure entry violation flag

Reset type: PORESETn

0INSTR_SECURITY_VIOR-0/W1C0hInstruction packet security violation flag clear register
0 - No action
1 - Clear Instruction packet security violation flag

Reset type: PORESETn

8.9.3.6 CPU1_PR_PC Register (Offset = 14h) [Reset = 00000000h]

CPU1_PR_PC is shown in Figure 8-14 and described in Table 8-31.

Return to the Summary Table.

CPU1 PR Error aggregator Register to store PC value at the first High priority error event

Figure 8-14 CPU1_PR_PC Register
313029282726252423222120191817161514131211109876543210
CPU1_PR_PC
R-0h
Table 8-31 CPU1_PR_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_PR_PCR0hCPPU1 PC at which first High priority error occurred on CPU1_PR access

Reset type: PORESETn

8.9.3.7 CPU1_DR1_HIGHPRIO_ERROR_ADDRESS Register (Offset = 40h) [Reset = 00000000h]

CPU1_DR1_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-15 and described in Table 8-32.

Return to the Summary Table.

CPU1 DR1 Error aggregator High Priority Error address register

Figure 8-15 CPU1_DR1_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU1_DR1_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-32 CPU1_DR1_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_DR1_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU1_DR1 access

Reset type: PORESETn

8.9.3.8 CPU1_DR1_LOWPRIO_ERROR_ADDRESS Register (Offset = 44h) [Reset = 00000000h]

CPU1_DR1_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-16 and described in Table 8-33.

Return to the Summary Table.

CPU1 DR1 Error aggregator Low Priority Error address register

Figure 8-16 CPU1_DR1_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU1_DR1_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-33 CPU1_DR1_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_DR1_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU1_DR1 access

Reset type: PORESETn

8.9.3.9 CPU1_DR1_ERROR_TYPE Register (Offset = 48h) [Reset = 00000000h]

CPU1_DR1_ERROR_TYPE is shown in Figure 8-17 and described in Table 8-34.

Return to the Summary Table.

CPU1 DR1 Error aggregator Error Type Register

Figure 8-17 CPU1_DR1_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-34 CPU1_DR1_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority high priority error set by software

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR0hUnaligned address error

Reset type: PORESETn

7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0hUncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0hAccess timeout error

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR0hSecurity violation

Reset type: PORESETn

8.9.3.10 CPU1_DR1_ERROR_TYPE_FRC Register (Offset = 4Ch) [Reset = 00000000h]

CPU1_DR1_ERROR_TYPE_FRC is shown in Figure 8-18 and described in Table 8-35.

Return to the Summary Table.

CPU1 DR1 Error aggregator Error Type Force Register

Figure 8-18 CPU1_DR1_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1S-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0h
Table 8-35 CPU1_DR1_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1S0hUnaligned address error flag force register
0 - No action
1 - force Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1S0hSecurity violation flag force register
0 - No action
1 - force Security violation flag

Reset type: PORESETn

8.9.3.11 CPU1_DR1_ERROR_TYPE_CLR Register (Offset = 50h) [Reset = 00000000h]

CPU1_DR1_ERROR_TYPE_CLR is shown in Figure 8-19 and described in Table 8-36.

Return to the Summary Table.

CPU1 DR1 Error aggregator Error Type Clear Register

Figure 8-19 CPU1_DR1_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1C-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0hR-0/W1C-0h
Table 8-36 CPU1_DR1_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1C0hUnaligned address error flag clear register
0 - No action
1 - Clear Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1C0hSecurity violation flag clear register
0 - No action
1 - Clear Security violation flag

Reset type: PORESETn

8.9.3.12 CPU1_DR1_PC Register (Offset = 54h) [Reset = 00000000h]

CPU1_DR1_PC is shown in Figure 8-20 and described in Table 8-37.

Return to the Summary Table.

CPU1 DR1 Error aggregator Register to store PC value at the first High priority error event

Figure 8-20 CPU1_DR1_PC Register
313029282726252423222120191817161514131211109876543210
CPU1_DR1_PC
R-0h
Table 8-37 CPU1_DR1_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_DR1_PCR0hCPU1 PC at which first High priority error occurred on CPU1_DR1 access

Reset type: PORESETn

8.9.3.13 CPU1_DR2_HIGHPRIO_ERROR_ADDRESS Register (Offset = 80h) [Reset = 00000000h]

CPU1_DR2_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-21 and described in Table 8-38.

Return to the Summary Table.

CPU1 DR2 Error aggregator High Priority Error address register

Figure 8-21 CPU1_DR2_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU1_DR2_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-38 CPU1_DR2_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_DR2_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU1_DR2 access

Reset type: PORESETn

8.9.3.14 CPU1_DR2_LOWPRIO_ERROR_ADDRESS Register (Offset = 84h) [Reset = 00000000h]

CPU1_DR2_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-22 and described in Table 8-39.

Return to the Summary Table.

CPU1 DR2 Error aggregator Low Priority Error address register

Figure 8-22 CPU1_DR2_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU1_DR2_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-39 CPU1_DR2_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_DR2_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU1_DR2 access

Reset type: PORESETn

8.9.3.15 CPU1_DR2_ERROR_TYPE Register (Offset = 88h) [Reset = 00000000h]

CPU1_DR2_ERROR_TYPE is shown in Figure 8-23 and described in Table 8-40.

Return to the Summary Table.

CPU1 DR2 Error aggregator Error Type Register

Figure 8-23 CPU1_DR2_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-40 CPU1_DR2_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority error set by software

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR0hUnaligned address error

Reset type: PORESETn

7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0hUncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0hAccess timeout error

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR0hSecurity violation

Reset type: PORESETn

8.9.3.16 CPU1_DR2_ERROR_TYPE_FRC Register (Offset = 8Ch) [Reset = 00000000h]

CPU1_DR2_ERROR_TYPE_FRC is shown in Figure 8-24 and described in Table 8-41.

Return to the Summary Table.

CPU1 DR2 Error aggregator Error Type Force Register

Figure 8-24 CPU1_DR2_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1S-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0h
Table 8-41 CPU1_DR2_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1S0hUnaligned address error flag force register
0 - No action
1 - force Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1S0hSecurity violation flag force register
0 - No action
1 - force Security violation flag

Reset type: PORESETn

8.9.3.17 CPU1_DR2_ERROR_TYPE_CLR Register (Offset = 90h) [Reset = 00000000h]

CPU1_DR2_ERROR_TYPE_CLR is shown in Figure 8-25 and described in Table 8-42.

Return to the Summary Table.

CPU1 DR2 Error aggregator Error Type Clear Register

Figure 8-25 CPU1_DR2_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1C-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0hR-0/W1C-0h
Table 8-42 CPU1_DR2_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1C0hUnaligned address error flag clear register
0 - No action
1 - Clear Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1C0hSecurity violation flag clear register
0 - No action
1 - Clear Security violation flag

Reset type: PORESETn

8.9.3.18 CPU1_DR2_PC Register (Offset = 94h) [Reset = 00000000h]

CPU1_DR2_PC is shown in Figure 8-26 and described in Table 8-43.

Return to the Summary Table.

CPU1 DR2 Error aggregator Register to store PC value at the first High priority error event

Figure 8-26 CPU1_DR2_PC Register
313029282726252423222120191817161514131211109876543210
CPU1_DR2_PC
R-0h
Table 8-43 CPU1_DR2_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_DR2_PCR0hCPU1 PC at which first High priority error occurred on CPU1_DR2 access

Reset type: PORESETn

8.9.3.19 CPU1_DW_HIGHPRIO_ERROR_ADDRESS Register (Offset = C0h) [Reset = 00000000h]

CPU1_DW_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-27 and described in Table 8-44.

Return to the Summary Table.

CPU1 DW Error aggregator High Priority Error address register

Figure 8-27 CPU1_DW_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU1_DW_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-44 CPU1_DW_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_DW_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU1_DW access

Reset type: PORESETn

8.9.3.20 CPU1_DW_LOWPRIO_ERROR_ADDRESS Register (Offset = C4h) [Reset = 00000000h]

CPU1_DW_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-28 and described in Table 8-45.

Return to the Summary Table.

CPU1 DW Error aggregator Low Priority Error address register

Figure 8-28 CPU1_DW_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU1_DW_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-45 CPU1_DW_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_DW_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU1_DW access

Reset type: PORESETn

8.9.3.21 CPU1_DW_ERROR_TYPE Register (Offset = C8h) [Reset = 00000000h]

CPU1_DW_ERROR_TYPE is shown in Figure 8-29 and described in Table 8-46.

Return to the Summary Table.

CPU1 DW Error aggregator Error Type Register

Figure 8-29 CPU1_DW_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-46 CPU1_DW_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority error set by software

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR0hUnaligned address error

Reset type: PORESETn

7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0hUncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0hAccess timeout error

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR0hSecurity violation

Reset type: PORESETn

8.9.3.22 CPU1_DW_ERROR_TYPE_FRC Register (Offset = CCh) [Reset = 00000000h]

CPU1_DW_ERROR_TYPE_FRC is shown in Figure 8-30 and described in Table 8-47.

Return to the Summary Table.

CPU1 DW Error aggregator Error Type Force Register

Figure 8-30 CPU1_DW_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1S-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0h
Table 8-47 CPU1_DW_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1S0hUnaligned address error flag force register
0 - No action
1 - force Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1S0hSecurity violation flag force register
0 - No action
1 - force Security violation flag

Reset type: PORESETn

8.9.3.23 CPU1_DW_ERROR_TYPE_CLR Register (Offset = D0h) [Reset = 00000000h]

CPU1_DW_ERROR_TYPE_CLR is shown in Figure 8-31 and described in Table 8-48.

Return to the Summary Table.

CPU1 DW Error aggregator Error Type Clear Register

Figure 8-31 CPU1_DW_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1C-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0hR-0/W1C-0h
Table 8-48 CPU1_DW_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1C0hUnaligned address error flag clear register
0 - No action
1 - Clear Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1C0hSecurity violation flag clear register
0 - No action
1 - Clear Security violation flag

Reset type: PORESETn

8.9.3.24 CPU1_DW_PC Register (Offset = D4h) [Reset = 00000000h]

CPU1_DW_PC is shown in Figure 8-32 and described in Table 8-49.

Return to the Summary Table.

CPU1 DW Error aggregator Register to store PC value at the first High priority error event

Figure 8-32 CPU1_DW_PC Register
313029282726252423222120191817161514131211109876543210
CPU1_DW_PC
R-0h
Table 8-49 CPU1_DW_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_DW_PCR0hCPU1 PC at which first High priority error occurred on CPU1_DW access

Reset type: PORESETn

8.9.3.25 CPU1_INT_HIGHPRIO_ERROR_ADDRESS Register (Offset = 100h) [Reset = 00000000h]

CPU1_INT_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-33 and described in Table 8-50.

Return to the Summary Table.

CPU1 INT Error aggregator High Priority Error address register

Figure 8-33 CPU1_INT_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU1_INT_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-50 CPU1_INT_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_INT_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU1_INT

Reset type: PORESETn

8.9.3.26 CPU1_INT_LOWPRIO_ERROR_ADDRESS Register (Offset = 104h) [Reset = 00000000h]

CPU1_INT_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-34 and described in Table 8-51.

Return to the Summary Table.

CPU1 INT Error aggregator Low Priority Error address register

Figure 8-34 CPU1_INT_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU1_INT_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-51 CPU1_INT_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_INT_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU1_INT

Reset type: PORESETn

8.9.3.27 CPU1_INT_ERROR_TYPE Register (Offset = 108h) [Reset = 00000000h]

CPU1_INT_ERROR_TYPE is shown in Figure 8-35 and described in Table 8-52.

Return to the Summary Table.

CPU1 INT Error aggregator Error Type Register

Figure 8-35 CPU1_INT_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRPIPE_LOCK_KEY_ERRREG_PARITY_DIAG_ERRREG_PARITY_ERRPIPE_SECURITY_VIOMAXISPWARNISP
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
VECT_UNCERRVECT_CERRNMI_CONTEXT_RESTORE_VECT_UNCERRNMI_CONTEXT_RESTORE_VECT_CERRNMI_INTERRUPT_RETURN_ERRNMI_VECT_UNCERRNMI_VECT_CERRNMI_ISR_ENTRY_ERR
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
NMI_MAXISP_ERRRESERVEDRTINT_CONTEXT_RESTORE_VECT_UNCERRRTINT_CONTEXT_RESTORE_VECT_CERRRTINT_INTERRUPT_RETURN_ERRRTINT_VECT_UNCERRRTINT_VECT_CERRRTINT_ISR_ENTRY_ERR
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
INT_INTERRUPT_RETURN_ERRINT_VECT_UNCERRINT_VECT_CERRINT_ISR_ENTRY_ERRMAIN_INTERRUPT_RETURN_ERRMAIN_VECT_UNCERRMAIN_VECT_CERRMAIN_ISR_ENTRY_ERR
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-52 CPU1_INT_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority error set by software

Reset type: PORESETn

29PIPE_LOCK_KEY_ERRR0hPIPE Lock/key error

Reset type: PORESETn

28REG_PARITY_DIAG_ERRR0hPIPE Register parity diag error

Reset type: PORESETn

27REG_PARITY_ERRR0hPIPE Reg parity error

Reset type: PORESETn

26PIPE_SECURITY_VIOR0hPIPE security violation

Reset type: PORESETn

25MAXISPR0hmaxisp

Reset type: PORESETn

24WARNISPR0hwarnisp

Reset type: PORESETn

23VECT_UNCERRR0hVector Uncorrectable error generated by PIPE on software read of vector register having uncorrectable error

Reset type: PORESETn

22VECT_CERRR0hVector Correctable error generated by PIPE on software read of vector register having correctable error

Reset type: PORESETn

21NMI_CONTEXT_RESTORE_VECT_UNCERRR0hNMI Context restore Uncorrectable vector error

Reset type: PORESETn

20NMI_CONTEXT_RESTORE_VECT_CERRR0hNMI Context restore Correctable vector error

Reset type: PORESETn

19NMI_INTERRUPT_RETURN_ERRR0hNMI Interrupt return error

Reset type: PORESETn

18NMI_VECT_UNCERRR0hNMI Uncorrectable vector error

Reset type: PORESETn

17NMI_VECT_CERRR0hNMI Correctable vector error

Reset type: PORESETn

16NMI_ISR_ENTRY_ERRR0hNMI ISR entry error

Reset type: PORESETn

15NMI_MAXISP_ERRR0hNMI MAXISP error

Reset type: PORESETn

14RESERVEDR0hReserved
13RTINT_CONTEXT_RESTORE_VECT_UNCERRR0hRTINT Context restore Uncorrectable vector error

Reset type: PORESETn

12RTINT_CONTEXT_RESTORE_VECT_CERRR0hRTINT Context restore Correctable vector error

Reset type: PORESETn

11RTINT_INTERRUPT_RETURN_ERRR0hRTINT Interrupt return error

Reset type: PORESETn

10RTINT_VECT_UNCERRR0hRTINT Uncorrectable vector error

Reset type: PORESETn

9RTINT_VECT_CERRR0hRTINT Correctable vector error

Reset type: PORESETn

8RTINT_ISR_ENTRY_ERRR0hRTINT ISR entry error

Reset type: PORESETn

7INT_INTERRUPT_RETURN_ERRR0hINT INTerrupt return error

Reset type: PORESETn

6INT_VECT_UNCERRR0hINT Uncorrectable vector error

Reset type: PORESETn

5INT_VECT_CERRR0hINT Correctable vector error

Reset type: PORESETn

4INT_ISR_ENTRY_ERRR0hINT ISR entry error

Reset type: PORESETn

3MAIN_INTERRUPT_RETURN_ERRR0hMain Interrupt return error

Reset type: PORESETn

2MAIN_VECT_UNCERRR0hMain Uncorrectable vector error

Reset type: PORESETn

1MAIN_VECT_CERRR0hMain Correctable vector error

Reset type: PORESETn

0MAIN_ISR_ENTRY_ERRR0hMain ISR entry error

Reset type: PORESETn

8.9.3.28 CPU1_INT_ERROR_TYPE_FRC Register (Offset = 10Ch) [Reset = 00000000h]

CPU1_INT_ERROR_TYPE_FRC is shown in Figure 8-36 and described in Table 8-53.

Return to the Summary Table.

CPU1 INT Error aggregator Error Type Force Register

Figure 8-36 CPU1_INT_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRPIPE_LOCK_KEY_ERRREG_PARITY_DIAG_ERRREG_PARITY_ERRPIPE_SECURITY_VIOMAXISPWARNISP
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
VECT_UNCERRVECT_CERRNMI_CONTEXT_RESTORE_VECT_UNCERRNMI_CONTEXT_RESTORE_VECT_CERRNMI_INTERRUPT_RETURN_ERRNMI_VECT_UNCERRNMI_VECT_CERRNMI_ISR_ENTRY_ERR
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
NMI_MAXISP_ERRRESERVEDRTINT_CONTEXT_RESTORE_VECT_UNCERRRTINT_CONTEXT_RESTORE_VECT_CERRRTINT_INTERRUPT_RETURN_ERRRTINT_VECT_UNCERRRTINT_VECT_CERRRTINT_ISR_ENTRY_ERR
R-0/W1S-0hR-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
INT_INTERRUPT_RETURN_ERRINT_VECT_UNCERRINT_VECT_CERRINT_ISR_ENTRY_ERRMAIN_INTERRUPT_RETURN_ERRMAIN_VECT_UNCERRMAIN_VECT_CERRMAIN_ISR_ENTRY_ERR
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 8-53 CPU1_INT_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29PIPE_LOCK_KEY_ERRR-0/W1S0hPIPE Lock key error force register
0 - No action
1 - force PIPE lock key error flag

Reset type: PORESETn

28REG_PARITY_DIAG_ERRR-0/W1S0hPIPE Register parity diag error force register
0 - No action
1 - force MAX PSP violation flag

Reset type: PORESETn

27REG_PARITY_ERRR-0/W1S0hPIPE Register parity error force register
0 - No action
1 - force PIPE Register parity errort error flag

Reset type: PORESETn

26PIPE_SECURITY_VIOR-0/W1S0hPIPE security violation force register
0 - No action
1 - force PIPE security violation flag

Reset type: PORESETn

25MAXISPR-0/W1S0hMaxisp error flag force register
0 - No action
1 - force Maxisp error flag

Reset type: PORESETn

24WARNISPR-0/W1S0hWarnisp error flag force register
0 - No action
1 - force Warnisp error flag

Reset type: PORESETn

23VECT_UNCERRR-0/W1S0hVector uncorrectable error force register
0 - No action
1 - force vector uncorrectable eror flag

Reset type: PORESETn

22VECT_CERRR-0/W1S0hVector correctable error force register
0 - No action
1 - force vector correctable error flag

Reset type: PORESETn

21NMI_CONTEXT_RESTORE_VECT_UNCERRR-0/W1S0hNMI Context restore Uncorrectable vector error flag force register
0 - No action
1 - force NMI Context restore Uncorrectable vector error flag

Reset type: PORESETn

20NMI_CONTEXT_RESTORE_VECT_CERRR-0/W1S0hNMI Context restore Correctable vector error flag force register
0 - No action
1 - force NMI Context restore Correctable vector error flag

Reset type: PORESETn

19NMI_INTERRUPT_RETURN_ERRR-0/W1S0hNMI Interrupt return error flag force register
0 - No action
1 - force NMI Interrupt return error flag

Reset type: PORESETn

18NMI_VECT_UNCERRR-0/W1S0hNMI uncorrectable vector error flag force register
0 - No action
1 - force NMI uncorrectable vector error flag

Reset type: PORESETn

17NMI_VECT_CERRR-0/W1S0hNMI Correctable vector error flag force register
0 - No action
1 - force NMI Correctable vector error flag

Reset type: PORESETn

16NMI_ISR_ENTRY_ERRR-0/W1S0hNMI ISR entry error flag force register
0 - No action
1 - NMI ISR entry error flag

Reset type: PORESETn

15NMI_MAXISP_ERRR-0/W1S0hNMI MAXISP error flag force register
0 - No action
1 - NMI MAXISP error flag

Reset type: PORESETn

14RESERVEDR0hReserved
13RTINT_CONTEXT_RESTORE_VECT_UNCERRR-0/W1S0hRTINT Context restore Uncorrectable vector error flag force register
0 - No action
1 - force RTINT Context restore Uncorrectable vector error flag

Reset type: PORESETn

12RTINT_CONTEXT_RESTORE_VECT_CERRR-0/W1S0hRTINT Context restore Correctable vector error flag force register
0 - No action
1 - force RTINT Context restore Correctable vector error flag

Reset type: PORESETn

11RTINT_INTERRUPT_RETURN_ERRR-0/W1S0hRTINT Interrupt return error flag force register
0 - No action
1 - force RTINT Interrupt return error flag

Reset type: PORESETn

10RTINT_VECT_UNCERRR-0/W1S0hRTINT uncorrectable vector error flag force register
0 - No action
1 - force RTINT uncorrectable vector error flag

Reset type: PORESETn

9RTINT_VECT_CERRR-0/W1S0hRTINT Correctable vector error flag force register
0 - No action
1 - force RTINT Correctable vector error flag

Reset type: PORESETn

8RTINT_ISR_ENTRY_ERRR-0/W1S0hRTINT ISR entry error flag force register
0 - No action
1 - RTINT ISR entry error flag

Reset type: PORESETn

7INT_INTERRUPT_RETURN_ERRR-0/W1S0hINT Interrupt return error flag force register
0 - No action
1 - force INT Interrupt return error flag

Reset type: PORESETn

6INT_VECT_UNCERRR-0/W1S0hINT uncorrectable vector error flag force register
0 - No action
1 - force INT uncorrectable vector error flag

Reset type: PORESETn

5INT_VECT_CERRR-0/W1S0hINT Correctable vector error flag force register
0 - No action
1 - force INT Correctable vector error flag

Reset type: PORESETn

4INT_ISR_ENTRY_ERRR-0/W1S0hINT ISR entry error flag force register
0 - No action
1 - INT ISR entry error flag

Reset type: PORESETn

3MAIN_INTERRUPT_RETURN_ERRR-0/W1S0hMain Interrupt return error flag force register
0 - No action
1 - force Main Interrupt return error flag

Reset type: PORESETn

2MAIN_VECT_UNCERRR-0/W1S0hMain uncorrectable vector error flag force register
0 - No action
1 - force Main uncorrectable vector error flag

Reset type: PORESETn

1MAIN_VECT_CERRR-0/W1S0hMain Correctable vector error flag force register
0 - No action
1 - force Main Correctable vector error flag

Reset type: PORESETn

0MAIN_ISR_ENTRY_ERRR-0/W1S0hMain ISR entry error flag force register
0 - No action
1 - Main ISR entry error flag

Reset type: PORESETn

8.9.3.29 CPU1_INT_ERROR_TYPE_CLR Register (Offset = 110h) [Reset = 00000000h]

CPU1_INT_ERROR_TYPE_CLR is shown in Figure 8-37 and described in Table 8-54.

Return to the Summary Table.

CPU1 INT Error aggregator Error Type Clear Register

Figure 8-37 CPU1_INT_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRPIPE_LOCK_KEY_ERRREG_PARITY_DIAG_ERRREG_PARITY_ERRPIPE_SECURITY_VIOMAXISPWARNISP
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
2322212019181716
VECT_UNCERRVECT_CERRNMI_CONTEXT_RESTORE_VECT_UNCERRNMI_CONTEXT_RESTORE_VECT_CERRNMI_INTERRUPT_RETURN_ERRNMI_VECT_UNCERRNMI_VECT_CERRNMI_ISR_ENTRY_ERR
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
15141312111098
NMI_MAXISP_ERRRESERVEDRTINT_CONTEXT_RESTORE_VECT_UNCERRRTINT_CONTEXT_RESTORE_VECT_CERRRTINT_INTERRUPT_RETURN_ERRRTINT_VECT_UNCERRRTINT_VECT_CERRRTINT_ISR_ENTRY_ERR
R-0/W1C-0hR-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
76543210
INT_INTERRUPT_RETURN_ERRINT_VECT_UNCERRINT_VECT_CERRINT_ISR_ENTRY_ERRMAIN_INTERRUPT_RETURN_ERRMAIN_VECT_UNCERRMAIN_VECT_CERRMAIN_ISR_ENTRY_ERR
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 8-54 CPU1_INT_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29PIPE_LOCK_KEY_ERRR-0/W1C0hPIPE Lock key error clear register
0 - No action
1 - clear PIPE lock key error flag

Reset type: PORESETn

28REG_PARITY_DIAG_ERRR-0/W1C0hPIPE Register parity diag error clear register
0 - No action
1 - clear MAX PSP violation flag

Reset type: PORESETn

27REG_PARITY_ERRR-0/W1C0hPIPE Register parity error clear register
0 - No action
1 - clear PIPE Register parity errort error flag

Reset type: PORESETn

26PIPE_SECURITY_VIOR-0/W1C0hPIPE security violation clear register
0 - No action
1 - clear PIPE security violation flag

Reset type: PORESETn

25MAXISPR-0/W1C0hMaxisp error flag clear register
0 - No action
1 - Clear Maxisp error flag

Reset type: PORESETn

24WARNISPR-0/W1C0hWarnisp error flag clear register
0 - No action
1 - Clear Warnisp error flag

Reset type: PORESETn

23VECT_UNCERRR-0/W1C0hVector uncorrectable error clear register
0 - No action
1 - Clear vector uncorrectable error flag

Reset type: PORESETn

22VECT_CERRR-0/W1C0hVector correctable error clear register
0 - No action
1 - Clear vector correctable error flag

Reset type: PORESETn

21NMI_CONTEXT_RESTORE_VECT_UNCERRR-0/W1C0hNMI Context restore Uncorrectable vector error flag clear register
0 - No action
1 - clear NMI Context restore Uncorrectable vector error flag

Reset type: PORESETn

20NMI_CONTEXT_RESTORE_VECT_CERRR-0/W1C0hNMI Context restore Correctable vector error flag clear register
0 - No action
1 - clear NMI Context restore Correctable vector error flag

Reset type: PORESETn

19NMI_INTERRUPT_RETURN_ERRR-0/W1C0hNMI Interrupt return error flag clear register
0 - No action
1 - clear NMI Interrupt return error flag

Reset type: PORESETn

18NMI_VECT_UNCERRR-0/W1C0hNMI uncorrectable vector error flag clear register
0 - No action
1 - clear NMI uncorrectable vector error flag

Reset type: PORESETn

17NMI_VECT_CERRR-0/W1C0hNMI Correctable vector error flag clear register
0 - No action
1 - clear NMI Correctable vector error flag

Reset type: PORESETn

16NMI_ISR_ENTRY_ERRR-0/W1C0hNMI ISR entry error flag clear register
0 - No action
1 - NMI ISR entry error flag

Reset type: PORESETn

15NMI_MAXISP_ERRR-0/W1C0hNMI MAXISP error flag clear register
0 - No action
1 - NMI MAXISP error flag

Reset type: PORESETn

14RESERVEDR0hReserved
13RTINT_CONTEXT_RESTORE_VECT_UNCERRR-0/W1C0hRTINT Context restore Uncorrectable vector error flag clear register
0 - No action
1 - clear RTINT Context restore Uncorrectable vector error flag

Reset type: PORESETn

12RTINT_CONTEXT_RESTORE_VECT_CERRR-0/W1C0hRTINT Context restore Correctable vector error flag clear register
0 - No action
1 - clear RTINT Context restore Correctable vector error flag

Reset type: PORESETn

11RTINT_INTERRUPT_RETURN_ERRR-0/W1C0hRTINT Interrupt return error flag clear register
0 - No action
1 - clear RTINT Interrupt return error flag

Reset type: PORESETn

10RTINT_VECT_UNCERRR-0/W1C0hRTINT uncorrectable vector error flag clear register
0 - No action
1 - clear RTINT uncorrectable vector error flag

Reset type: PORESETn

9RTINT_VECT_CERRR-0/W1C0hRTINT Correctable vector error flag clear register
0 - No action
1 - clear RTINT Correctable vector error flag

Reset type: PORESETn

8RTINT_ISR_ENTRY_ERRR-0/W1C0hRTINT ISR entry error flag clear register
0 - No action
1 - RTINT ISR entry error flag

Reset type: PORESETn

7INT_INTERRUPT_RETURN_ERRR-0/W1C0hINT Interrupt return error flag clear register
0 - No action
1 - clear INT Interrupt return error flag

Reset type: PORESETn

6INT_VECT_UNCERRR-0/W1C0hINT uncorrectable vector error flag clear register
0 - No action
1 - clear INT uncorrectable vector error flag

Reset type: PORESETn

5INT_VECT_CERRR-0/W1C0hINT Correctable vector error flag clear register
0 - No action
1 - clear INT Correctable vector error flag

Reset type: PORESETn

4INT_ISR_ENTRY_ERRR-0/W1C0hINT ISR entry error flag clear register
0 - No action
1 - INT ISR entry error flag

Reset type: PORESETn

3MAIN_INTERRUPT_RETURN_ERRR-0/W1C0hMain Interrupt return error flag clear register
0 - No action
1 - clear Main Interrupt return error flag

Reset type: PORESETn

2MAIN_VECT_UNCERRR-0/W1C0hMain uncorrectable vector error flag clear register
0 - No action
1 - clear Main uncorrectable vector error flag

Reset type: PORESETn

1MAIN_VECT_CERRR-0/W1C0hMain Correctable vector error flag clear register
0 - No action
1 - clear Main Correctable vector error flag

Reset type: PORESETn

0MAIN_ISR_ENTRY_ERRR-0/W1C0hMain ISR entry error flag clear register
0 - No action
1 - Main ISR entry error flag

Reset type: PORESETn

8.9.3.30 CPU1_INT_PC Register (Offset = 114h) [Reset = 00000000h]

CPU1_INT_PC is shown in Figure 8-38 and described in Table 8-55.

Return to the Summary Table.

CPU1 INT Error aggregator Register to store PC value at the first High priority error event

Figure 8-38 CPU1_INT_PC Register
313029282726252423222120191817161514131211109876543210
CPU1_INT_PC
R-0h
Table 8-55 CPU1_INT_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU1_INT_PCR0hCPU1 PC at which first High priority error occurred on CPU1_INT

Reset type: PORESETn

8.9.3.31 CPU2_PR_HIGHPRIO_ERROR_ADDRESS Register (Offset = 140h) [Reset = 00000000h]

CPU2_PR_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-39 and described in Table 8-56.

Return to the Summary Table.

CPU2 PR Error aggregator High Priority Error address register

Figure 8-39 CPU2_PR_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU2_PR_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-56 CPU2_PR_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_PR_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU2_PR access

Reset type: PORESETn

8.9.3.32 CPU2_PR_LOWPRIO_ERROR_ADDRESS Register (Offset = 144h) [Reset = 00000000h]

CPU2_PR_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-40 and described in Table 8-57.

Return to the Summary Table.

CPU2 PR Error aggregator Low Priority Error address register

Figure 8-40 CPU2_PR_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU2_PR_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-57 CPU2_PR_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_PR_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU2_PR access

Reset type: PORESETn

8.9.3.33 CPU2_PR_ERROR_TYPE Register (Offset = 148h) [Reset = 00000000h]

CPU2_PR_ERROR_TYPE is shown in Figure 8-41 and described in Table 8-58.

Return to the Summary Table.

CPU2 PR Error aggregator Error Type Register

Figure 8-41 CPU2_PR_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDINSTRUCTION_TIMEOUTILLEGAL_INSTRUCTIONSW_BREAKPOINT_ERRWARN_PSP_ERR
R-0hR-0hR-0hR-0hR-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRMAX_PSP_ERRSEC_EXIT_VIOSEC_ENTRY_VIOINSTR_SECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-58 CPU2_PR_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority set by software

Reset type: PORESETn

29-12RESERVEDR0hReserved
11INSTRUCTION_TIMEOUTR0hInstruction timeout error

Reset type: PORESETn

10ILLEGAL_INSTRUCTIONR0hIllegal instruction error

Reset type: PORESETn

9SW_BREAKPOINT_ERRR0hSoftware brakepoint error

Reset type: PORESETn

8WARN_PSP_ERRR0hWarn PSP error

Reset type: PORESETn

7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0h Uncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0h Access timeout error

Reset type: PORESETn

3MAX_PSP_ERRR0h MAX PSP error

Reset type: PORESETn

2SEC_EXIT_VIOR0hSecure exit error

Reset type: PORESETn

1SEC_ENTRY_VIOR0hSecure entry and linear code crossing LINK, STACK, ZONE error.

Reset type: PORESETn

0INSTR_SECURITY_VIOR0hInstruction packet security violation. Instruction packet crossed LINK, STACK, ZONE boundary.

Reset type: PORESETn

8.9.3.34 CPU2_PR_ERROR_TYPE_FRC Register (Offset = 14Ch) [Reset = 00000000h]

CPU2_PR_ERROR_TYPE_FRC is shown in Figure 8-42 and described in Table 8-59.

Return to the Summary Table.

CPU2 PR Error aggregator Error Type Force Register

Figure 8-42 CPU2_PR_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDINSTRUCTION_TIMEOUTILLEGAL_INSTRUCTIONSW_BREAKPOINT_ERRWARN_PSP_ERR
R-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRMAX_PSP_ERRSEC_EXIT_VIOSEC_ENTRY_VIOINSTR_SECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 8-59 CPU2_PR_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hForce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-12RESERVEDR0hReserved
11INSTRUCTION_TIMEOUTR-0/W1S0hInstruction timeout error flag force register
0 - No action
1 - force Instruction timeout flag

Reset type: PORESETn

10ILLEGAL_INSTRUCTIONR-0/W1S0hIllegal instruction error flag force register
0 - No action
1 - Illegal instruction error flag

Reset type: PORESETn

9SW_BREAKPOINT_ERRR-0/W1S0hSoftware brakepoint error flag force register
0 - No action
1 - force Software brakepoint error flag

Reset type: PORESETn

8WARN_PSP_ERRR-0/W1S0hWARN PSP violation flag force register
0 - No action
1 - force WARN PSP violation flag

Reset type: PORESETn

7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3MAX_PSP_ERRR-0/W1S0hMAX PSP violation flag force register
0 - No action
1 - force MAX PSP violation flag

Reset type: PORESETn

2SEC_EXIT_VIOR-0/W1S0hSecure exit violation flag force register
0 - No action
1 - force Secure exit violation flag

Reset type: PORESETn

1SEC_ENTRY_VIOR-0/W1S0hSecure entry violation flag force register
0 - No action
1 - force Secure entry violation flag

Reset type: PORESETn

0INSTR_SECURITY_VIOR-0/W1S0hInstruction packet security violation flag force register
0 - No action
1 - force Instruction packet security violation flag

Reset type: PORESETn

8.9.3.35 CPU2_PR_ERROR_TYPE_CLR Register (Offset = 150h) [Reset = 00000000h]

CPU2_PR_ERROR_TYPE_CLR is shown in Figure 8-43 and described in Table 8-60.

Return to the Summary Table.

CPU2 PR Error aggregator Error Type Clear Register

Figure 8-43 CPU2_PR_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDINSTRUCTION_TIMEOUTILLEGAL_INSTRUCTIONSW_BREAKPOINT_ERRWARN_PSP_ERR
R-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRMAX_PSP_ERRSEC_EXIT_VIOSEC_ENTRY_VIOINSTR_SECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 8-60 CPU2_PR_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-12RESERVEDR0hReserved
11INSTRUCTION_TIMEOUTR-0/W1C0hInstruction timeout error flag clear register
0 - No action
1 - clear Instruction timeout flag

Reset type: PORESETn

10ILLEGAL_INSTRUCTIONR-0/W1C0hIllegal instruction error flag clear register
0 - No action
1 - Illegal instruction error flag

Reset type: PORESETn

9SW_BREAKPOINT_ERRR-0/W1C0hSoftware brakepoint error flag clear register
0 - No action
1 - clear Software brakepoint error flag

Reset type: PORESETn

8WARN_PSP_ERRR-0/W1C0hWARN PSP violation flag clear register
0 - No action
1 - Clear WARN PSP violation flag

Reset type: PORESETn

7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3MAX_PSP_ERRR-0/W1C0hMAX PSP violation flag clear register
0 - No action
1 - Clear MAX PSP violation flag

Reset type: PORESETn

2SEC_EXIT_VIOR-0/W1C0hSecure exit violation flag clear register
0 - No action
1 - Clear Secure exit violation flag

Reset type: PORESETn

1SEC_ENTRY_VIOR-0/W1C0hSecure entry violation flag clear register
0 - No action
1 - Clear Secure entry violation flag

Reset type: PORESETn

0INSTR_SECURITY_VIOR-0/W1C0hInstruction packet security violation flag clear register
0 - No action
1 - Clear Instruction packet security violation flag

Reset type: PORESETn

8.9.3.36 CPU2_PR_PC Register (Offset = 154h) [Reset = 00000000h]

CPU2_PR_PC is shown in Figure 8-44 and described in Table 8-61.

Return to the Summary Table.

CPU2 PR Error aggregator Register to store PC value at the first High priority error event

Figure 8-44 CPU2_PR_PC Register
313029282726252423222120191817161514131211109876543210
CPU2_PR_PC
R-0h
Table 8-61 CPU2_PR_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_PR_PCR0hCPPU2 PC at which first High priority error occurred on CPU2_PR access

Reset type: PORESETn

8.9.3.37 CPU2_DR1_HIGHPRIO_ERROR_ADDRESS Register (Offset = 180h) [Reset = 00000000h]

CPU2_DR1_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-45 and described in Table 8-62.

Return to the Summary Table.

CPU2 DR1 Error aggregator High Priority Error address register

Figure 8-45 CPU2_DR1_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU2_DR1_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-62 CPU2_DR1_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_DR1_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU2_DR1 access

Reset type: PORESETn

8.9.3.38 CPU2_DR1_LOWPRIO_ERROR_ADDRESS Register (Offset = 184h) [Reset = 00000000h]

CPU2_DR1_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-46 and described in Table 8-63.

Return to the Summary Table.

CPU2 DR1 Error aggregator Low Priority Error address register

Figure 8-46 CPU2_DR1_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU2_DR1_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-63 CPU2_DR1_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_DR1_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU2_DR1 access

Reset type: PORESETn

8.9.3.39 CPU2_DR1_ERROR_TYPE Register (Offset = 188h) [Reset = 00000000h]

CPU2_DR1_ERROR_TYPE is shown in Figure 8-47 and described in Table 8-64.

Return to the Summary Table.

CPU2 DR1 Error aggregator Error Type Register

Figure 8-47 CPU2_DR1_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-64 CPU2_DR1_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority high priority error set by software

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR0hUnaligned address error

Reset type: PORESETn

7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0hUncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0hAccess timeout error

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR0hSecurity violation

Reset type: PORESETn

8.9.3.40 CPU2_DR1_ERROR_TYPE_FRC Register (Offset = 18Ch) [Reset = 00000000h]

CPU2_DR1_ERROR_TYPE_FRC is shown in Figure 8-48 and described in Table 8-65.

Return to the Summary Table.

CPU2 DR1 Error aggregator Error Type Force Register

Figure 8-48 CPU2_DR1_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1S-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0h
Table 8-65 CPU2_DR1_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1S0hUnaligned address error flag force register
0 - No action
1 - force Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1S0hSecurity violation flag force register
0 - No action
1 - force Security violation flag

Reset type: PORESETn

8.9.3.41 CPU2_DR1_ERROR_TYPE_CLR Register (Offset = 190h) [Reset = 00000000h]

CPU2_DR1_ERROR_TYPE_CLR is shown in Figure 8-49 and described in Table 8-66.

Return to the Summary Table.

CPU2 DR1 Error aggregator Error Type Clear Register

Figure 8-49 CPU2_DR1_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1C-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0hR-0/W1C-0h
Table 8-66 CPU2_DR1_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1C0hUnaligned address error flag clear register
0 - No action
1 - Clear Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1C0hSecurity violation flag clear register
0 - No action
1 - Clear Security violation flag

Reset type: PORESETn

8.9.3.42 CPU2_DR1_PC Register (Offset = 194h) [Reset = 00000000h]

CPU2_DR1_PC is shown in Figure 8-50 and described in Table 8-67.

Return to the Summary Table.

CPU2 DR1 Error aggregator Register to store PC value at the first High priority error event

Figure 8-50 CPU2_DR1_PC Register
313029282726252423222120191817161514131211109876543210
CPU2_DR1_PC
R-0h
Table 8-67 CPU2_DR1_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_DR1_PCR0hCPU2 PC at which first High priority error occurred on CPU2_DR1 access

Reset type: PORESETn

8.9.3.43 CPU2_DR2_HIGHPRIO_ERROR_ADDRESS Register (Offset = 1C0h) [Reset = 00000000h]

CPU2_DR2_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-51 and described in Table 8-68.

Return to the Summary Table.

CPU2 DR2 Error aggregator High Priority Error address register

Figure 8-51 CPU2_DR2_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU2_DR2_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-68 CPU2_DR2_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_DR2_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU2_DR2 access

Reset type: PORESETn

8.9.3.44 CPU2_DR2_LOWPRIO_ERROR_ADDRESS Register (Offset = 1C4h) [Reset = 00000000h]

CPU2_DR2_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-52 and described in Table 8-69.

Return to the Summary Table.

CPU2 DR2 Error aggregator Low Priority Error address register

Figure 8-52 CPU2_DR2_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU2_DR2_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-69 CPU2_DR2_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_DR2_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU2_DR2 access

Reset type: PORESETn

8.9.3.45 CPU2_DR2_ERROR_TYPE Register (Offset = 1C8h) [Reset = 00000000h]

CPU2_DR2_ERROR_TYPE is shown in Figure 8-53 and described in Table 8-70.

Return to the Summary Table.

CPU2 DR2 Error aggregator Error Type Register

Figure 8-53 CPU2_DR2_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-70 CPU2_DR2_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority error set by software

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR0hUnaligned address error

Reset type: PORESETn

7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0hUncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0hAccess timeout error

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR0hSecurity violation

Reset type: PORESETn

8.9.3.46 CPU2_DR2_ERROR_TYPE_FRC Register (Offset = 1CCh) [Reset = 00000000h]

CPU2_DR2_ERROR_TYPE_FRC is shown in Figure 8-54 and described in Table 8-71.

Return to the Summary Table.

CPU2 DR2 Error aggregator Error Type Force Register

Figure 8-54 CPU2_DR2_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1S-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0h
Table 8-71 CPU2_DR2_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1S0hUnaligned address error flag force register
0 - No action
1 - force Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1S0hSecurity violation flag force register
0 - No action
1 - force Security violation flag

Reset type: PORESETn

8.9.3.47 CPU2_DR2_ERROR_TYPE_CLR Register (Offset = 1D0h) [Reset = 00000000h]

CPU2_DR2_ERROR_TYPE_CLR is shown in Figure 8-55 and described in Table 8-72.

Return to the Summary Table.

CPU2 DR2 Error aggregator Error Type Clear Register

Figure 8-55 CPU2_DR2_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1C-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0hR-0/W1C-0h
Table 8-72 CPU2_DR2_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1C0hUnaligned address error flag clear register
0 - No action
1 - Clear Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1C0hSecurity violation flag clear register
0 - No action
1 - Clear Security violation flag

Reset type: PORESETn

8.9.3.48 CPU2_DR2_PC Register (Offset = 1D4h) [Reset = 00000000h]

CPU2_DR2_PC is shown in Figure 8-56 and described in Table 8-73.

Return to the Summary Table.

CPU2 DR2 Error aggregator Register to store PC value at the first High priority error event

Figure 8-56 CPU2_DR2_PC Register
313029282726252423222120191817161514131211109876543210
CPU2_DR2_PC
R-0h
Table 8-73 CPU2_DR2_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_DR2_PCR0hCPU2 PC at which first High priority error occurred on CPU2_DR2 access

Reset type: PORESETn

8.9.3.49 CPU2_DW_HIGHPRIO_ERROR_ADDRESS Register (Offset = 200h) [Reset = 00000000h]

CPU2_DW_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-57 and described in Table 8-74.

Return to the Summary Table.

CPU2 DW Error aggregator High Priority Error address register

Figure 8-57 CPU2_DW_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU2_DW_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-74 CPU2_DW_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_DW_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU2_DW access

Reset type: PORESETn

8.9.3.50 CPU2_DW_LOWPRIO_ERROR_ADDRESS Register (Offset = 204h) [Reset = 00000000h]

CPU2_DW_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-58 and described in Table 8-75.

Return to the Summary Table.

CPU2 DW Error aggregator Low Priority Error address register

Figure 8-58 CPU2_DW_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU2_DW_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-75 CPU2_DW_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_DW_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU2_DW access

Reset type: PORESETn

8.9.3.51 CPU2_DW_ERROR_TYPE Register (Offset = 208h) [Reset = 00000000h]

CPU2_DW_ERROR_TYPE is shown in Figure 8-59 and described in Table 8-76.

Return to the Summary Table.

CPU2 DW Error aggregator Error Type Register

Figure 8-59 CPU2_DW_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-76 CPU2_DW_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority error set by software

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR0hUnaligned address error

Reset type: PORESETn

7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0hUncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0hAccess timeout error

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR0hSecurity violation

Reset type: PORESETn

8.9.3.52 CPU2_DW_ERROR_TYPE_FRC Register (Offset = 20Ch) [Reset = 00000000h]

CPU2_DW_ERROR_TYPE_FRC is shown in Figure 8-60 and described in Table 8-77.

Return to the Summary Table.

CPU2 DW Error aggregator Error Type Force Register

Figure 8-60 CPU2_DW_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1S-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0h
Table 8-77 CPU2_DW_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1S0hUnaligned address error flag force register
0 - No action
1 - force Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1S0hSecurity violation flag force register
0 - No action
1 - force Security violation flag

Reset type: PORESETn

8.9.3.53 CPU2_DW_ERROR_TYPE_CLR Register (Offset = 210h) [Reset = 00000000h]

CPU2_DW_ERROR_TYPE_CLR is shown in Figure 8-61 and described in Table 8-78.

Return to the Summary Table.

CPU2 DW Error aggregator Error Type Clear Register

Figure 8-61 CPU2_DW_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1C-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0hR-0/W1C-0h
Table 8-78 CPU2_DW_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1C0hUnaligned address error flag clear register
0 - No action
1 - Clear Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1C0hSecurity violation flag clear register
0 - No action
1 - Clear Security violation flag

Reset type: PORESETn

8.9.3.54 CPU2_DW_PC Register (Offset = 214h) [Reset = 00000000h]

CPU2_DW_PC is shown in Figure 8-62 and described in Table 8-79.

Return to the Summary Table.

CPU2 DW Error aggregator Register to store PC value at the first High priority error event

Figure 8-62 CPU2_DW_PC Register
313029282726252423222120191817161514131211109876543210
CPU2_DW_PC
R-0h
Table 8-79 CPU2_DW_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_DW_PCR0hCPU2 PC at which first High priority error occurred on CPU2_DW access

Reset type: PORESETn

8.9.3.55 CPU2_INT_HIGHPRIO_ERROR_ADDRESS Register (Offset = 240h) [Reset = 00000000h]

CPU2_INT_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-63 and described in Table 8-80.

Return to the Summary Table.

CPU2 INT Error aggregator High Priority Error address register

Figure 8-63 CPU2_INT_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU2_INT_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-80 CPU2_INT_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_INT_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU2_INT

Reset type: PORESETn

8.9.3.56 CPU2_INT_LOWPRIO_ERROR_ADDRESS Register (Offset = 244h) [Reset = 00000000h]

CPU2_INT_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-64 and described in Table 8-81.

Return to the Summary Table.

CPU2 INT Error aggregator Low Priority Error address register

Figure 8-64 CPU2_INT_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU2_INT_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-81 CPU2_INT_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_INT_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU2_INT

Reset type: PORESETn

8.9.3.57 CPU2_INT_ERROR_TYPE Register (Offset = 248h) [Reset = 00000000h]

CPU2_INT_ERROR_TYPE is shown in Figure 8-65 and described in Table 8-82.

Return to the Summary Table.

CPU2 INT Error aggregator Error Type Register

Figure 8-65 CPU2_INT_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRPIPE_LOCK_KEY_ERRREG_PARITY_DIAG_ERRREG_PARITY_ERRPIPE_SECURITY_VIOMAXISPWARNISP
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
VECT_UNCERRVECT_CERRNMI_CONTEXT_RESTORE_VECT_UNCERRNMI_CONTEXT_RESTORE_VECT_CERRNMI_INTERRUPT_RETURN_ERRNMI_VECT_UNCERRNMI_VECT_CERRNMI_ISR_ENTRY_ERR
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
NMI_MAXISP_ERRRESERVEDRTINT_CONTEXT_RESTORE_VECT_UNCERRRTINT_CONTEXT_RESTORE_VECT_CERRRTINT_INTERRUPT_RETURN_ERRRTINT_VECT_UNCERRRTINT_VECT_CERRRTINT_ISR_ENTRY_ERR
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
INT_INTERRUPT_RETURN_ERRINT_VECT_UNCERRINT_VECT_CERRINT_ISR_ENTRY_ERRMAIN_INTERRUPT_RETURN_ERRMAIN_VECT_UNCERRMAIN_VECT_CERRMAIN_ISR_ENTRY_ERR
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-82 CPU2_INT_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority error set by software

Reset type: PORESETn

29PIPE_LOCK_KEY_ERRR0hPIPE Lock/key error

Reset type: PORESETn

28REG_PARITY_DIAG_ERRR0hPIPE Register parity diag error

Reset type: PORESETn

27REG_PARITY_ERRR0hPIPE Reg parity error

Reset type: PORESETn

26PIPE_SECURITY_VIOR0hPIPE security violation

Reset type: PORESETn

25MAXISPR0hmaxisp

Reset type: PORESETn

24WARNISPR0hwarnisp

Reset type: PORESETn

23VECT_UNCERRR0hVector Uncorrectable error generated by PIPE on software read of vector register having uncorrectable error

Reset type: PORESETn

22VECT_CERRR0hVector Correctable error generated by PIPE on software read of vector register having correctable error

Reset type: PORESETn

21NMI_CONTEXT_RESTORE_VECT_UNCERRR0hNMI Context restore Uncorrectable vector error

Reset type: PORESETn

20NMI_CONTEXT_RESTORE_VECT_CERRR0hNMI Context restore Correctable vector error

Reset type: PORESETn

19NMI_INTERRUPT_RETURN_ERRR0hNMI Interrupt return error

Reset type: PORESETn

18NMI_VECT_UNCERRR0hNMI Uncorrectable vector error

Reset type: PORESETn

17NMI_VECT_CERRR0hNMI Correctable vector error

Reset type: PORESETn

16NMI_ISR_ENTRY_ERRR0hNMI ISR entry error

Reset type: PORESETn

15NMI_MAXISP_ERRR0hNMI MAXISP error

Reset type: PORESETn

14RESERVEDR0hReserved
13RTINT_CONTEXT_RESTORE_VECT_UNCERRR0hRTINT Context restore Uncorrectable vector error

Reset type: PORESETn

12RTINT_CONTEXT_RESTORE_VECT_CERRR0hRTINT Context restore Correctable vector error

Reset type: PORESETn

11RTINT_INTERRUPT_RETURN_ERRR0hRTINT Interrupt return error

Reset type: PORESETn

10RTINT_VECT_UNCERRR0hRTINT Uncorrectable vector error

Reset type: PORESETn

9RTINT_VECT_CERRR0hRTINT Correctable vector error

Reset type: PORESETn

8RTINT_ISR_ENTRY_ERRR0hRTINT ISR entry error

Reset type: PORESETn

7INT_INTERRUPT_RETURN_ERRR0hINT INTerrupt return error

Reset type: PORESETn

6INT_VECT_UNCERRR0hINT Uncorrectable vector error

Reset type: PORESETn

5INT_VECT_CERRR0hINT Correctable vector error

Reset type: PORESETn

4INT_ISR_ENTRY_ERRR0hINT ISR entry error

Reset type: PORESETn

3MAIN_INTERRUPT_RETURN_ERRR0hMain Interrupt return error

Reset type: PORESETn

2MAIN_VECT_UNCERRR0hMain Uncorrectable vector error

Reset type: PORESETn

1MAIN_VECT_CERRR0hMain Correctable vector error

Reset type: PORESETn

0MAIN_ISR_ENTRY_ERRR0hMain ISR entry error

Reset type: PORESETn

8.9.3.58 CPU2_INT_ERROR_TYPE_FRC Register (Offset = 24Ch) [Reset = 00000000h]

CPU2_INT_ERROR_TYPE_FRC is shown in Figure 8-66 and described in Table 8-83.

Return to the Summary Table.

CPU2 INT Error aggregator Error Type Force Register

Figure 8-66 CPU2_INT_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRPIPE_LOCK_KEY_ERRREG_PARITY_DIAG_ERRREG_PARITY_ERRPIPE_SECURITY_VIOMAXISPWARNISP
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
VECT_UNCERRVECT_CERRNMI_CONTEXT_RESTORE_VECT_UNCERRNMI_CONTEXT_RESTORE_VECT_CERRNMI_INTERRUPT_RETURN_ERRNMI_VECT_UNCERRNMI_VECT_CERRNMI_ISR_ENTRY_ERR
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
NMI_MAXISP_ERRRESERVEDRTINT_CONTEXT_RESTORE_VECT_UNCERRRTINT_CONTEXT_RESTORE_VECT_CERRRTINT_INTERRUPT_RETURN_ERRRTINT_VECT_UNCERRRTINT_VECT_CERRRTINT_ISR_ENTRY_ERR
R-0/W1S-0hR-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
INT_INTERRUPT_RETURN_ERRINT_VECT_UNCERRINT_VECT_CERRINT_ISR_ENTRY_ERRMAIN_INTERRUPT_RETURN_ERRMAIN_VECT_UNCERRMAIN_VECT_CERRMAIN_ISR_ENTRY_ERR
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 8-83 CPU2_INT_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29PIPE_LOCK_KEY_ERRR-0/W1S0hPIPE Lock key error force register
0 - No action
1 - force PIPE lock key error flag

Reset type: PORESETn

28REG_PARITY_DIAG_ERRR-0/W1S0hPIPE Register parity diag error force register
0 - No action
1 - force MAX PSP violation flag

Reset type: PORESETn

27REG_PARITY_ERRR-0/W1S0hPIPE Register parity error force register
0 - No action
1 - force PIPE Register parity errort error flag

Reset type: PORESETn

26PIPE_SECURITY_VIOR-0/W1S0hPIPE security violation force register
0 - No action
1 - force PIPE security violation flag

Reset type: PORESETn

25MAXISPR-0/W1S0hMaxisp error flag force register
0 - No action
1 - force Maxisp error flag

Reset type: PORESETn

24WARNISPR-0/W1S0hWarnisp error flag force register
0 - No action
1 - force Warnisp error flag

Reset type: PORESETn

23VECT_UNCERRR-0/W1S0hVector uncorrectable error force register
0 - No action
1 - force vector uncorrectable eror flag

Reset type: PORESETn

22VECT_CERRR-0/W1S0hVector correctable error force register
0 - No action
1 - force vector correctable error flag

Reset type: PORESETn

21NMI_CONTEXT_RESTORE_VECT_UNCERRR-0/W1S0hNMI Context restore Uncorrectable vector error flag force register
0 - No action
1 - force NMI Context restore Uncorrectable vector error flag

Reset type: PORESETn

20NMI_CONTEXT_RESTORE_VECT_CERRR-0/W1S0hNMI Context restore Correctable vector error flag force register
0 - No action
1 - force NMI Context restore Correctable vector error flag

Reset type: PORESETn

19NMI_INTERRUPT_RETURN_ERRR-0/W1S0hNMI Interrupt return error flag force register
0 - No action
1 - force NMI Interrupt return error flag

Reset type: PORESETn

18NMI_VECT_UNCERRR-0/W1S0hNMI uncorrectable vector error flag force register
0 - No action
1 - force NMI uncorrectable vector error flag

Reset type: PORESETn

17NMI_VECT_CERRR-0/W1S0hNMI Correctable vector error flag force register
0 - No action
1 - force NMI Correctable vector error flag

Reset type: PORESETn

16NMI_ISR_ENTRY_ERRR-0/W1S0hNMI ISR entry error flag force register
0 - No action
1 - NMI ISR entry error flag

Reset type: PORESETn

15NMI_MAXISP_ERRR-0/W1S0hNMI MAXISP error flag force register
0 - No action
1 - NMI MAXISP error flag

Reset type: PORESETn

14RESERVEDR0hReserved
13RTINT_CONTEXT_RESTORE_VECT_UNCERRR-0/W1S0hRTINT Context restore Uncorrectable vector error flag force register
0 - No action
1 - force RTINT Context restore Uncorrectable vector error flag

Reset type: PORESETn

12RTINT_CONTEXT_RESTORE_VECT_CERRR-0/W1S0hRTINT Context restore Correctable vector error flag force register
0 - No action
1 - force RTINT Context restore Correctable vector error flag

Reset type: PORESETn

11RTINT_INTERRUPT_RETURN_ERRR-0/W1S0hRTINT Interrupt return error flag force register
0 - No action
1 - force RTINT Interrupt return error flag

Reset type: PORESETn

10RTINT_VECT_UNCERRR-0/W1S0hRTINT uncorrectable vector error flag force register
0 - No action
1 - force RTINT uncorrectable vector error flag

Reset type: PORESETn

9RTINT_VECT_CERRR-0/W1S0hRTINT Correctable vector error flag force register
0 - No action
1 - force RTINT Correctable vector error flag

Reset type: PORESETn

8RTINT_ISR_ENTRY_ERRR-0/W1S0hRTINT ISR entry error flag force register
0 - No action
1 - RTINT ISR entry error flag

Reset type: PORESETn

7INT_INTERRUPT_RETURN_ERRR-0/W1S0hINT Interrupt return error flag force register
0 - No action
1 - force INT Interrupt return error flag

Reset type: PORESETn

6INT_VECT_UNCERRR-0/W1S0hINT uncorrectable vector error flag force register
0 - No action
1 - force INT uncorrectable vector error flag

Reset type: PORESETn

5INT_VECT_CERRR-0/W1S0hINT Correctable vector error flag force register
0 - No action
1 - force INT Correctable vector error flag

Reset type: PORESETn

4INT_ISR_ENTRY_ERRR-0/W1S0hINT ISR entry error flag force register
0 - No action
1 - INT ISR entry error flag

Reset type: PORESETn

3MAIN_INTERRUPT_RETURN_ERRR-0/W1S0hMain Interrupt return error flag force register
0 - No action
1 - force Main Interrupt return error flag

Reset type: PORESETn

2MAIN_VECT_UNCERRR-0/W1S0hMain uncorrectable vector error flag force register
0 - No action
1 - force Main uncorrectable vector error flag

Reset type: PORESETn

1MAIN_VECT_CERRR-0/W1S0hMain Correctable vector error flag force register
0 - No action
1 - force Main Correctable vector error flag

Reset type: PORESETn

0MAIN_ISR_ENTRY_ERRR-0/W1S0hMain ISR entry error flag force register
0 - No action
1 - Main ISR entry error flag

Reset type: PORESETn

8.9.3.59 CPU2_INT_ERROR_TYPE_CLR Register (Offset = 250h) [Reset = 00000000h]

CPU2_INT_ERROR_TYPE_CLR is shown in Figure 8-67 and described in Table 8-84.

Return to the Summary Table.

CPU2 INT Error aggregator Error Type Clear Register

Figure 8-67 CPU2_INT_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRPIPE_LOCK_KEY_ERRREG_PARITY_DIAG_ERRREG_PARITY_ERRPIPE_SECURITY_VIOMAXISPWARNISP
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
2322212019181716
VECT_UNCERRVECT_CERRNMI_CONTEXT_RESTORE_VECT_UNCERRNMI_CONTEXT_RESTORE_VECT_CERRNMI_INTERRUPT_RETURN_ERRNMI_VECT_UNCERRNMI_VECT_CERRNMI_ISR_ENTRY_ERR
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
15141312111098
NMI_MAXISP_ERRRESERVEDRTINT_CONTEXT_RESTORE_VECT_UNCERRRTINT_CONTEXT_RESTORE_VECT_CERRRTINT_INTERRUPT_RETURN_ERRRTINT_VECT_UNCERRRTINT_VECT_CERRRTINT_ISR_ENTRY_ERR
R-0/W1C-0hR-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
76543210
INT_INTERRUPT_RETURN_ERRINT_VECT_UNCERRINT_VECT_CERRINT_ISR_ENTRY_ERRMAIN_INTERRUPT_RETURN_ERRMAIN_VECT_UNCERRMAIN_VECT_CERRMAIN_ISR_ENTRY_ERR
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 8-84 CPU2_INT_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29PIPE_LOCK_KEY_ERRR-0/W1C0hPIPE Lock key error clear register
0 - No action
1 - clear PIPE lock key error flag

Reset type: PORESETn

28REG_PARITY_DIAG_ERRR-0/W1C0hPIPE Register parity diag error clear register
0 - No action
1 - clear MAX PSP violation flag

Reset type: PORESETn

27REG_PARITY_ERRR-0/W1C0hPIPE Register parity error clear register
0 - No action
1 - clear PIPE Register parity errort error flag

Reset type: PORESETn

26PIPE_SECURITY_VIOR-0/W1C0hPIPE security violation clear register
0 - No action
1 - clear PIPE security violation flag

Reset type: PORESETn

25MAXISPR-0/W1C0hMaxisp error flag clear register
0 - No action
1 - Clear Maxisp error flag

Reset type: PORESETn

24WARNISPR-0/W1C0hWarnisp error flag clear register
0 - No action
1 - Clear Warnisp error flag

Reset type: PORESETn

23VECT_UNCERRR-0/W1C0hVector uncorrectable error clear register
0 - No action
1 - Clear vector uncorrectable error flag

Reset type: PORESETn

22VECT_CERRR-0/W1C0hVector correctable error clear register
0 - No action
1 - Clear vector correctable error flag

Reset type: PORESETn

21NMI_CONTEXT_RESTORE_VECT_UNCERRR-0/W1C0hNMI Context restore Uncorrectable vector error flag clear register
0 - No action
1 - clear NMI Context restore Uncorrectable vector error flag

Reset type: PORESETn

20NMI_CONTEXT_RESTORE_VECT_CERRR-0/W1C0hNMI Context restore Correctable vector error flag clear register
0 - No action
1 - clear NMI Context restore Correctable vector error flag

Reset type: PORESETn

19NMI_INTERRUPT_RETURN_ERRR-0/W1C0hNMI Interrupt return error flag clear register
0 - No action
1 - clear NMI Interrupt return error flag

Reset type: PORESETn

18NMI_VECT_UNCERRR-0/W1C0hNMI uncorrectable vector error flag clear register
0 - No action
1 - clear NMI uncorrectable vector error flag

Reset type: PORESETn

17NMI_VECT_CERRR-0/W1C0hNMI Correctable vector error flag clear register
0 - No action
1 - clear NMI Correctable vector error flag

Reset type: PORESETn

16NMI_ISR_ENTRY_ERRR-0/W1C0hNMI ISR entry error flag clear register
0 - No action
1 - NMI ISR entry error flag

Reset type: PORESETn

15NMI_MAXISP_ERRR-0/W1C0hNMI MAXISP error flag clear register
0 - No action
1 - NMI MAXISP error flag

Reset type: PORESETn

14RESERVEDR0hReserved
13RTINT_CONTEXT_RESTORE_VECT_UNCERRR-0/W1C0hRTINT Context restore Uncorrectable vector error flag clear register
0 - No action
1 - clear RTINT Context restore Uncorrectable vector error flag

Reset type: PORESETn

12RTINT_CONTEXT_RESTORE_VECT_CERRR-0/W1C0hRTINT Context restore Correctable vector error flag clear register
0 - No action
1 - clear RTINT Context restore Correctable vector error flag

Reset type: PORESETn

11RTINT_INTERRUPT_RETURN_ERRR-0/W1C0hRTINT Interrupt return error flag clear register
0 - No action
1 - clear RTINT Interrupt return error flag

Reset type: PORESETn

10RTINT_VECT_UNCERRR-0/W1C0hRTINT uncorrectable vector error flag clear register
0 - No action
1 - clear RTINT uncorrectable vector error flag

Reset type: PORESETn

9RTINT_VECT_CERRR-0/W1C0hRTINT Correctable vector error flag clear register
0 - No action
1 - clear RTINT Correctable vector error flag

Reset type: PORESETn

8RTINT_ISR_ENTRY_ERRR-0/W1C0hRTINT ISR entry error flag clear register
0 - No action
1 - RTINT ISR entry error flag

Reset type: PORESETn

7INT_INTERRUPT_RETURN_ERRR-0/W1C0hINT Interrupt return error flag clear register
0 - No action
1 - clear INT Interrupt return error flag

Reset type: PORESETn

6INT_VECT_UNCERRR-0/W1C0hINT uncorrectable vector error flag clear register
0 - No action
1 - clear INT uncorrectable vector error flag

Reset type: PORESETn

5INT_VECT_CERRR-0/W1C0hINT Correctable vector error flag clear register
0 - No action
1 - clear INT Correctable vector error flag

Reset type: PORESETn

4INT_ISR_ENTRY_ERRR-0/W1C0hINT ISR entry error flag clear register
0 - No action
1 - INT ISR entry error flag

Reset type: PORESETn

3MAIN_INTERRUPT_RETURN_ERRR-0/W1C0hMain Interrupt return error flag clear register
0 - No action
1 - clear Main Interrupt return error flag

Reset type: PORESETn

2MAIN_VECT_UNCERRR-0/W1C0hMain uncorrectable vector error flag clear register
0 - No action
1 - clear Main uncorrectable vector error flag

Reset type: PORESETn

1MAIN_VECT_CERRR-0/W1C0hMain Correctable vector error flag clear register
0 - No action
1 - clear Main Correctable vector error flag

Reset type: PORESETn

0MAIN_ISR_ENTRY_ERRR-0/W1C0hMain ISR entry error flag clear register
0 - No action
1 - Main ISR entry error flag

Reset type: PORESETn

8.9.3.60 CPU2_INT_PC Register (Offset = 254h) [Reset = 00000000h]

CPU2_INT_PC is shown in Figure 8-68 and described in Table 8-85.

Return to the Summary Table.

CPU2 INT Error aggregator Register to store PC value at the first High priority error event

Figure 8-68 CPU2_INT_PC Register
313029282726252423222120191817161514131211109876543210
CPU2_INT_PC
R-0h
Table 8-85 CPU2_INT_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU2_INT_PCR0hCPU2 PC at which first High priority error occurred on CPU2_INT

Reset type: PORESETn

8.9.3.61 CPU3_PR_HIGHPRIO_ERROR_ADDRESS Register (Offset = 280h) [Reset = 00000000h]

CPU3_PR_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-69 and described in Table 8-86.

Return to the Summary Table.

CPU3 PR Error aggregator High Priority Error address register

Figure 8-69 CPU3_PR_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU3_PR_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-86 CPU3_PR_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_PR_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU3_PR access

Reset type: PORESETn

8.9.3.62 CPU3_PR_LOWPRIO_ERROR_ADDRESS Register (Offset = 284h) [Reset = 00000000h]

CPU3_PR_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-70 and described in Table 8-87.

Return to the Summary Table.

CPU3 PR Error aggregator Low Priority Error address register

Figure 8-70 CPU3_PR_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU3_PR_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-87 CPU3_PR_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_PR_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU3_PR access

Reset type: PORESETn

8.9.3.63 CPU3_PR_ERROR_TYPE Register (Offset = 288h) [Reset = 00000000h]

CPU3_PR_ERROR_TYPE is shown in Figure 8-71 and described in Table 8-88.

Return to the Summary Table.

CPU3 PR Error aggregator Error Type Register

Figure 8-71 CPU3_PR_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDINSTRUCTION_TIMEOUTILLEGAL_INSTRUCTIONSW_BREAKPOINT_ERRWARN_PSP_ERR
R-0hR-0hR-0hR-0hR-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRMAX_PSP_ERRSEC_EXIT_VIOSEC_ENTRY_VIOINSTR_SECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-88 CPU3_PR_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority set by software

Reset type: PORESETn

29-12RESERVEDR0hReserved
11INSTRUCTION_TIMEOUTR0hInstruction timeout error

Reset type: PORESETn

10ILLEGAL_INSTRUCTIONR0hIllegal instruction error

Reset type: PORESETn

9SW_BREAKPOINT_ERRR0hSoftware brakepoint error

Reset type: PORESETn

8WARN_PSP_ERRR0hWarn PSP error

Reset type: PORESETn

7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0h Uncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0h Access timeout error

Reset type: PORESETn

3MAX_PSP_ERRR0h MAX PSP error

Reset type: PORESETn

2SEC_EXIT_VIOR0hSecure exit error

Reset type: PORESETn

1SEC_ENTRY_VIOR0hSecure entry and linear code crossing LINK, STACK, ZONE error.

Reset type: PORESETn

0INSTR_SECURITY_VIOR0hInstruction packet security violation. Instruction packet crossed LINK, STACK, ZONE boundary.

Reset type: PORESETn

8.9.3.64 CPU3_PR_ERROR_TYPE_FRC Register (Offset = 28Ch) [Reset = 00000000h]

CPU3_PR_ERROR_TYPE_FRC is shown in Figure 8-72 and described in Table 8-89.

Return to the Summary Table.

CPU3 PR Error aggregator Error Type Force Register

Figure 8-72 CPU3_PR_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDINSTRUCTION_TIMEOUTILLEGAL_INSTRUCTIONSW_BREAKPOINT_ERRWARN_PSP_ERR
R-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRMAX_PSP_ERRSEC_EXIT_VIOSEC_ENTRY_VIOINSTR_SECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 8-89 CPU3_PR_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hForce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-12RESERVEDR0hReserved
11INSTRUCTION_TIMEOUTR-0/W1S0hInstruction timeout error flag force register
0 - No action
1 - force Instruction timeout flag

Reset type: PORESETn

10ILLEGAL_INSTRUCTIONR-0/W1S0hIllegal instruction error flag force register
0 - No action
1 - Illegal instruction error flag

Reset type: PORESETn

9SW_BREAKPOINT_ERRR-0/W1S0hSoftware brakepoint error flag force register
0 - No action
1 - force Software brakepoint error flag

Reset type: PORESETn

8WARN_PSP_ERRR-0/W1S0hWARN PSP violation flag force register
0 - No action
1 - force WARN PSP violation flag

Reset type: PORESETn

7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3MAX_PSP_ERRR-0/W1S0hMAX PSP violation flag force register
0 - No action
1 - force MAX PSP violation flag

Reset type: PORESETn

2SEC_EXIT_VIOR-0/W1S0hSecure exit violation flag force register
0 - No action
1 - force Secure exit violation flag

Reset type: PORESETn

1SEC_ENTRY_VIOR-0/W1S0hSecure entry violation flag force register
0 - No action
1 - force Secure entry violation flag

Reset type: PORESETn

0INSTR_SECURITY_VIOR-0/W1S0hInstruction packet security violation flag force register
0 - No action
1 - force Instruction packet security violation flag

Reset type: PORESETn

8.9.3.65 CPU3_PR_ERROR_TYPE_CLR Register (Offset = 290h) [Reset = 00000000h]

CPU3_PR_ERROR_TYPE_CLR is shown in Figure 8-73 and described in Table 8-90.

Return to the Summary Table.

CPU3 PR Error aggregator Error Type Clear Register

Figure 8-73 CPU3_PR_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDINSTRUCTION_TIMEOUTILLEGAL_INSTRUCTIONSW_BREAKPOINT_ERRWARN_PSP_ERR
R-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRMAX_PSP_ERRSEC_EXIT_VIOSEC_ENTRY_VIOINSTR_SECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 8-90 CPU3_PR_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-12RESERVEDR0hReserved
11INSTRUCTION_TIMEOUTR-0/W1C0hInstruction timeout error flag clear register
0 - No action
1 - clear Instruction timeout flag

Reset type: PORESETn

10ILLEGAL_INSTRUCTIONR-0/W1C0hIllegal instruction error flag clear register
0 - No action
1 - Illegal instruction error flag

Reset type: PORESETn

9SW_BREAKPOINT_ERRR-0/W1C0hSoftware brakepoint error flag clear register
0 - No action
1 - clear Software brakepoint error flag

Reset type: PORESETn

8WARN_PSP_ERRR-0/W1C0hWARN PSP violation flag clear register
0 - No action
1 - Clear WARN PSP violation flag

Reset type: PORESETn

7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3MAX_PSP_ERRR-0/W1C0hMAX PSP violation flag clear register
0 - No action
1 - Clear MAX PSP violation flag

Reset type: PORESETn

2SEC_EXIT_VIOR-0/W1C0hSecure exit violation flag clear register
0 - No action
1 - Clear Secure exit violation flag

Reset type: PORESETn

1SEC_ENTRY_VIOR-0/W1C0hSecure entry violation flag clear register
0 - No action
1 - Clear Secure entry violation flag

Reset type: PORESETn

0INSTR_SECURITY_VIOR-0/W1C0hInstruction packet security violation flag clear register
0 - No action
1 - Clear Instruction packet security violation flag

Reset type: PORESETn

8.9.3.66 CPU3_PR_PC Register (Offset = 294h) [Reset = 00000000h]

CPU3_PR_PC is shown in Figure 8-74 and described in Table 8-91.

Return to the Summary Table.

CPU3 PR Error aggregator Register to store PC value at the first High priority error event

Figure 8-74 CPU3_PR_PC Register
313029282726252423222120191817161514131211109876543210
CPU3_PR_PC
R-0h
Table 8-91 CPU3_PR_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_PR_PCR0hCPPU3 PC at which first High priority error occurred on CPU3_PR access

Reset type: PORESETn

8.9.3.67 CPU3_DR1_HIGHPRIO_ERROR_ADDRESS Register (Offset = 2C0h) [Reset = 00000000h]

CPU3_DR1_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-75 and described in Table 8-92.

Return to the Summary Table.

CPU3 DR1 Error aggregator High Priority Error address register

Figure 8-75 CPU3_DR1_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU3_DR1_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-92 CPU3_DR1_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_DR1_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU3_DR1 access

Reset type: PORESETn

8.9.3.68 CPU3_DR1_LOWPRIO_ERROR_ADDRESS Register (Offset = 2C4h) [Reset = 00000000h]

CPU3_DR1_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-76 and described in Table 8-93.

Return to the Summary Table.

CPU3 DR1 Error aggregator Low Priority Error address register

Figure 8-76 CPU3_DR1_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU3_DR1_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-93 CPU3_DR1_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_DR1_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU3_DR1 access

Reset type: PORESETn

8.9.3.69 CPU3_DR1_ERROR_TYPE Register (Offset = 2C8h) [Reset = 00000000h]

CPU3_DR1_ERROR_TYPE is shown in Figure 8-77 and described in Table 8-94.

Return to the Summary Table.

CPU3 DR1 Error aggregator Error Type Register

Figure 8-77 CPU3_DR1_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-94 CPU3_DR1_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority high priority error set by software

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR0hUnaligned address error

Reset type: PORESETn

7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0hUncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0hAccess timeout error

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR0hSecurity violation

Reset type: PORESETn

8.9.3.70 CPU3_DR1_ERROR_TYPE_FRC Register (Offset = 2CCh) [Reset = 00000000h]

CPU3_DR1_ERROR_TYPE_FRC is shown in Figure 8-78 and described in Table 8-95.

Return to the Summary Table.

CPU3 DR1 Error aggregator Error Type Force Register

Figure 8-78 CPU3_DR1_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1S-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0h
Table 8-95 CPU3_DR1_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1S0hUnaligned address error flag force register
0 - No action
1 - force Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1S0hSecurity violation flag force register
0 - No action
1 - force Security violation flag

Reset type: PORESETn

8.9.3.71 CPU3_DR1_ERROR_TYPE_CLR Register (Offset = 2D0h) [Reset = 00000000h]

CPU3_DR1_ERROR_TYPE_CLR is shown in Figure 8-79 and described in Table 8-96.

Return to the Summary Table.

CPU3 DR1 Error aggregator Error Type Clear Register

Figure 8-79 CPU3_DR1_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1C-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0hR-0/W1C-0h
Table 8-96 CPU3_DR1_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1C0hUnaligned address error flag clear register
0 - No action
1 - Clear Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1C0hSecurity violation flag clear register
0 - No action
1 - Clear Security violation flag

Reset type: PORESETn

8.9.3.72 CPU3_DR1_PC Register (Offset = 2D4h) [Reset = 00000000h]

CPU3_DR1_PC is shown in Figure 8-80 and described in Table 8-97.

Return to the Summary Table.

CPU3 DR1 Error aggregator Register to store PC value at the first High priority error event

Figure 8-80 CPU3_DR1_PC Register
313029282726252423222120191817161514131211109876543210
CPU3_DR1_PC
R-0h
Table 8-97 CPU3_DR1_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_DR1_PCR0hCPU3 PC at which first High priority error occurred on CPU3_DR1 access

Reset type: PORESETn

8.9.3.73 CPU3_DR2_HIGHPRIO_ERROR_ADDRESS Register (Offset = 300h) [Reset = 00000000h]

CPU3_DR2_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-81 and described in Table 8-98.

Return to the Summary Table.

CPU3 DR2 Error aggregator High Priority Error address register

Figure 8-81 CPU3_DR2_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU3_DR2_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-98 CPU3_DR2_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_DR2_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU3_DR2 access

Reset type: PORESETn

8.9.3.74 CPU3_DR2_LOWPRIO_ERROR_ADDRESS Register (Offset = 304h) [Reset = 00000000h]

CPU3_DR2_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-82 and described in Table 8-99.

Return to the Summary Table.

CPU3 DR2 Error aggregator Low Priority Error address register

Figure 8-82 CPU3_DR2_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU3_DR2_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-99 CPU3_DR2_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_DR2_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU3_DR2 access

Reset type: PORESETn

8.9.3.75 CPU3_DR2_ERROR_TYPE Register (Offset = 308h) [Reset = 00000000h]

CPU3_DR2_ERROR_TYPE is shown in Figure 8-83 and described in Table 8-100.

Return to the Summary Table.

CPU3 DR2 Error aggregator Error Type Register

Figure 8-83 CPU3_DR2_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-100 CPU3_DR2_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority error set by software

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR0hUnaligned address error

Reset type: PORESETn

7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0hUncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0hAccess timeout error

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR0hSecurity violation

Reset type: PORESETn

8.9.3.76 CPU3_DR2_ERROR_TYPE_FRC Register (Offset = 30Ch) [Reset = 00000000h]

CPU3_DR2_ERROR_TYPE_FRC is shown in Figure 8-84 and described in Table 8-101.

Return to the Summary Table.

CPU3 DR2 Error aggregator Error Type Force Register

Figure 8-84 CPU3_DR2_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1S-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0h
Table 8-101 CPU3_DR2_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1S0hUnaligned address error flag force register
0 - No action
1 - force Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1S0hSecurity violation flag force register
0 - No action
1 - force Security violation flag

Reset type: PORESETn

8.9.3.77 CPU3_DR2_ERROR_TYPE_CLR Register (Offset = 310h) [Reset = 00000000h]

CPU3_DR2_ERROR_TYPE_CLR is shown in Figure 8-85 and described in Table 8-102.

Return to the Summary Table.

CPU3 DR2 Error aggregator Error Type Clear Register

Figure 8-85 CPU3_DR2_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1C-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0hR-0/W1C-0h
Table 8-102 CPU3_DR2_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1C0hUnaligned address error flag clear register
0 - No action
1 - Clear Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1C0hSecurity violation flag clear register
0 - No action
1 - Clear Security violation flag

Reset type: PORESETn

8.9.3.78 CPU3_DR2_PC Register (Offset = 314h) [Reset = 00000000h]

CPU3_DR2_PC is shown in Figure 8-86 and described in Table 8-103.

Return to the Summary Table.

CPU3 DR2 Error aggregator Register to store PC value at the first High priority error event

Figure 8-86 CPU3_DR2_PC Register
313029282726252423222120191817161514131211109876543210
CPU3_DR2_PC
R-0h
Table 8-103 CPU3_DR2_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_DR2_PCR0hCPU3 PC at which first High priority error occurred on CPU3_DR2 access

Reset type: PORESETn

8.9.3.79 CPU3_DW_HIGHPRIO_ERROR_ADDRESS Register (Offset = 340h) [Reset = 00000000h]

CPU3_DW_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-87 and described in Table 8-104.

Return to the Summary Table.

CPU3 DW Error aggregator High Priority Error address register

Figure 8-87 CPU3_DW_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU3_DW_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-104 CPU3_DW_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_DW_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU3_DW access

Reset type: PORESETn

8.9.3.80 CPU3_DW_LOWPRIO_ERROR_ADDRESS Register (Offset = 344h) [Reset = 00000000h]

CPU3_DW_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-88 and described in Table 8-105.

Return to the Summary Table.

CPU3 DW Error aggregator Low Priority Error address register

Figure 8-88 CPU3_DW_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU3_DW_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-105 CPU3_DW_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_DW_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU3_DW access

Reset type: PORESETn

8.9.3.81 CPU3_DW_ERROR_TYPE Register (Offset = 348h) [Reset = 00000000h]

CPU3_DW_ERROR_TYPE is shown in Figure 8-89 and described in Table 8-106.

Return to the Summary Table.

CPU3 DW Error aggregator Error Type Register

Figure 8-89 CPU3_DW_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-106 CPU3_DW_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority error set by software

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR0hUnaligned address error

Reset type: PORESETn

7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0hUncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0hAccess timeout error

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR0hSecurity violation

Reset type: PORESETn

8.9.3.82 CPU3_DW_ERROR_TYPE_FRC Register (Offset = 34Ch) [Reset = 00000000h]

CPU3_DW_ERROR_TYPE_FRC is shown in Figure 8-90 and described in Table 8-107.

Return to the Summary Table.

CPU3 DW Error aggregator Error Type Force Register

Figure 8-90 CPU3_DW_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1S-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0h
Table 8-107 CPU3_DW_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1S0hUnaligned address error flag force register
0 - No action
1 - force Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1S0hSecurity violation flag force register
0 - No action
1 - force Security violation flag

Reset type: PORESETn

8.9.3.83 CPU3_DW_ERROR_TYPE_CLR Register (Offset = 350h) [Reset = 00000000h]

CPU3_DW_ERROR_TYPE_CLR is shown in Figure 8-91 and described in Table 8-108.

Return to the Summary Table.

CPU3 DW Error aggregator Error Type Clear Register

Figure 8-91 CPU3_DW_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUNALIGNED_ADDR_ERR
R-0hR-0/W1C-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0hR-0/W1C-0h
Table 8-108 CPU3_DW_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-9RESERVEDR0hReserved
8UNALIGNED_ADDR_ERRR-0/W1C0hUnaligned address error flag clear register
0 - No action
1 - Clear Unaligned address error flag

Reset type: PORESETn

7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1C0hSecurity violation flag clear register
0 - No action
1 - Clear Security violation flag

Reset type: PORESETn

8.9.3.84 CPU3_DW_PC Register (Offset = 354h) [Reset = 00000000h]

CPU3_DW_PC is shown in Figure 8-92 and described in Table 8-109.

Return to the Summary Table.

CPU3 DW Error aggregator Register to store PC value at the first High priority error event

Figure 8-92 CPU3_DW_PC Register
313029282726252423222120191817161514131211109876543210
CPU3_DW_PC
R-0h
Table 8-109 CPU3_DW_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_DW_PCR0hCPU3 PC at which first High priority error occurred on CPU3_DW access

Reset type: PORESETn

8.9.3.85 CPU3_INT_HIGHPRIO_ERROR_ADDRESS Register (Offset = 380h) [Reset = 00000000h]

CPU3_INT_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-93 and described in Table 8-110.

Return to the Summary Table.

CPU3 INT Error aggregator High Priority Error address register

Figure 8-93 CPU3_INT_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU3_INT_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-110 CPU3_INT_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_INT_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on CPU3_INT

Reset type: PORESETn

8.9.3.86 CPU3_INT_LOWPRIO_ERROR_ADDRESS Register (Offset = 384h) [Reset = 00000000h]

CPU3_INT_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-94 and described in Table 8-111.

Return to the Summary Table.

CPU3 INT Error aggregator Low Priority Error address register

Figure 8-94 CPU3_INT_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
CPU3_INT_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-111 CPU3_INT_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_INT_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on CPU3_INT

Reset type: PORESETn

8.9.3.87 CPU3_INT_ERROR_TYPE Register (Offset = 388h) [Reset = 00000000h]

CPU3_INT_ERROR_TYPE is shown in Figure 8-95 and described in Table 8-112.

Return to the Summary Table.

CPU3 INT Error aggregator Error Type Register

Figure 8-95 CPU3_INT_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRPIPE_LOCK_KEY_ERRREG_PARITY_DIAG_ERRREG_PARITY_ERRPIPE_SECURITY_VIOMAXISPWARNISP
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
VECT_UNCERRVECT_CERRNMI_CONTEXT_RESTORE_VECT_UNCERRNMI_CONTEXT_RESTORE_VECT_CERRNMI_INTERRUPT_RETURN_ERRNMI_VECT_UNCERRNMI_VECT_CERRNMI_ISR_ENTRY_ERR
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
NMI_MAXISP_ERRRESERVEDRTINT_CONTEXT_RESTORE_VECT_UNCERRRTINT_CONTEXT_RESTORE_VECT_CERRRTINT_INTERRUPT_RETURN_ERRRTINT_VECT_UNCERRRTINT_VECT_CERRRTINT_ISR_ENTRY_ERR
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
INT_INTERRUPT_RETURN_ERRINT_VECT_UNCERRINT_VECT_CERRINT_ISR_ENTRY_ERRMAIN_INTERRUPT_RETURN_ERRMAIN_VECT_UNCERRMAIN_VECT_CERRMAIN_ISR_ENTRY_ERR
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-112 CPU3_INT_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority error set by software

Reset type: PORESETn

29PIPE_LOCK_KEY_ERRR0hPIPE Lock/key error

Reset type: PORESETn

28REG_PARITY_DIAG_ERRR0hPIPE Register parity diag error

Reset type: PORESETn

27REG_PARITY_ERRR0hPIPE Reg parity error

Reset type: PORESETn

26PIPE_SECURITY_VIOR0hPIPE security violation

Reset type: PORESETn

25MAXISPR0hmaxisp

Reset type: PORESETn

24WARNISPR0hwarnisp

Reset type: PORESETn

23VECT_UNCERRR0hVector Uncorrectable error generated by PIPE on software read of vector register having uncorrectable error

Reset type: PORESETn

22VECT_CERRR0hVector Correctable error generated by PIPE on software read of vector register having correctable error

Reset type: PORESETn

21NMI_CONTEXT_RESTORE_VECT_UNCERRR0hNMI Context restore Uncorrectable vector error

Reset type: PORESETn

20NMI_CONTEXT_RESTORE_VECT_CERRR0hNMI Context restore Correctable vector error

Reset type: PORESETn

19NMI_INTERRUPT_RETURN_ERRR0hNMI Interrupt return error

Reset type: PORESETn

18NMI_VECT_UNCERRR0hNMI Uncorrectable vector error

Reset type: PORESETn

17NMI_VECT_CERRR0hNMI Correctable vector error

Reset type: PORESETn

16NMI_ISR_ENTRY_ERRR0hNMI ISR entry error

Reset type: PORESETn

15NMI_MAXISP_ERRR0hNMI MAXISP error

Reset type: PORESETn

14RESERVEDR0hReserved
13RTINT_CONTEXT_RESTORE_VECT_UNCERRR0hRTINT Context restore Uncorrectable vector error

Reset type: PORESETn

12RTINT_CONTEXT_RESTORE_VECT_CERRR0hRTINT Context restore Correctable vector error

Reset type: PORESETn

11RTINT_INTERRUPT_RETURN_ERRR0hRTINT Interrupt return error

Reset type: PORESETn

10RTINT_VECT_UNCERRR0hRTINT Uncorrectable vector error

Reset type: PORESETn

9RTINT_VECT_CERRR0hRTINT Correctable vector error

Reset type: PORESETn

8RTINT_ISR_ENTRY_ERRR0hRTINT ISR entry error

Reset type: PORESETn

7INT_INTERRUPT_RETURN_ERRR0hINT INTerrupt return error

Reset type: PORESETn

6INT_VECT_UNCERRR0hINT Uncorrectable vector error

Reset type: PORESETn

5INT_VECT_CERRR0hINT Correctable vector error

Reset type: PORESETn

4INT_ISR_ENTRY_ERRR0hINT ISR entry error

Reset type: PORESETn

3MAIN_INTERRUPT_RETURN_ERRR0hMain Interrupt return error

Reset type: PORESETn

2MAIN_VECT_UNCERRR0hMain Uncorrectable vector error

Reset type: PORESETn

1MAIN_VECT_CERRR0hMain Correctable vector error

Reset type: PORESETn

0MAIN_ISR_ENTRY_ERRR0hMain ISR entry error

Reset type: PORESETn

8.9.3.88 CPU3_INT_ERROR_TYPE_FRC Register (Offset = 38Ch) [Reset = 00000000h]

CPU3_INT_ERROR_TYPE_FRC is shown in Figure 8-96 and described in Table 8-113.

Return to the Summary Table.

CPU3 INT Error aggregator Error Type Force Register

Figure 8-96 CPU3_INT_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRPIPE_LOCK_KEY_ERRREG_PARITY_DIAG_ERRREG_PARITY_ERRPIPE_SECURITY_VIOMAXISPWARNISP
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
VECT_UNCERRVECT_CERRNMI_CONTEXT_RESTORE_VECT_UNCERRNMI_CONTEXT_RESTORE_VECT_CERRNMI_INTERRUPT_RETURN_ERRNMI_VECT_UNCERRNMI_VECT_CERRNMI_ISR_ENTRY_ERR
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
NMI_MAXISP_ERRRESERVEDRTINT_CONTEXT_RESTORE_VECT_UNCERRRTINT_CONTEXT_RESTORE_VECT_CERRRTINT_INTERRUPT_RETURN_ERRRTINT_VECT_UNCERRRTINT_VECT_CERRRTINT_ISR_ENTRY_ERR
R-0/W1S-0hR-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
INT_INTERRUPT_RETURN_ERRINT_VECT_UNCERRINT_VECT_CERRINT_ISR_ENTRY_ERRMAIN_INTERRUPT_RETURN_ERRMAIN_VECT_UNCERRMAIN_VECT_CERRMAIN_ISR_ENTRY_ERR
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 8-113 CPU3_INT_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29PIPE_LOCK_KEY_ERRR-0/W1S0hPIPE Lock key error force register
0 - No action
1 - force PIPE lock key error flag

Reset type: PORESETn

28REG_PARITY_DIAG_ERRR-0/W1S0hPIPE Register parity diag error force register
0 - No action
1 - force MAX PSP violation flag

Reset type: PORESETn

27REG_PARITY_ERRR-0/W1S0hPIPE Register parity error force register
0 - No action
1 - force PIPE Register parity errort error flag

Reset type: PORESETn

26PIPE_SECURITY_VIOR-0/W1S0hPIPE security violation force register
0 - No action
1 - force PIPE security violation flag

Reset type: PORESETn

25MAXISPR-0/W1S0hMaxisp error flag force register
0 - No action
1 - force Maxisp error flag

Reset type: PORESETn

24WARNISPR-0/W1S0hWarnisp error flag force register
0 - No action
1 - force Warnisp error flag

Reset type: PORESETn

23VECT_UNCERRR-0/W1S0hVector uncorrectable error force register
0 - No action
1 - force vector uncorrectable eror flag

Reset type: PORESETn

22VECT_CERRR-0/W1S0hVector correctable error force register
0 - No action
1 - force vector correctable error flag

Reset type: PORESETn

21NMI_CONTEXT_RESTORE_VECT_UNCERRR-0/W1S0hNMI Context restore Uncorrectable vector error flag force register
0 - No action
1 - force NMI Context restore Uncorrectable vector error flag

Reset type: PORESETn

20NMI_CONTEXT_RESTORE_VECT_CERRR-0/W1S0hNMI Context restore Correctable vector error flag force register
0 - No action
1 - force NMI Context restore Correctable vector error flag

Reset type: PORESETn

19NMI_INTERRUPT_RETURN_ERRR-0/W1S0hNMI Interrupt return error flag force register
0 - No action
1 - force NMI Interrupt return error flag

Reset type: PORESETn

18NMI_VECT_UNCERRR-0/W1S0hNMI uncorrectable vector error flag force register
0 - No action
1 - force NMI uncorrectable vector error flag

Reset type: PORESETn

17NMI_VECT_CERRR-0/W1S0hNMI Correctable vector error flag force register
0 - No action
1 - force NMI Correctable vector error flag

Reset type: PORESETn

16NMI_ISR_ENTRY_ERRR-0/W1S0hNMI ISR entry error flag force register
0 - No action
1 - NMI ISR entry error flag

Reset type: PORESETn

15NMI_MAXISP_ERRR-0/W1S0hNMI MAXISP error flag force register
0 - No action
1 - NMI MAXISP error flag

Reset type: PORESETn

14RESERVEDR0hReserved
13RTINT_CONTEXT_RESTORE_VECT_UNCERRR-0/W1S0hRTINT Context restore Uncorrectable vector error flag force register
0 - No action
1 - force RTINT Context restore Uncorrectable vector error flag

Reset type: PORESETn

12RTINT_CONTEXT_RESTORE_VECT_CERRR-0/W1S0hRTINT Context restore Correctable vector error flag force register
0 - No action
1 - force RTINT Context restore Correctable vector error flag

Reset type: PORESETn

11RTINT_INTERRUPT_RETURN_ERRR-0/W1S0hRTINT Interrupt return error flag force register
0 - No action
1 - force RTINT Interrupt return error flag

Reset type: PORESETn

10RTINT_VECT_UNCERRR-0/W1S0hRTINT uncorrectable vector error flag force register
0 - No action
1 - force RTINT uncorrectable vector error flag

Reset type: PORESETn

9RTINT_VECT_CERRR-0/W1S0hRTINT Correctable vector error flag force register
0 - No action
1 - force RTINT Correctable vector error flag

Reset type: PORESETn

8RTINT_ISR_ENTRY_ERRR-0/W1S0hRTINT ISR entry error flag force register
0 - No action
1 - RTINT ISR entry error flag

Reset type: PORESETn

7INT_INTERRUPT_RETURN_ERRR-0/W1S0hINT Interrupt return error flag force register
0 - No action
1 - force INT Interrupt return error flag

Reset type: PORESETn

6INT_VECT_UNCERRR-0/W1S0hINT uncorrectable vector error flag force register
0 - No action
1 - force INT uncorrectable vector error flag

Reset type: PORESETn

5INT_VECT_CERRR-0/W1S0hINT Correctable vector error flag force register
0 - No action
1 - force INT Correctable vector error flag

Reset type: PORESETn

4INT_ISR_ENTRY_ERRR-0/W1S0hINT ISR entry error flag force register
0 - No action
1 - INT ISR entry error flag

Reset type: PORESETn

3MAIN_INTERRUPT_RETURN_ERRR-0/W1S0hMain Interrupt return error flag force register
0 - No action
1 - force Main Interrupt return error flag

Reset type: PORESETn

2MAIN_VECT_UNCERRR-0/W1S0hMain uncorrectable vector error flag force register
0 - No action
1 - force Main uncorrectable vector error flag

Reset type: PORESETn

1MAIN_VECT_CERRR-0/W1S0hMain Correctable vector error flag force register
0 - No action
1 - force Main Correctable vector error flag

Reset type: PORESETn

0MAIN_ISR_ENTRY_ERRR-0/W1S0hMain ISR entry error flag force register
0 - No action
1 - Main ISR entry error flag

Reset type: PORESETn

8.9.3.89 CPU3_INT_ERROR_TYPE_CLR Register (Offset = 390h) [Reset = 00000000h]

CPU3_INT_ERROR_TYPE_CLR is shown in Figure 8-97 and described in Table 8-114.

Return to the Summary Table.

CPU3 INT Error aggregator Error Type Clear Register

Figure 8-97 CPU3_INT_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRPIPE_LOCK_KEY_ERRREG_PARITY_DIAG_ERRREG_PARITY_ERRPIPE_SECURITY_VIOMAXISPWARNISP
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
2322212019181716
VECT_UNCERRVECT_CERRNMI_CONTEXT_RESTORE_VECT_UNCERRNMI_CONTEXT_RESTORE_VECT_CERRNMI_INTERRUPT_RETURN_ERRNMI_VECT_UNCERRNMI_VECT_CERRNMI_ISR_ENTRY_ERR
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
15141312111098
NMI_MAXISP_ERRRESERVEDRTINT_CONTEXT_RESTORE_VECT_UNCERRRTINT_CONTEXT_RESTORE_VECT_CERRRTINT_INTERRUPT_RETURN_ERRRTINT_VECT_UNCERRRTINT_VECT_CERRRTINT_ISR_ENTRY_ERR
R-0/W1C-0hR-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
76543210
INT_INTERRUPT_RETURN_ERRINT_VECT_UNCERRINT_VECT_CERRINT_ISR_ENTRY_ERRMAIN_INTERRUPT_RETURN_ERRMAIN_VECT_UNCERRMAIN_VECT_CERRMAIN_ISR_ENTRY_ERR
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 8-114 CPU3_INT_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29PIPE_LOCK_KEY_ERRR-0/W1C0hPIPE Lock key error clear register
0 - No action
1 - clear PIPE lock key error flag

Reset type: PORESETn

28REG_PARITY_DIAG_ERRR-0/W1C0hPIPE Register parity diag error clear register
0 - No action
1 - clear MAX PSP violation flag

Reset type: PORESETn

27REG_PARITY_ERRR-0/W1C0hPIPE Register parity error clear register
0 - No action
1 - clear PIPE Register parity errort error flag

Reset type: PORESETn

26PIPE_SECURITY_VIOR-0/W1C0hPIPE security violation clear register
0 - No action
1 - clear PIPE security violation flag

Reset type: PORESETn

25MAXISPR-0/W1C0hMaxisp error flag clear register
0 - No action
1 - Clear Maxisp error flag

Reset type: PORESETn

24WARNISPR-0/W1C0hWarnisp error flag clear register
0 - No action
1 - Clear Warnisp error flag

Reset type: PORESETn

23VECT_UNCERRR-0/W1C0hVector uncorrectable error clear register
0 - No action
1 - Clear vector uncorrectable error flag

Reset type: PORESETn

22VECT_CERRR-0/W1C0hVector correctable error clear register
0 - No action
1 - Clear vector correctable error flag

Reset type: PORESETn

21NMI_CONTEXT_RESTORE_VECT_UNCERRR-0/W1C0hNMI Context restore Uncorrectable vector error flag clear register
0 - No action
1 - clear NMI Context restore Uncorrectable vector error flag

Reset type: PORESETn

20NMI_CONTEXT_RESTORE_VECT_CERRR-0/W1C0hNMI Context restore Correctable vector error flag clear register
0 - No action
1 - clear NMI Context restore Correctable vector error flag

Reset type: PORESETn

19NMI_INTERRUPT_RETURN_ERRR-0/W1C0hNMI Interrupt return error flag clear register
0 - No action
1 - clear NMI Interrupt return error flag

Reset type: PORESETn

18NMI_VECT_UNCERRR-0/W1C0hNMI uncorrectable vector error flag clear register
0 - No action
1 - clear NMI uncorrectable vector error flag

Reset type: PORESETn

17NMI_VECT_CERRR-0/W1C0hNMI Correctable vector error flag clear register
0 - No action
1 - clear NMI Correctable vector error flag

Reset type: PORESETn

16NMI_ISR_ENTRY_ERRR-0/W1C0hNMI ISR entry error flag clear register
0 - No action
1 - NMI ISR entry error flag

Reset type: PORESETn

15NMI_MAXISP_ERRR-0/W1C0hNMI MAXISP error flag clear register
0 - No action
1 - NMI MAXISP error flag

Reset type: PORESETn

14RESERVEDR0hReserved
13RTINT_CONTEXT_RESTORE_VECT_UNCERRR-0/W1C0hRTINT Context restore Uncorrectable vector error flag clear register
0 - No action
1 - clear RTINT Context restore Uncorrectable vector error flag

Reset type: PORESETn

12RTINT_CONTEXT_RESTORE_VECT_CERRR-0/W1C0hRTINT Context restore Correctable vector error flag clear register
0 - No action
1 - clear RTINT Context restore Correctable vector error flag

Reset type: PORESETn

11RTINT_INTERRUPT_RETURN_ERRR-0/W1C0hRTINT Interrupt return error flag clear register
0 - No action
1 - clear RTINT Interrupt return error flag

Reset type: PORESETn

10RTINT_VECT_UNCERRR-0/W1C0hRTINT uncorrectable vector error flag clear register
0 - No action
1 - clear RTINT uncorrectable vector error flag

Reset type: PORESETn

9RTINT_VECT_CERRR-0/W1C0hRTINT Correctable vector error flag clear register
0 - No action
1 - clear RTINT Correctable vector error flag

Reset type: PORESETn

8RTINT_ISR_ENTRY_ERRR-0/W1C0hRTINT ISR entry error flag clear register
0 - No action
1 - RTINT ISR entry error flag

Reset type: PORESETn

7INT_INTERRUPT_RETURN_ERRR-0/W1C0hINT Interrupt return error flag clear register
0 - No action
1 - clear INT Interrupt return error flag

Reset type: PORESETn

6INT_VECT_UNCERRR-0/W1C0hINT uncorrectable vector error flag clear register
0 - No action
1 - clear INT uncorrectable vector error flag

Reset type: PORESETn

5INT_VECT_CERRR-0/W1C0hINT Correctable vector error flag clear register
0 - No action
1 - clear INT Correctable vector error flag

Reset type: PORESETn

4INT_ISR_ENTRY_ERRR-0/W1C0hINT ISR entry error flag clear register
0 - No action
1 - INT ISR entry error flag

Reset type: PORESETn

3MAIN_INTERRUPT_RETURN_ERRR-0/W1C0hMain Interrupt return error flag clear register
0 - No action
1 - clear Main Interrupt return error flag

Reset type: PORESETn

2MAIN_VECT_UNCERRR-0/W1C0hMain uncorrectable vector error flag clear register
0 - No action
1 - clear Main uncorrectable vector error flag

Reset type: PORESETn

1MAIN_VECT_CERRR-0/W1C0hMain Correctable vector error flag clear register
0 - No action
1 - clear Main Correctable vector error flag

Reset type: PORESETn

0MAIN_ISR_ENTRY_ERRR-0/W1C0hMain ISR entry error flag clear register
0 - No action
1 - Main ISR entry error flag

Reset type: PORESETn

8.9.3.90 CPU3_INT_PC Register (Offset = 394h) [Reset = 00000000h]

CPU3_INT_PC is shown in Figure 8-98 and described in Table 8-115.

Return to the Summary Table.

CPU3 INT Error aggregator Register to store PC value at the first High priority error event

Figure 8-98 CPU3_INT_PC Register
313029282726252423222120191817161514131211109876543210
CPU3_INT_PC
R-0h
Table 8-115 CPU3_INT_PC Register Field Descriptions
BitFieldTypeResetDescription
31-0CPU3_INT_PCR0hCPU3 PC at which first High priority error occurred on CPU3_INT

Reset type: PORESETn

8.9.3.91 RTDMA1_DR_HIGHPRIO_ERROR_ADDRESS Register (Offset = 780h) [Reset = 00000000h]

RTDMA1_DR_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-99 and described in Table 8-116.

Return to the Summary Table.

RTDMA1 DR Error aggregator High Priority Error address register

Figure 8-99 RTDMA1_DR_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
RTDMA1_DR_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-116 RTDMA1_DR_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0RTDMA1_DR_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on RTDMA1_DR access

Reset type: PORESETn

8.9.3.92 RTDMA1_DR_LOWPRIO_ERROR_ADDRESS Register (Offset = 784h) [Reset = 00000000h]

RTDMA1_DR_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-100 and described in Table 8-117.

Return to the Summary Table.

RTDMA1 DR Error aggregator Low Priority Error address register

Figure 8-100 RTDMA1_DR_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
RTDMA1_DR_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-117 RTDMA1_DR_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0RTDMA1_DR_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on RTDMA1_DR access

Reset type: PORESETn

8.9.3.93 RTDMA1_DR_ERROR_TYPE Register (Offset = 788h) [Reset = 00000000h]

RTDMA1_DR_ERROR_TYPE is shown in Figure 8-101 and described in Table 8-118.

Return to the Summary Table.

RTDMA1 DR Error aggregator Error Type Register

Figure 8-101 RTDMA1_DR_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-118 RTDMA1_DR_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hlow priority software error set by software

Reset type: PORESETn

29-8RESERVEDR0hReserved
7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0hUncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0hAccess timeout error

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR0hSecurity violation

Reset type: PORESETn

8.9.3.94 RTDMA1_DR_ERROR_TYPE_FRC Register (Offset = 78Ch) [Reset = 00000000h]

RTDMA1_DR_ERROR_TYPE_FRC is shown in Figure 8-102 and described in Table 8-119.

Return to the Summary Table.

RTDMA1 DR Error aggregator Error Type Force Register

Figure 8-102 RTDMA1_DR_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0h
Table 8-119 RTDMA1_DR_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-8RESERVEDR0hReserved
7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1S0hSecurity violation flag force register
0 - No action
1 - force Security violation flag

Reset type: PORESETn

8.9.3.95 RTDMA1_DR_ERROR_TYPE_CLR Register (Offset = 790h) [Reset = 00000000h]

RTDMA1_DR_ERROR_TYPE_CLR is shown in Figure 8-103 and described in Table 8-120.

Return to the Summary Table.

RTDMA1 DR Error aggregator Error Type Clear Register

Figure 8-103 RTDMA1_DR_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0hR-0/W1C-0h
Table 8-120 RTDMA1_DR_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-8RESERVEDR0hReserved
7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1C0hSecurity violation flag clear register
0 - No action
1 - Clear Security violation flag

Reset type: PORESETn

8.9.3.96 RTDMA1_DW_HIGHPRIO_ERROR_ADDRESS Register (Offset = 7C0h) [Reset = 00000000h]

RTDMA1_DW_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-104 and described in Table 8-121.

Return to the Summary Table.

RTDMA1 DW Error aggregator High Priority Error address register

Figure 8-104 RTDMA1_DW_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
RTDMA1_DW_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-121 RTDMA1_DW_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0RTDMA1_DW_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on RTDMA1_DW access

Reset type: PORESETn

8.9.3.97 RTDMA1_DW_LOWPRIO_ERROR_ADDRESS Register (Offset = 7C4h) [Reset = 00000000h]

RTDMA1_DW_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-105 and described in Table 8-122.

Return to the Summary Table.

RTDMA1 DW Error aggregator Low Priority Error address register

Figure 8-105 RTDMA1_DW_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
RTDMA1_DW_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-122 RTDMA1_DW_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0RTDMA1_DW_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on RTDMA1_DW access

Reset type: PORESETn

8.9.3.98 RTDMA1_DW_ERROR_TYPE Register (Offset = 7C8h) [Reset = 00000000h]

RTDMA1_DW_ERROR_TYPE is shown in Figure 8-106 and described in Table 8-123.

Return to the Summary Table.

RTDMA1 DW Error aggregator Error Type Register

Figure 8-106 RTDMA1_DW_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-123 RTDMA1_DW_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority error set by software

Reset type: PORESETn

29-8RESERVEDR0hReserved
7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0hUncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0hAccess timeout error

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR0hSecurity violation

Reset type: PORESETn

8.9.3.99 RTDMA1_DW_ERROR_TYPE_FRC Register (Offset = 7CCh) [Reset = 00000000h]

RTDMA1_DW_ERROR_TYPE_FRC is shown in Figure 8-107 and described in Table 8-124.

Return to the Summary Table.

RTDMA1 DW Error aggregator Error Type Force Register

Figure 8-107 RTDMA1_DW_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0h
Table 8-124 RTDMA1_DW_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-8RESERVEDR0hReserved
7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1S0hSecurity violation flag force register
0 - No action
1 - force Security violation flag

Reset type: PORESETn

8.9.3.100 RTDMA1_DW_ERROR_TYPE_CLR Register (Offset = 7D0h) [Reset = 00000000h]

RTDMA1_DW_ERROR_TYPE_CLR is shown in Figure 8-108 and described in Table 8-125.

Return to the Summary Table.

RTDMA1 DW Error aggregator Error Type Clear Register

Figure 8-108 RTDMA1_DW_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0hR-0/W1C-0h
Table 8-125 RTDMA1_DW_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-8RESERVEDR0hReserved
7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1C0hSecurity violation flag clear register
0 - No action
1 - Clear Security violation flag

Reset type: PORESETn

8.9.3.101 RTDMA2_DR_HIGHPRIO_ERROR_ADDRESS Register (Offset = 800h) [Reset = 00000000h]

RTDMA2_DR_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-109 and described in Table 8-126.

Return to the Summary Table.

RTDMA2 DR Error aggregator High Priority Error address register

Figure 8-109 RTDMA2_DR_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
RTDMA2_DR_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-126 RTDMA2_DR_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0RTDMA2_DR_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on RTDMA2_DR access

Reset type: PORESETn

8.9.3.102 RTDMA2_DR_LOWPRIO_ERROR_ADDRESS Register (Offset = 804h) [Reset = 00000000h]

RTDMA2_DR_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-110 and described in Table 8-127.

Return to the Summary Table.

RTDMA2 DR Error aggregator Low Priority Error address register

Figure 8-110 RTDMA2_DR_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
RTDMA2_DR_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-127 RTDMA2_DR_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0RTDMA2_DR_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on RTDMA2_DR access

Reset type: PORESETn

8.9.3.103 RTDMA2_DR_ERROR_TYPE Register (Offset = 808h) [Reset = 00000000h]

RTDMA2_DR_ERROR_TYPE is shown in Figure 8-111 and described in Table 8-128.

Return to the Summary Table.

RTDMA2 DR Error aggregator Error Type Register

Figure 8-111 RTDMA2_DR_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-128 RTDMA2_DR_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hlow priority software error set by software

Reset type: PORESETn

29-8RESERVEDR0hReserved
7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0hUncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0hAccess timeout error

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR0hSecurity violation

Reset type: PORESETn

8.9.3.104 RTDMA2_DR_ERROR_TYPE_FRC Register (Offset = 80Ch) [Reset = 00000000h]

RTDMA2_DR_ERROR_TYPE_FRC is shown in Figure 8-112 and described in Table 8-129.

Return to the Summary Table.

RTDMA2 DR Error aggregator Error Type Force Register

Figure 8-112 RTDMA2_DR_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0h
Table 8-129 RTDMA2_DR_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-8RESERVEDR0hReserved
7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1S0hSecurity violation flag force register
0 - No action
1 - force Security violation flag

Reset type: PORESETn

8.9.3.105 RTDMA2_DR_ERROR_TYPE_CLR Register (Offset = 810h) [Reset = 00000000h]

RTDMA2_DR_ERROR_TYPE_CLR is shown in Figure 8-113 and described in Table 8-130.

Return to the Summary Table.

RTDMA2 DR Error aggregator Error Type Clear Register

Figure 8-113 RTDMA2_DR_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0hR-0/W1C-0h
Table 8-130 RTDMA2_DR_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-8RESERVEDR0hReserved
7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1C0hSecurity violation flag clear register
0 - No action
1 - Clear Security violation flag

Reset type: PORESETn

8.9.3.106 RTDMA2_DW_HIGHPRIO_ERROR_ADDRESS Register (Offset = 840h) [Reset = 00000000h]

RTDMA2_DW_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-114 and described in Table 8-131.

Return to the Summary Table.

RTDMA2 DW Error aggregator High Priority Error address register

Figure 8-114 RTDMA2_DW_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
RTDMA2_DW_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-131 RTDMA2_DW_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0RTDMA2_DW_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on RTDMA2_DW access

Reset type: PORESETn

8.9.3.107 RTDMA2_DW_LOWPRIO_ERROR_ADDRESS Register (Offset = 844h) [Reset = 00000000h]

RTDMA2_DW_LOWPRIO_ERROR_ADDRESS is shown in Figure 8-115 and described in Table 8-132.

Return to the Summary Table.

RTDMA2 DW Error aggregator Low Priority Error address register

Figure 8-115 RTDMA2_DW_LOWPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
RTDMA2_DW_LOWPRIO_ERROR_ADDRESS
R-0h
Table 8-132 RTDMA2_DW_LOWPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0RTDMA2_DW_LOWPRIO_ERROR_ADDRESSR0hAddress at which first low priority error occurred on RTDMA2_DW access

Reset type: PORESETn

8.9.3.108 RTDMA2_DW_ERROR_TYPE Register (Offset = 848h) [Reset = 00000000h]

RTDMA2_DW_ERROR_TYPE is shown in Figure 8-116 and described in Table 8-133.

Return to the Summary Table.

RTDMA2 DW Error aggregator Error Type Register

Figure 8-116 RTDMA2_DW_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-133 RTDMA2_DW_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30LP_SOFTWARE_ERRR0hLow priority error set by software

Reset type: PORESETn

29-8RESERVEDR0hReserved
7CERRR0hCorrectable error

Reset type: PORESETn

6UNCERRR0hUncorrectable error

Reset type: PORESETn

5ACC_ACK_ERRR0hAccess ACK error

Reset type: PORESETn

4ACC_TIMEOUT_ERRR0hAccess timeout error

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR0hSecurity violation

Reset type: PORESETn

8.9.3.109 RTDMA2_DW_ERROR_TYPE_FRC Register (Offset = 84Ch) [Reset = 00000000h]

RTDMA2_DW_ERROR_TYPE_FRC is shown in Figure 8-117 and described in Table 8-134.

Return to the Summary Table.

RTDMA2 DW Error aggregator Error Type Force Register

Figure 8-117 RTDMA2_DW_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0h
Table 8-134 RTDMA2_DW_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1S0hForce low priority software error
0 - No action
1 - force low priority software error

Reset type: PORESETn

29-8RESERVEDR0hReserved
7CERRR-0/W1S0hCorrectable error flag force register
0 - No action
1 - force Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1S0hAccess ACK error flag force register
0 - No action
1 - force Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1S0hAccess timeout error flag force register
0 - No action
1 - force Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1S0hSecurity violation flag force register
0 - No action
1 - force Security violation flag

Reset type: PORESETn

8.9.3.110 RTDMA2_DW_ERROR_TYPE_CLR Register (Offset = 850h) [Reset = 00000000h]

RTDMA2_DW_ERROR_TYPE_CLR is shown in Figure 8-118 and described in Table 8-135.

Return to the Summary Table.

RTDMA2 DW Error aggregator Error Type Clear Register

Figure 8-118 RTDMA2_DW_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRLP_SOFTWARE_ERRRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CERRUNCERRACC_ACK_ERRACC_TIMEOUT_ERRRESERVEDSECURITY_VIO
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0hR-0/W1C-0h
Table 8-135 RTDMA2_DW_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30LP_SOFTWARE_ERRR-0/W1C0hclear low priority software error
0 - No action
1 - clear low priority software error

Reset type: PORESETn

29-8RESERVEDR0hReserved
7CERRR-0/W1C0hCorrectable error flag clear register
0 - No action
1 - Clear Correctable error flag

Reset type: PORESETn

6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5ACC_ACK_ERRR-0/W1C0hAccess ACK error flag clear register
0 - No action
1 - Clear Access ACK error flag

Reset type: PORESETn

4ACC_TIMEOUT_ERRR-0/W1C0hAccess timeout error flag clear register
0 - No action
1 - Clear Access timeout error flag

Reset type: PORESETn

3-1RESERVEDR0hReserved
0SECURITY_VIOR-0/W1C0hSecurity violation flag clear register
0 - No action
1 - Clear Security violation flag

Reset type: PORESETn

8.9.3.111 SSU_HIGHPRIO_ERROR_ADDRESS Register (Offset = 880h) [Reset = 00000000h]

SSU_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-119 and described in Table 8-136.

Return to the Summary Table.

SSU Error aggregator High Priority Error address register

Figure 8-119 SSU_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
SSU_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-136 SSU_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0SSU_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first high priority SSU error occurred

Reset type: PORESETn

8.9.3.112 SSU_ERROR_TYPE Register (Offset = 888h) [Reset = 00000000h]

SSU_ERROR_TYPE is shown in Figure 8-120 and described in Table 8-137.

Return to the Summary Table.

SSU Error aggregator Error Type Register

Figure 8-120 SSU_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRRESERVEDRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVEDFLC2_MMR_ACCESS_ERRORFLC2_ERROR_TYPE
R-0hR-0hR-0h
15141312111098
FLC2_ERROR_TYPEFLC2_ERROR_STSFLC1_MMR_ACCESS_ERRORFLC1_ERROR_TYPEFLC1_ERROR_STS
R-0hR-0hR-0hR-0hR-0h
76543210
MODE_INVALIDRESERVEDCPU3_SSU_MMR_ACCESS_ERRORCPU2_SSU_MMR_ACCESS_ERRORCPU1_SSU_MMR_ACCESS_ERRORRESERVED
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-137 SSU_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30RESERVEDR0hReserved
29-18RESERVEDR0hReserved
17FLC2_MMR_ACCESS_ERRORR0hFLC2_MMR_ACCESS_ERROR

Reset type: PORESETn

16-14FLC2_ERROR_TYPER0hFLC2_ERROR type
0x0: FLC2_ILLADDR
0x1: FLC2_ILLPROG
0x2: FLC2_ILLERASE
0x3: FLC2_ILLRDVER
0x4: FLC2_ILLMODECH
0x5: FLC2_ILLCMD
0x6: FLC2_ILLSIZE
0x7: FLC2_ILLBANKERASE
Note: SSU_ERROR_TYPE.FLC2_ERROR_TYPE register will not get updated on further FLC2 errors until the SSU_ERROR_TYPE.FLC2_ERROR_TYPE bits are cleared.

Reset type: PORESETn

13FLC2_ERROR_STSR0hFLC2_ERROR status

Reset type: PORESETn

12FLC1_MMR_ACCESS_ERRORR0hFLC1_MMR_ACCESS_ERROR

Reset type: PORESETn

11-9FLC1_ERROR_TYPER0hFLC1_ERROR type register
0x0: FLC1_ILLADDR
0x1: FLC1_ILLPROG
0x2: FLC1_ILLERASE
0x3: FLC1_ILLRDVER
0x4: FLC1_ILLMODECH
0x5: FLC1_ILLCMD
0x6: FLC1_ILLSIZE
0x7: FLC1_ILLBANKERASE
Note: SSU_ERROR_TYPE.FLC1_ERROR_TYPE register will not get updated on further FLC1 errors until the SSU_ERROR_TYPE.FLC1_ERROR_TYPE bits are cleared.

Reset type: PORESETn

8FLC1_ERROR_STSR0hFLC1_ERROR status

Reset type: PORESETn

7MODE_INVALIDR0hBANKMAP, SECVALID, BANKMODE, SSUMODE invalid

Reset type: PORESETn

6-4RESERVEDR0hReserved
3CPU3_SSU_MMR_ACCESS_ERRORR0hCPU3_SSU_MMR_ACCESS_ERROR

Reset type: PORESETn

2CPU2_SSU_MMR_ACCESS_ERRORR0hCPU2_SSU_MMR_ACCESS_ERROR

Reset type: PORESETn

1CPU1_SSU_MMR_ACCESS_ERRORR0hCPU1_SSU_MMR_ACCESS_ERROR

Reset type: PORESETn

0RESERVEDR0hReserved

8.9.3.113 SSU_ERROR_TYPE_FRC Register (Offset = 88Ch) [Reset = 00000000h]

SSU_ERROR_TYPE_FRC is shown in Figure 8-121 and described in Table 8-138.

Return to the Summary Table.

SSU Error aggregator Error Type Force Register

Figure 8-121 SSU_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRRESERVEDRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVEDFLC2_MMR_ACCESS_ERRORFLC2_ERROR_TYPE
R-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
FLC2_ERROR_TYPEFLC2_ERROR_STSFLC1_MMR_ACCESS_ERRORFLC1_ERROR_TYPEFLC1_ERROR_STS
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
MODE_INVALIDRESERVEDCPU3_SSU_MMR_ACCESS_ERRORCPU2_SSU_MMR_ACCESS_ERRORCPU1_SSU_MMR_ACCESS_ERRORRESERVED
R-0/W1S-0hR-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0h
Table 8-138 SSU_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30RESERVEDR-0/W1S0hReserved
29-18RESERVEDR0hReserved
17FLC2_MMR_ACCESS_ERRORR-0/W1S0hFLC2_MMR_ACCESS_ERROR force register
0 - No action
1 - forces corresponding error type flag

Reset type: PORESETn

16-14FLC2_ERROR_TYPER-0/W1S0hFLC2_ERROR type force register
0 - No action
1 - forces corresponding error type flag
Note: SSU_ERROR_TYPE_FRC.FLC2_ERROR_STS should also be written along with writing SSU_ERROR_TYPE_FRC.FLC2_ERROR_TYPE to force any of the FLC2 errors

Reset type: PORESETn

13FLC2_ERROR_STSR-0/W1S0hFLC2_ERROR status force register
0 - No action
1 - forces corresponding error type flag

Reset type: PORESETn

12FLC1_MMR_ACCESS_ERRORR-0/W1S0hFLC1_MMR_ACCESS_ERROR force register
0 - No action
1 - forces corresponding error type flag

Reset type: PORESETn

11-9FLC1_ERROR_TYPER-0/W1S0hFLC1_ERROR type force register
0 - No action
1 - forces corresponding error type flag
Note: SSU_ERROR_TYPE_FRC.FLC1_ERROR_STS should also be written along with writing SSU_ERROR_TYPE_FRC.FLC1_ERROR_TYPE to force any of the FLC1 errors

Reset type: PORESETn

8FLC1_ERROR_STSR-0/W1S0hFLC1_ERROR status force register
0 - No action
1 - forces corresponding error type flag

Reset type: PORESETn

7MODE_INVALIDR-0/W1S0hBANKMAP, SECVALID, BANKMODE, SSUMODE invalid force register
0 - No action
1 - forces corresponding error type flag

Reset type: PORESETn

6-4RESERVEDR0hReserved
3CPU3_SSU_MMR_ACCESS_ERRORR-0/W1S0hCPU3_SSU_MMR_ACCESS_ERROR force register
0 - No action
1 - forces corresponding error type flag

Reset type: PORESETn

2CPU2_SSU_MMR_ACCESS_ERRORR-0/W1S0hCPU2_SSU_MMR_ACCESS_ERROR force register
0 - No action
1 - forces corresponding error type flag

Reset type: PORESETn

1CPU1_SSU_MMR_ACCESS_ERRORR-0/W1S0hCPU1_SSU_MMR_ACCESS_ERROR force register
0 - No action
1 - forces corresponding error type flag

Reset type: PORESETn

0RESERVEDR0hReserved

8.9.3.114 SSU_ERROR_TYPE_CLR Register (Offset = 890h) [Reset = 00000000h]

SSU_ERROR_TYPE_CLR is shown in Figure 8-122 and described in Table 8-139.

Return to the Summary Table.

SSU Error aggregator Error Type Clear Register

Figure 8-122 SSU_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRRESERVEDRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVEDFLC2_MMR_ACCESS_ERRORFLC2_ERROR_TYPE
R-0hR-0/W1C-0hR-0/W1C-0h
15141312111098
FLC2_ERROR_TYPEFLC2_ERROR_STSFLC1_MMR_ACCESS_ERRORFLC1_ERROR_TYPEFLC1_ERROR_STS
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
76543210
MODE_INVALIDRESERVEDCPU3_SSU_MMR_ACCESS_ERRORCPU2_SSU_MMR_ACCESS_ERRORCPU1_SSU_MMR_ACCESS_ERRORRESERVED
R-0/W1C-0hR-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0h
Table 8-139 SSU_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30RESERVEDR-0/W1C0hReserved
29-18RESERVEDR0hReserved
17FLC2_MMR_ACCESS_ERRORR-0/W1C0hFLC2_MMR_ACCESS_ERROR clear register
0 - No action
1 - Clears corresponding error type flag

Reset type: PORESETn

16-14FLC2_ERROR_TYPER-0/W1C0hFLC2_ERROR type clear register
0 - No action
1 - Clears corresponding error type flag
Note: SSU_ERROR_TYPE_CLR.FLC2_ERROR_STS should also be written along with writing corresponding value in SSU_ERROR_TYPE_CLR.FLC2_ERROR_TYPE to clear the FLC2 errors

Reset type: PORESETn

13FLC2_ERROR_STSR-0/W1C0hFLC2_ERROR status clear register
0 - No action
1 - Clears corresponding error type flag

Reset type: PORESETn

12FLC1_MMR_ACCESS_ERRORR-0/W1C0hFLC1_MMR_ACCESS_ERROR clear register
0 - No action
1 - Clears corresponding error type flag

Reset type: PORESETn

11-9FLC1_ERROR_TYPER-0/W1C0hFLC1_ERROR type clear register
0 - No action
1 - Clears corresponding error type flag
Note: SSU_ERROR_TYPE_CLR.FLC1_ERROR_STS should also be written along with writing corresponding value in SSU_ERROR_TYPE_CLR.FLC1_ERROR_TYPE to clear the FLC1 errors

Reset type: PORESETn

8FLC1_ERROR_STSR-0/W1C0hFLC1_ERROR status clear register
0 - No action
1 - Clears corresponding error type flag

Reset type: PORESETn

7MODE_INVALIDR-0/W1C0hBANKMAP, SECVALID, BANKMODE, SSUMODE invalid clear register
0 - No action
1 - Clears corresponding error type flag

Reset type: PORESETn

6-4RESERVEDR0hReserved
3CPU3_SSU_MMR_ACCESS_ERRORR-0/W1C0hCPU3_SSU_MMR_ACCESS_ERROR clear register
0 - No action
1 - Clears corresponding error type flag

Reset type: PORESETn

2CPU2_SSU_MMR_ACCESS_ERRORR-0/W1C0hCPU2_SSU_MMR_ACCESS_ERROR clear register
0 - No action
1 - Clears corresponding error type flag

Reset type: PORESETn

1CPU1_SSU_MMR_ACCESS_ERRORR-0/W1C0hCPU1_SSU_MMR_ACCESS_ERROR clear register
0 - No action
1 - Clears corresponding error type flag

Reset type: PORESETn

0RESERVEDR0hReserved

8.9.3.115 ETHERCAT_HIGHPRIO_ERROR_ADDRESS Register (Offset = 8C0h) [Reset = 00000000h]

ETHERCAT_HIGHPRIO_ERROR_ADDRESS is shown in Figure 8-123 and described in Table 8-140.

Return to the Summary Table.

ETHERCAT Error aggregator High Priority Error address register

Figure 8-123 ETHERCAT_HIGHPRIO_ERROR_ADDRESS Register
313029282726252423222120191817161514131211109876543210
ETHERCAT_HIGHPRIO_ERROR_ADDRESS
R-0h
Table 8-140 ETHERCAT_HIGHPRIO_ERROR_ADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0ETHERCAT_HIGHPRIO_ERROR_ADDRESSR0hAddress at which first High priority error occurred on ETHERCAT access

Reset type: PORESETn

8.9.3.116 ETHERCAT_ERROR_TYPE Register (Offset = 8C8h) [Reset = 00000000h]

ETHERCAT_ERROR_TYPE is shown in Figure 8-124 and described in Table 8-141.

Return to the Summary Table.

ETHERCAT Error aggregator Error Type Register

Figure 8-124 ETHERCAT_ERROR_TYPE Register
3130292827262524
HP_SOFTWARE_ERRRESERVEDRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDUNCERRRESERVED
R-0hR-0hR-0h
Table 8-141 ETHERCAT_ERROR_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR0hhigh priority error set by software

Reset type: PORESETn

30RESERVEDR0hReserved
29-7RESERVEDR0hReserved
6UNCERRR0hUncorrectable error

Reset type: PORESETn

5-0RESERVEDR0hReserved

8.9.3.117 ETHERCAT_ERROR_TYPE_FRC Register (Offset = 8CCh) [Reset = 00000000h]

ETHERCAT_ERROR_TYPE_FRC is shown in Figure 8-125 and described in Table 8-142.

Return to the Summary Table.

ETHERCAT Error aggregator Error Type Force Register

Figure 8-125 ETHERCAT_ERROR_TYPE_FRC Register
3130292827262524
HP_SOFTWARE_ERRRESERVEDRESERVED
R-0/W1S-0hR-0/W1S-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDUNCERRRESERVED
R-0hR-0/W1S-0hR-0h
Table 8-142 ETHERCAT_ERROR_TYPE_FRC Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1S0hforce high priority software error
0 - No action
1 - force high priority software error

Reset type: PORESETn

30RESERVEDR-0/W1S0hReserved
29-7RESERVEDR0hReserved
6UNCERRR-0/W1S0hUncorrectable error flag force register
0 - No action
1 - force Uncorrectable error flag

Reset type: PORESETn

5-0RESERVEDR0hReserved

8.9.3.118 ETHERCAT_ERROR_TYPE_CLR Register (Offset = 8D0h) [Reset = 00000000h]

ETHERCAT_ERROR_TYPE_CLR is shown in Figure 8-126 and described in Table 8-143.

Return to the Summary Table.

ETHERCAT Error aggregator Error Type Clear Register

Figure 8-126 ETHERCAT_ERROR_TYPE_CLR Register
3130292827262524
HP_SOFTWARE_ERRRESERVEDRESERVED
R-0/W1C-0hR-0/W1C-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDUNCERRRESERVED
R-0hR-0/W1C-0hR-0h
Table 8-143 ETHERCAT_ERROR_TYPE_CLR Register Field Descriptions
BitFieldTypeResetDescription
31HP_SOFTWARE_ERRR-0/W1C0hClear high priority software error
0 - No action
1 - clear high priority software error

Reset type: PORESETn

30RESERVEDR-0/W1C0hReserved
29-7RESERVEDR0hReserved
6UNCERRR-0/W1C0hUncorrectable error flag clear register
0 - No action
1 - Clear Uncorrectable error flag

Reset type: PORESETn

5-0RESERVEDR0hReserved