SPRUJ79 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 â–º C29x SYSTEM RESOURCES
    1.     Technical Reference Manual Overview
  4. 2 F29x Processor
    1. 2.1 CPU Architecture
      1. 2.1.1 C29x Related Collateral
    2. 2.2 Lock and Commit Registers
    3. 2.3 C29x CPU Registers
      1. 2.3.1 C29CPU Base Address Table
      2. 2.3.2 C29_RTINT_STACK Registers
      3. 2.3.3 C29_SECCALL_STACK Registers
      4. 2.3.4 C29_SECURE_REGS Registers
      5. 2.3.5 C29_DIAG_REGS Registers
      6. 2.3.6 C29_SELFTEST_REGS Registers
  5. 3 System Control and Interrupts
    1. 3.1  C29x System Control Introduction
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
      2. 3.2.2 Device Configuration Registers
    3. 3.3  Resets
      1. 3.3.1 Reset Sources
      2. 3.3.2 External Reset (XRS)
      3. 3.3.3 Simulate External Reset
      4. 3.3.4 Power-On Reset (POR)
      5. 3.3.5 Debugger Reset (SYSRS)
      6. 3.3.6 Watchdog Reset (WDRS)
      7. 3.3.7 ESM NMI Watchdog Reset (NMIWDRS)
      8. 3.3.8 EtherCAT Slave Controller (ESC) Module Reset Output
    4. 3.4  Safety Features
      1. 3.4.1 Write Protection on Registers
        1. 3.4.1.1 LOCK Protection on System Configuration Registers
        2. 3.4.1.2 EALLOW Protection
      2. 3.4.2 PIPE Vector Address Validity Check
      3. 3.4.3 NMIWDs
      4. 3.4.4 System Control Registers Parity Protection
      5. 3.4.5 ECC Enabled RAMs, Shared RAMs Protection
      6. 3.4.6 ECC Enabled Flash Memory
      7. 3.4.7 ERRORSTS Pin
    5. 3.5  Clocking
      1. 3.5.1 Clock Sources
        1. 3.5.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.5.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.5.1.3 External Oscillator (XTAL)
        4. 3.5.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.5.2 Derived Clocks
        1. 3.5.2.1 Oscillator Clock (OSCCLK)
        2. 3.5.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.5.3 Device Clock Domains
        1. 3.5.3.1 System Clock (PLLSYSCLK)
        2. 3.5.3.2 CPU Clock (CPUCLK)
        3. 3.5.3.3 Peripheral Clock (PERx.SYSCLK)
        4. 3.5.3.4 MCAN Bit Clock
        5. 3.5.3.5 CPU Timer2 Clock (TIMER2CLK)
      4. 3.5.4 External Clock Output (XCLKOUT)
      5. 3.5.5 Clock Connectivity
      6. 3.5.6 Using an External Crystal or Resonator
        1. 3.5.6.1 X1/X2 Precondition Circuit
      7. 3.5.7 PLL
        1. 3.5.7.1 System Clock Setup
        2. 3.5.7.2 SYS PLL Bypass
      8. 3.5.8 Clock (OSCCLK) Failure Detection
        1. 3.5.8.1 Missing Clock Detection Logic
        2. 3.5.8.2 Dual Clock Comparator (DCC)
    6. 3.6  Bus Architecture
      1. 3.6.1 Safe Interconnect
        1. 3.6.1.1 Safe Interconnect for Read Operation
        2. 3.6.1.2 Safe Interconnect for Write Operation
      2. 3.6.2 Peripheral Access Configuration using FRAMESEL
      3. 3.6.3 Bus Arbitration
    7. 3.7  32-Bit CPU Timers 0/1/2
    8. 3.8  Watchdog Timers
      1. 3.8.1 Servicing the Watchdog Timer
      2. 3.8.2 Minimum Window Check
      3. 3.8.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.8.4 Watchdog Operation in Low-Power Modes
      5. 3.8.5 Emulation Considerations
    9. 3.9  Low-Power Modes
      1. 3.9.1 IDLE
      2. 3.9.2 STANDBY
    10. 3.10 Memory Subsystem (MEMSS)
      1. 3.10.1 Introduction
      2. 3.10.2 Features
      3. 3.10.3 Configuration Bits
        1. 3.10.3.1 Memory Initialization
      4. 3.10.4 RAM
        1. 3.10.4.1  MEMSS Architecture
        2. 3.10.4.2  RAM Memory Controller Overview
        3. 3.10.4.3  Memory Controllers
          1. 3.10.4.3.1 128-Bit LPx and CPx Memory Controller
          2. 3.10.4.3.2 64-Bit LDx and CDx Memory Controller
          3. 3.10.4.3.3 M0 Memory Controller
        4. 3.10.4.4  RTDMA Burst Support
        5. 3.10.4.5  Atomic Memory Operations
        6. 3.10.4.6  RAM ECC
        7. 3.10.4.7  Read-Modify-Write Operations
        8. 3.10.4.8  Dataline Buffer
        9. 3.10.4.9  HSM Sync Bridge
        10. 3.10.4.10 Access Bridges
          1. 3.10.4.10.1 Debug Access Bridge
          2. 3.10.4.10.2 Global Access Bridge
          3. 3.10.4.10.3 Program Access Bridge
      5. 3.10.5 ROM
        1. 3.10.5.1 ROM Dataline Buffer
        2. 3.10.5.2 ROM Prefetch
      6. 3.10.6 Arbitration
      7. 3.10.7 Test Modes
      8. 3.10.8 Emulation Mode
    11. 3.11 System Control Register Configuration Restrictions
    12. 3.12 Software
      1. 3.12.1  SYSCTL Registers to Driverlib Functions
      2. 3.12.2  MEMSS Registers to Driverlib Functions
      3. 3.12.3  CPU Registers to Driverlib Functions
      4. 3.12.4  WD Registers to Driverlib Functions
      5. 3.12.5  CPUTIMER Registers to Driverlib Functions
      6. 3.12.6  XINT Registers to Driverlib Functions
      7. 3.12.7  LPOST Registers to Driverlib Functions
      8. 3.12.8  SYSCTL Examples
        1. 3.12.8.1 Missing clock detection (MCD) - SINGLE_CORE
        2. 3.12.8.2 XCLKOUT (External Clock Output) Configuration - SINGLE_CORE
      9. 3.12.9  TIMER Examples
        1. 3.12.9.1 Timer Academy Lab - SINGLE_CORE
        2. 3.12.9.2 CPU Timers - SINGLE_CORE
        3. 3.12.9.3 CPU Timers - SINGLE_CORE
      10. 3.12.10 WATCHDOG Examples
        1. 3.12.10.1 Watchdog - SINGLE_CORE
      11. 3.12.11 LPM Examples
        1. 3.12.11.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO - SINGLE_CORE
        2. 3.12.11.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog - SINGLE_CORE
        3. 3.12.11.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO - SINGLE_CORE
        4. 3.12.11.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog - SINGLE_CORE
    13. 3.13 SYSCTRL Registers
      1. 3.13.1  SYSCTRL Base Address Table
      2. 3.13.2  DEV_CFG_REGS Registers
      3. 3.13.3  MEMSS_L_CONFIG_REGS Registers
      4. 3.13.4  MEMSS_C_CONFIG_REGS Registers
      5. 3.13.5  MEMSS_M_CONFIG_REGS Registers
      6. 3.13.6  MEMSS_MISCI_REGS Registers
      7. 3.13.7  CPU_SYS_REGS Registers
      8. 3.13.8  CPU_PER_CFG_REGS Registers
      9. 3.13.9  WD_REGS Registers
      10. 3.13.10 CPUTIMER_REGS Registers
      11. 3.13.11 XINT_REGS Registers
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Device Boot Flow
      2. 4.5.2 CPU1 Boot Flow
      3. 4.5.3 Emulation Boot Flow
      4. 4.5.4 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 MPOST and LPOST Configurations
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Memory Maps
        1. 4.7.4.1 Boot ROM Memory-Maps
        2. 4.7.4.2 Reserved RAM Memory-Maps
      5. 4.7.5  ROM Structure and Status Information
      6. 4.7.6  Boot Modes and Loaders
        1. 4.7.6.1 Boot Modes
          1. 4.7.6.1.1 Flash Boot
          2. 4.7.6.1.2 RAM Boot
          3. 4.7.6.1.3 Wait Boot
        2. 4.7.6.2 Bootloaders
          1. 4.7.6.2.1 SPI Boot Mode
          2. 4.7.6.2.2 I2C Boot Mode
          3. 4.7.6.2.3 Parallel Boot Mode
          4. 4.7.6.2.4 CAN Boot Mode
          5. 4.7.6.2.5 CAN-FD Boot Mode
          6. 4.7.6.2.6 UART Boot Mode
      7. 4.7.7  GPIO Assignments
      8. 4.7.8  HSM and C29 ROM Task Ownership and Interactions
        1. 4.7.8.1 Application Authentication by HSM
      9. 4.7.9  Boot Status Information
        1. 4.7.9.1 Booting Status
      10. 4.7.10 BootROM Timing
    8. 4.8 Software
      1. 4.8.1 BOOT Examples
  7. 5 Lockstep Compare Module (LCM)
    1. 5.1 Introduction
      1. 5.1.1 Features
      2. 5.1.2 Block Diagram
      3. 5.1.3 Lockstep Compare Modules
    2. 5.2 Enabling LCM Comparators
    3. 5.3 LCM Redundant Module Configuration
    4. 5.4 LCM Error Handling
    5. 5.5 Debug Mode with LCM
    6. 5.6 Register Parity Error Protection
    7. 5.7 Functional Logic
      1. 5.7.1 Comparator Logic
      2. 5.7.2 Self-Test Logic
        1. 5.7.2.1 Match Test Mode
        2. 5.7.2.2 Mismatch Test Mode
      3. 5.7.3 Error Injection Tests
        1. 5.7.3.1 Comparator Error Force Test
        2. 5.7.3.2 Register Parity Error Test
    8. 5.8 Software
      1. 5.8.1 LCM Registers to Driverlib Functions
    9. 5.9 LCM Registers
      1. 5.9.1 LCM Base Address Table
      2. 5.9.2 LCM_REGS Registers
  8. 6 Peripheral Interrupt Priority and Expansion (PIPE)
    1. 6.1 Introduction
      1. 6.1.1 Features
      2. 6.1.2 Interrupt Concepts
      3. 6.1.3 PIPE Related Collateral
    2. 6.2 Interrupt Architecture
      1. 6.2.1 Dynamic Priority Arbitration Block
      2. 6.2.2 Post Processing Block
      3. 6.2.3 Memory-Mapped Registers
    3. 6.3 Interrupt Propagation
    4. 6.4 Configuring Interrupts
      1. 6.4.1 Enabling and Disabling Interrupts
      2. 6.4.2 Prioritization
        1. 6.4.2.1 User-Configured Interrupt Priority
        2. 6.4.2.2 Index-Based Fixed Interrupt Priority
      3. 6.4.3 Nesting and Priority Grouping
      4. 6.4.4 Stack Protection
      5. 6.4.5 Context
    5. 6.5 Safety and Security
      1. 6.5.1 Access Control
      2. 6.5.2 PIPE Errors
      3. 6.5.3 Register Data Integrity and Safety
      4. 6.5.4 Self-Test and Diagnostics
    6. 6.6 Software
      1. 6.6.1 PIPE Registers to Driverlib Functions
      2. 6.6.2 INTERRUPT Examples
        1. 6.6.2.1 RTINT vs INT Latency example - SINGLE_CORE
        2. 6.6.2.2 INT and RTINT Nesting Example - SINGLE_CORE
    7. 6.7 PIPE Registers
      1. 6.7.1 PIPE Base Address Table
      2. 6.7.2 PIPE_REGS Registers
  9. 7  Error Signaling Module (ESM_C29)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 ESM Related Collateral
    2. 7.2 ESM Subsystem
      1. 7.2.1 System ESM
        1. 7.2.1.1 Error Pin Monitor Event
      2. 7.2.2 Safety Aggregator
        1. 7.2.2.1 EDC Controller Interface Description
          1. 7.2.2.1.1 EDC_REGS Registers
        2. 7.2.2.2 Read Operation on EDC Controller
        3. 7.2.2.3 Write Operation on EDC Controller
        4. 7.2.2.4 Safety Aggregator Error Injection
      3. 7.2.3 ESM Subsystem Integration View
    3. 7.3 ESM Functional Description
      1. 7.3.1 Error Event Inputs
      2. 7.3.2 Error Interrupt Outputs
        1. 7.3.2.1 High Priority Watchdog
        2. 7.3.2.2 Critical Priority Interrupt Output
      3. 7.3.3 Error Pin Output (ERR_O/ERRORSTS)
        1. 7.3.3.1 Minimum Time Interval
        2. 7.3.3.2 PWM Mode
      4. 7.3.4 Reset Type Information for ESM Registers
      5. 7.3.5 Clock Stop
      6. 7.3.6 Commit/Lock for MMRs
      7. 7.3.7 Safety Protection for MMRs
      8. 7.3.8 Register Configuration Tieoffs
        1. 7.3.8.1 Group0 High Priority Tieoff
        2. 7.3.8.2 High Priority Watchdog Enable Tieoff
    4. 7.4 ESM Configuration Guide
    5. 7.5 Interrupt Condition Control and Handling
      1. 7.5.1 ESM Low Priority Error Interrupt
      2. 7.5.2 ESM High Priority Error Interrupt
      3. 7.5.3 Critical Priority Error Interrupt
      4. 7.5.4 High Priority Watchdog Interrupt
      5. 7.5.5 Safety Aggregator Interrupt Control and Handling
    6. 7.6 Software
      1. 7.6.1 ESM_CPU Registers to Driverlib Functions
      2. 7.6.2 ESM_SYS Registers to Driverlib Functions
      3. 7.6.3 ESM_SAFETY_AGGREGATOR Registers to Driverlib Functions
      4. 7.6.4 ESM Examples
        1. 7.6.4.1 ESM Multicore Example (CPU1,CPU3) - MULTI_CORE
        2. 7.6.4.2 ESM Multicore Example (CPU1,CPU3) - MULTI_CORE
        3. 7.6.4.3 ESM - SINGLE_CORE
        4. 7.6.4.4 ESM - SINGLE_CORE
    7. 7.7 ESM Registers
      1. 7.7.1 ESM Base Address Table
      2. 7.7.2 ESM_CPU_REGS Registers
      3. 7.7.3 ESM_SYSTEM_REGS Registers
      4. 7.7.4 ESM_SAFETYAGG_REGS Registers
  10. 8  Error Aggregator
    1. 8.1 Introduction
    2. 8.2 Error Aggregator Modules
    3. 8.3 Error Propagation Path from Source to CPU
    4. 8.4 Error Aggregator Interface
      1. 8.4.1 Functional Description
    5. 8.5 Error Condition Handling User Guide
    6. 8.6 Error Type Information
    7. 8.7 Error Sources Information
    8. 8.8 Software
      1. 8.8.1 ERROR_AGGREGATOR Registers to Driverlib Functions
    9. 8.9 ERRORAGGREGATOR Registers
      1. 8.9.1 ERRORAGGREGATOR Base Address Table
      2. 8.9.2 HSM_ERROR_AGGREGATOR_CONFIG_REGS Registers
      3. 8.9.3 ERROR_AGGREGATOR_CONFIG_REGS Registers
  11. 9 Flash Module
    1. 9.1 Introduction to Flash Memory
      1. 9.1.1 FLASH Related Collateral
      2. 9.1.2 Features
      3. 9.1.3 Flash Tools
      4. 9.1.4 Block Diagram
    2. 9.2 Flash Subsystem Overview
    3. 9.3 Flash Banks and Pumps
    4. 9.4 Flash Read Interfaces
      1. 9.4.1 Bank Modes and Swapping
      2. 9.4.2 Flash Wait States
      3. 9.4.3 Buffer and Cache Mechanisms
        1. 9.4.3.1 Prefetch Mechanism and Block Cache
        2. 9.4.3.2 Data Line Buffer
        3. 9.4.3.3 Sequential Data Pre-read Mode
      4. 9.4.4 Flash Read Arbitration
      5. 9.4.5 Error Correction Code (ECC) Protection
      6. 9.4.6 Procedure to Change Flash Read Interface Registers
    5. 9.5 Flash Erase and Program
      1. 9.5.1 Flash Semaphore and Update Protection
      2. 9.5.2 Erase
      3. 9.5.3 Program
    6. 9.6 Migrating an Application from RAM to Flash
    7. 9.7 Flash Registers
      1. 9.7.1 FLASH Base Address Table
      2. 9.7.2 FLASH_CMD_REGS_FLC1 Registers
      3. 9.7.3 FLASH_CMD_REGS_FLC2 Registers
      4. 9.7.4 FRI_CTRL_REGS Registers
  12. 10Safety and Security Unit (SSU)
    1. 10.1  Introduction
      1. 10.1.1 SSU Related Collateral
      2. 10.1.2 Block Diagram
      3. 10.1.3 System SSU Configuration Example
    2. 10.2  Access Protection Ranges
      1. 10.2.1 Access Protection Inheritance
    3. 10.3  LINKs
    4. 10.4  STACKs
    5. 10.5  ZONEs
    6. 10.6  SSU-CPU Interface
      1. 10.6.1 SSU Operation in Lockstep Mode
    7. 10.7  SSU Operation Modes
    8. 10.8  Security Configuration and Flash Management
      1. 10.8.1 BANKMGMT Sectors
      2. 10.8.2 SECCFG Sectors
      3. 10.8.3 SECCFG Sector Address Mapping
      4. 10.8.4 SECCFG Sector Memory Map
      5. 10.8.5 SECCFG CRC
    9. 10.9  Flash Write/Erase Access Control
      1. 10.9.1 Permanent Flash Lock (Write/Erase Protection)
      2. 10.9.2 Updating Flash MAIN Sectors
      3. 10.9.3 Firmware-Over-The-Air Updates (FOTA)
      4. 10.9.4 Updating Flash SECCFG Sectors
      5. 10.9.5 Reading Flash SECCFG Sectors
    10. 10.10 RAMOPEN Feature
    11. 10.11 Debug Authorization
      1. 10.11.1 Global CPU Debug Enable
      2. 10.11.2 ZONE Debug
      3. 10.11.3 Authentication for Debug Access
        1. 10.11.3.1 Password-based Authentication
        2. 10.11.3.2 CPU-based Authentication
    12. 10.12 Hardcoded Protections
    13. 10.13 SSU Register Access Permissions
      1. 10.13.1 Permissions for SSU General Control Registers
      2. 10.13.2 Permissions for SSU CPU1 Configuration Registers
      3. 10.13.3 Permissions for SSU CPU2+ Configuration Registers
      4. 10.13.4 Permissions for CPU1 Access Protection Registers
      5. 10.13.5 Permissions for CPU2+ Access Protection Registers
    14. 10.14 SSU Fault Signals
    15. 10.15 Software
      1. 10.15.1 SSU Registers to Driverlib Functions
    16. 10.16 SSU Registers
      1. 10.16.1 SSU Base Address Table
      2. 10.16.2 SSU_GEN_REGS Registers
      3. 10.16.3 SSU_CPU1_CFG_REGS Registers
      4. 10.16.4 SSU_CPU2_CFG_REGS Registers
      5. 10.16.5 SSU_CPU3_CFG_REGS Registers
      6. 10.16.6 SSU_CPU1_AP_REGS Registers
      7. 10.16.7 SSU_CPU2_AP_REGS Registers
      8. 10.16.8 SSU_CPU3_AP_REGS Registers
  13. 11Configurable Logic Block (CLB)
    1. 11.1  Introduction
      1. 11.1.1 CLB Related Collateral
    2. 11.2  Description
      1. 11.2.1 CLB Clock
    3. 11.3  CLB Input/Output Connection
      1. 11.3.1 Overview
      2. 11.3.2 CLB Input Selection
      3. 11.3.3 CLB Output Selection
      4. 11.3.4 CLB Output Signal Multiplexer
    4. 11.4  CLB Tile
      1. 11.4.1 Static Switch Block
      2. 11.4.2 Counter Block
        1. 11.4.2.1 Counter Description
        2. 11.4.2.2 Counter Operation
        3. 11.4.2.3 Serializer Mode
        4. 11.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 11.4.3 FSM Block
      4. 11.4.4 LUT4 Block
      5. 11.4.5 Output LUT Block
      6. 11.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 11.4.7 High Level Controller (HLC)
        1. 11.4.7.1 High Level Controller Events
        2. 11.4.7.2 High Level Controller Instructions
        3. 11.4.7.3 <Src> and <Dest>
        4. 11.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 11.5  CPU Interface
      1. 11.5.1 Register Description
      2. 11.5.2 Non-Memory Mapped Registers
    6. 11.6  RTDMA Access
    7. 11.7  CLB Data Export Through SPI RX Buffer
    8. 11.8  CLB Pipeline Mode
    9. 11.9  Software
      1. 11.9.1 CLB Registers to Driverlib Functions
      2. 11.9.2 CLB Examples
    10. 11.10 CLB Registers
      1. 11.10.1 CLB Base Address Table
      2. 11.10.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 11.10.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 11.10.4 CLB_DATA_EXCHANGE_REGS Registers
  14. 12Dual-Clock Comparator (DCC)
    1. 12.1 Introduction
      1. 12.1.1 Features
      2. 12.1.2 Block Diagram
    2. 12.2 Module Operation
      1. 12.2.1 Configuring DCC Counters
      2. 12.2.2 Single-Shot Measurement Mode
      3. 12.2.3 Continuous Monitoring Mode
      4. 12.2.4 Error Conditions
    3. 12.3 Interrupts
    4. 12.4 Software
      1. 12.4.1 DCC Registers to Driverlib Functions
      2. 12.4.2 DCC Examples
        1. 12.4.2.1 DCC Single shot Clock verification - SINGLE_CORE
        2. 12.4.2.2 DCC Single shot Clock measurement - SINGLE_CORE
        3. 12.4.2.3 DCC Continuous clock monitoring - SINGLE_CORE
    5. 12.5 DCC Registers
      1. 12.5.1 DCC Base Address Table
      2. 12.5.2 DCC_REGS Registers
  15. 13Real-Time Direct Memory Access (RTDMA)
    1. 13.1  Introduction
      1. 13.1.1 Features
      2. 13.1.2 RTDMA Related Collateral
      3. 13.1.3 Block Diagram
    2. 13.2  RTDMA Trigger Source Options
    3. 13.3  RTDMA Bus
    4. 13.4  Address Pointer and Transfer Control
    5. 13.5  Pipeline Timing and Throughput
    6. 13.6  Channel Priority
      1. 13.6.1 Round-Robin Mode
      2. 13.6.2 Software Configurable Priority of Channels
    7. 13.7  Overrun Detection Feature
    8. 13.8  Burst Mode
    9. 13.9  Safety and Security
      1. 13.9.1 Safety
        1. 13.9.1.1 Lockstep Mode
        2. 13.9.1.2 Memory Protection Unit (MPU)
          1. 13.9.1.2.1 MPU Errors
      2. 13.9.2 Security
      3. 13.9.3 RTDMA Errors
      4. 13.9.4 Self-Test and Diagnostics
    10. 13.10 Software
      1. 13.10.1 RTDMA Registers to Driverlib Functions
      2. 13.10.2 RTDMA Examples
        1. 13.10.2.1 RTDMA Academy Lab - SINGLE_CORE
        2. 13.10.2.2 RTDMA Transfer - SINGLE_CORE
        3. 13.10.2.3 RTDMA Transfer with MPU - SINGLE_CORE
    11. 13.11 RTDMA Registers
      1. 13.11.1 RTDMA Base Address Table
      2. 13.11.2 RTDMA_REGS Registers
      3. 13.11.3 RTDMA_DIAG_REGS Registers
      4. 13.11.4 RTDMA_SELFTEST_REGS Registers
      5. 13.11.5 RTDMA_MPU_REGS Registers
      6. 13.11.6 RTDMA_CH_REGS Registers
  16. 14External Memory Interface (EMIF)
    1. 14.1 Introduction
      1. 14.1.1 Purpose of the Peripheral
      2. 14.1.2 Features
        1. 14.1.2.1 Asynchronous Memory Support
        2. 14.1.2.2 Synchronous DRAM Memory Support
      3. 14.1.3 Functional Block Diagram
      4. 14.1.4 Configuring Device Pins
    2. 14.2 EMIF Module Architecture
      1. 14.2.1  EMIF Clock Control
      2. 14.2.2  EMIF Requests
      3. 14.2.3  EMIF Signal Descriptions
      4. 14.2.4  EMIF Signal Multiplexing Control
      5. 14.2.5  SDRAM Controller and Interface
        1. 14.2.5.1  SDRAM Commands
        2. 14.2.5.2  Interfacing to SDRAM
        3. 14.2.5.3  SDRAM Configuration Registers
        4. 14.2.5.4  SDRAM Auto-Initialization Sequence
        5. 14.2.5.5  SDRAM Configuration Procedure
        6. 14.2.5.6  EMIF Refresh Controller
          1. 14.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 14.2.5.7  Self-Refresh Mode
        8. 14.2.5.8  Power-Down Mode
        9. 14.2.5.9  SDRAM Read Operation
        10. 14.2.5.10 SDRAM Write Operations
        11. 14.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 14.2.6  Asynchronous Controller and Interface
        1. 14.2.6.1 Interfacing to Asynchronous Memory
        2. 14.2.6.2 Accessing Larger Asynchronous Memories
        3. 14.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 14.2.6.4 Read and Write Operations in Normal Mode
          1. 14.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 14.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 14.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 14.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 14.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 14.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 14.2.7  Data Bus Parking
      8. 14.2.8  Reset and Initialization Considerations
      9. 14.2.9  Interrupt Support
        1. 14.2.9.1 Interrupt Events
      10. 14.2.10 RTDMA Event Support
      11. 14.2.11 EMIF Signal Multiplexing
      12. 14.2.12 Memory Map
      13. 14.2.13 Priority and Arbitration
      14. 14.2.14 System Considerations
        1. 14.2.14.1 Asynchronous Request Times
      15. 14.2.15 Power Management
        1. 14.2.15.1 Power Management Using Self-Refresh Mode
        2. 14.2.15.2 Power Management Using Power Down Mode
      16. 14.2.16 Emulation Considerations
    3. 14.3 EMIF Subsystem (EMIFSS)
      1. 14.3.1 Burst Support
      2. 14.3.2 EMIFSS Performance Improvement
      3. 14.3.3 Buffer Module
        1. 14.3.3.1 CPU Write FIFO
      4. 14.3.4 Emulation Mode
    4. 14.4 Example Configuration
      1. 14.4.1 Hardware Interface
      2. 14.4.2 Software Configuration
        1. 14.4.2.1 Configuring the SDRAM Interface
          1. 14.4.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 14.4.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 14.4.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 14.4.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 14.4.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 14.4.2.2 Configuring the Flash Interface
          1. 14.4.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    5. 14.5 Software
      1. 14.5.1 EMIF Registers to Driverlib Functions
      2. 14.5.2 EMIF Examples
    6. 14.6 EMIF Registers
      1. 14.6.1 EMIF Base Address Table
      2. 14.6.2 EMIF_REGS Registers
  17. 15General-Purpose Input/Output (GPIO)
    1. 15.1  Introduction
      1. 15.1.1 GPIO Related Collateral
    2. 15.2  Configuration Overview
    3. 15.3  Digital Inputs on ADC Pins (AIOs)
    4. 15.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 15.5  Digital General-Purpose I/O Control
    6. 15.6  Input Qualification
      1. 15.6.1 No Synchronization (Asynchronous Input)
      2. 15.6.2 Synchronization to SYSCLKOUT Only
      3. 15.6.3 Qualification Using a Sampling Window
    7. 15.7  PMBUS and I2C Signals
    8. 15.8  GPIO and Peripheral Muxing
      1. 15.8.1 GPIO Muxing
      2. 15.8.2 Peripheral Muxing
    9. 15.9  Internal Pullup Configuration Requirements
    10. 15.10 Software
      1. 15.10.1 GPIO Registers to Driverlib Functions
      2. 15.10.2 GPIO Examples
        1. 15.10.2.1 Device GPIO Toggle - SINGLE_CORE
        2. 15.10.2.2 XINT/XBAR example - SINGLE_CORE
      3. 15.10.3 LED Examples
        1. 15.10.3.1 LED Blinky Example - MULTI_CORE
        2. 15.10.3.2 LED Blinky Example (CPU1,CPU3) - MULTI_CORE
        3. 15.10.3.3 LED Blinky example - SINGLE_CORE
        4. 15.10.3.4 LED Blinky Example (CPU1|CPU2|CPU3) - MULTI_CORE
        5. 15.10.3.5 LED Blinky Example (CPU2) - MULTI_CORE
        6. 15.10.3.6 LED Blinky Example (CPU3) - MULTI_CORE
    11. 15.11 GPIO Registers
      1. 15.11.1 GPIO Base Address Table
      2. 15.11.2 GPIO_CTRL_REGS Registers
      3. 15.11.3 GPIO_DATA_REGS Registers
      4. 15.11.4 GPIO_DATA_READ_REGS Registers
  18. 16Interprocessor Communication (IPC)
    1. 16.1 Introduction
    2. 16.2 IPC Flags and Interrupts
    3. 16.3 IPC Command Registers
    4. 16.4 Free-Running Counter
    5. 16.5 IPC Communication Protocol
    6. 16.6 Software
      1. 16.6.1 IPC Registers to Driverlib Functions
      2. 16.6.2 IPC Examples
        1. 16.6.2.1 IPC basic message passing example with interrupt - MULTI_CORE
        2. 16.6.2.2 IPC basic message passing example with interrupt - MULTI_CORE
        3. 16.6.2.3 IPC basic message passing example with interrupt - MULTI_CORE
        4. 16.6.2.4 IPC basic message passing example with interrupt - MULTI_CORE
    7. 16.7 IPC Registers
      1. 16.7.1 IPC Base Address Table
      2. 16.7.2 IPC_COUNTER_REGS Registers
      3. 16.7.3 CPU1_IPC_SEND_REGS Registers
      4. 16.7.4 CPU2_IPC_SEND_REGS Registers
      5. 16.7.5 CPU3_IPC_SEND_REGS Registers
      6. 16.7.6 CPU1_IPC_RCV_REGS Registers
      7. 16.7.7 CPU2_IPC_RCV_REGS Registers
      8. 16.7.8 CPU3_IPC_RCV_REGS Registers
  19. 17Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 17.1 Introduction
    2. 17.2 Enhanced Bus Comparator Unit
      1. 17.2.1 Enhanced Bus Comparator Unit Operations
      2. 17.2.2 Stack Qualification
      3. 17.2.3 Event Masking and Exporting
    3. 17.3 System Event Counter Unit
      1. 17.3.1 System Event Counter Modes
        1. 17.3.1.1 Counting Active Levels Versus Edges
        2. 17.3.1.2 Max and Min Mode
        3. 17.3.1.3 Cumulative Mode
        4. 17.3.1.4 Input Signal Selection
      2. 17.3.2 Reset on Event
      3. 17.3.3 Operation Conditions
    4. 17.4 Program Counter Trace
      1. 17.4.1 Functional Block Diagram
      2. 17.4.2 Trace Qualification Modes
        1. 17.4.2.1 Trace Input Signal Conditioning
      3. 17.4.3 Trace Memory
      4. 17.4.4 PC Trace Software Operation
      5. 17.4.5 Trace Operation in Debug Mode
    5. 17.5 ERAD Ownership, Initialization, and Reset
      1. 17.5.1 Feature Level Ownership
      2. 17.5.2 Feature Access Security Mechanism
      3. 17.5.3 PC Trace Access Security Mechanism
    6. 17.6 ERAD Programming Sequence
      1. 17.6.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 17.6.2 Timer and Counter Programming Sequence
    7. 17.7 Software
      1. 17.7.1 ERAD Registers to Driverlib Functions
    8. 17.8 ERAD Registers
      1. 17.8.1 ERAD Base Address Table
        1. 17.8.1.1 ERAD_REGS Registers
  20. 18Data Logger and Trace (DLT)
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 DLT Related Collateral
      3. 18.1.3 Interfaces
        1. 18.1.3.1 Block Diagram
    2. 18.2 Functional Overview
      1. 18.2.1 DLT Configuration
        1. 18.2.1.1 LINK Filter
        2. 18.2.1.2 TAG Filter
        3. 18.2.1.3 ERAD Event Trigger
        4. 18.2.1.4 Concurrent FILTERING modes
      2. 18.2.2 Time-stamping
      3. 18.2.3 FIFO Construction
        1. 18.2.3.1 FIFO Interrupt
    3. 18.3 Software
      1. 18.3.1 DLT Registers to Driverlib Functions
      2. 18.3.2 DLT Examples
        1. 18.3.2.1 DLT TAG filter example - SINGLE_CORE
        2. 18.3.2.2 DLT TAG filter example - SINGLE_CORE
        3. 18.3.2.3 DLT ERAD filter example - SINGLE_CORE
    4. 18.4 DLT Registers
      1. 18.4.1 DLT Base Address Table
      2. 18.4.2 DLT_CORE_REGS Registers
      3. 18.4.3 DLT_FIFO_REGS Registers
  21. 19Waveform Analyzer Diagnostic (WADI)
    1. 19.1 WADI Overview
      1. 19.1.1 Features
      2. 19.1.2 WADI Related Collateral
      3. 19.1.3 Block Diagram
      4. 19.1.4 Description
    2. 19.2 Signal and Trigger Input Configuration
      1. 19.2.1 SIG1 and SIG2 Configuration
      2. 19.2.2 Trigger 1 and Trigger 2
    3. 19.3 WADI Block
      1. 19.3.1 Overview
      2. 19.3.2 Counters
      3. 19.3.3 Pulse Width
        1. 19.3.3.1 Pulse Width Single Measurement
        2. 19.3.3.2 Pulse Width Aggregation
        3. 19.3.3.3 Pulse Width Average and Peak
      4. 19.3.4 Edge Count
        1. 19.3.4.1 Edge Count with Fixed Window
        2. 19.3.4.2 Edge Count with Moving Window
      5. 19.3.5 Signal1 to Signal2 Comparison
      6. 19.3.6 Dead Band and Phase
      7. 19.3.7 Simultaneous Measurement
    4. 19.4 Safe State Sequencer (SSS)
      1. 19.4.1 SSS Configuration
    5. 19.5 Lock and Commit Registers
    6. 19.6 Interrupt and Error Handling
    7. 19.7 RTDMA Interfaces
      1. 19.7.1 RTDMA Trigger
    8. 19.8 Software
      1. 19.8.1 WADI Registers to Driverlib Functions
      2. 19.8.2 WADI Examples
        1. 19.8.2.1 WADI Duty and Frequency check - SINGLE_CORE
    9. 19.9 WADI Registers
      1. 19.9.1 WADI Base Address Table
      2. 19.9.2 WADI_CONFIG_REGS Registers
      3. 19.9.3 WADI_OPER_SSS_REGS Registers
  22. 20Crossbar (X-BAR)
    1. 20.1 X-BAR Related Collateral
    2. 20.2 Input X-BAR, ICL XBAR, MINDB XBAR,
      1. 20.2.1 ICL and MINDB X-BAR
    3. 20.3 ePWM , CLB, and GPIO Output X-BAR
      1. 20.3.1 ePWM X-BAR
        1. 20.3.1.1 ePWM X-BAR Architecture
      2. 20.3.2 CLB X-BAR
        1. 20.3.2.1 CLB X-BAR Architecture
      3. 20.3.3 GPIO Output X-BAR
        1. 20.3.3.1 GPIO Output X-BAR Architecture
      4. 20.3.4 X-BAR Flags
    4. 20.4 Software
      1. 20.4.1 INPUT_XBAR Registers to Driverlib Functions
      2. 20.4.2 EPWM_XBAR Registers to Driverlib Functions
      3. 20.4.3 CLB_XBAR Registers to Driverlib Functions
      4. 20.4.4 OUTPUT_XBAR Registers to Driverlib Functions
      5. 20.4.5 MDL_XBAR Registers to Driverlib Functions
      6. 20.4.6 ICL_XBAR Registers to Driverlib Functions
      7. 20.4.7 XBAR Registers to Driverlib Functions
      8. 20.4.8 XBAR Examples
        1. 20.4.8.1 Input XBAR to Output XBAR Connection - SINGLE_CORE
        2. 20.4.8.2 Output XBAR Pulse Stretch - SINGLE_CORE
    5. 20.5 XBAR Registers
      1. 20.5.1 XBAR Base Address Table
      2. 20.5.2 INPUT_XBAR_REGS Registers
      3. 20.5.3 EPWM_XBAR_REGS Registers
      4. 20.5.4 CLB_XBAR_REGS Registers
      5. 20.5.5 OUTPUTXBAR_REGS Registers
      6. 20.5.6 MDL_XBAR_REGS Registers
      7. 20.5.7 ICL_XBAR_REGS Registers
      8. 20.5.8 OUTPUTXBAR_FLAG_REGS Registers
      9. 20.5.9 XBAR_REGS Registers
  23. 21Embedded Pattern Generator (EPG)
    1. 21.1 Introduction
      1. 21.1.1 Features
      2. 21.1.2 EPG Block Diagram
      3. 21.1.3 EPG Related Collateral
    2. 21.2 Clock Generator Modules
      1. 21.2.1 DCLK (50% duty cycle clock)
      2. 21.2.2 Clock Stop
    3. 21.3 Signal Generator Module
    4. 21.4 EPG Peripheral Signal Mux Selection
    5. 21.5 Application Software Notes
    6. 21.6 EPG Example Use Cases
      1. 21.6.1 EPG Example: Synchronous Clocks with Offset
        1. 21.6.1.1 Synchronous Clocks with Offset Register Configuration
      2. 21.6.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 21.6.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 21.6.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 21.6.3.1 Serial Data Bit Stream (MSB first) Register Configuration
      4. 21.6.4 EPG Example: Clock and Data Pair
        1. 21.6.4.1 Clock and Data Pair Register Configuration
      5. 21.6.5 EPG Example: Clock and Skewed Data Pair
        1. 21.6.5.1 Clock and Skewed Data Pair Register Configuration
      6. 21.6.6 EPG Example: Capturing Serial Data with a Known Baud Rate
        1. 21.6.6.1 Capturing Serial Data with a Known Baud Rate Register Configuration
    7. 21.7 EPG Interrupt
    8. 21.8 Software
      1. 21.8.1 EPG Registers to Driverlib Functions
      2. 21.8.2 EPG Examples
        1. 21.8.2.1 EPG Generating Synchronous Clocks - SINGLE_CORE
        2. 21.8.2.2 EPG Generating Two Offset Clocks - SINGLE_CORE
        3. 21.8.2.3 EPG Generating Two Offset Clocks With SIGGEN - SINGLE_CORE
        4. 21.8.2.4 EPG Generate Serial Data - SINGLE_CORE
        5. 21.8.2.5 EPG Generate Serial Data Shift Mode - SINGLE_CORE
    9. 21.9 EPG Registers
      1. 21.9.1 EPG Base Address Table
      2. 21.9.2 EPG_REGS Registers
      3. 21.9.3 EPG_MUX_REGS Registers
  24. 22â–º ANALOG PERIPHERALS
    1.     Technical Reference Manual Overview
  25. 23Analog Subsystem
    1. 23.1 Introduction
      1. 23.1.1 Features
      2. 23.1.2 Block Diagram
    2. 23.2 Optimizing Power-Up Time
    3. 23.3 Digital Inputs on ADC Pins (AIOs)
    4. 23.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 23.5 Analog Pins and Internal Connections
    6. 23.6 Software
      1. 23.6.1 ASYSCTL Registers to Driverlib Functions
    7. 23.7 Lock Registers
    8. 23.8 ASBSYS Registers
      1. 23.8.1 ASBSYS Base Address Table
      2. 23.8.2 ANALOG_SUBSYS_REGS Registers
  26. 24Analog-to-Digital Converter (ADC)
    1. 24.1  Introduction
      1. 24.1.1 ADC Related Collateral
      2. 24.1.2 Features
      3. 24.1.3 Block Diagram
    2. 24.2  ADC Configurability
      1. 24.2.1 Clock Configuration
      2. 24.2.2 Resolution
      3. 24.2.3 Voltage Reference
        1. 24.2.3.1 External Reference Mode
        2. 24.2.3.2 Internal Reference Mode
        3. 24.2.3.3 Ganged References
        4. 24.2.3.4 Selecting Reference Mode
      4. 24.2.4 Signal Mode
      5. 24.2.5 Expected Conversion Results
      6. 24.2.6 Interpreting Conversion Results
    3. 24.3  SOC Principle of Operation
      1. 24.3.1 SOC Configuration
      2. 24.3.2 Trigger Operation
        1. 24.3.2.1 Global Software Trigger
        2. 24.3.2.2 Trigger Repeaters
          1. 24.3.2.2.1 Oversampling Mode
          2. 24.3.2.2.2 Undersampling Mode
          3. 24.3.2.2.3 Trigger Phase Delay
          4. 24.3.2.2.4 Re-trigger Spread
          5. 24.3.2.2.5 Trigger Repeater Configuration
            1. 24.3.2.2.5.1 Register Shadow Updates
          6. 24.3.2.2.6 Re-Trigger Logic
          7. 24.3.2.2.7 Multi-Path Triggering Behavior
      3. 24.3.3 ADC Acquisition (Sample and Hold) Window
      4. 24.3.4 ADC Input Models
      5. 24.3.5 Channel Selection
        1. 24.3.5.1 External Channel Selection
          1. 24.3.5.1.1 External Channel Selection Timing
    4. 24.4  SOC Configuration Examples
      1. 24.4.1 Single Conversion from ePWM Trigger
      2. 24.4.2 Oversampled Conversion from ePWM Trigger
      3. 24.4.3 Multiple Conversions from CPU Timer Trigger
      4. 24.4.4 Software Triggering of SOCs
    5. 24.5  ADC Conversion Priority
    6. 24.6  Burst Mode
      1. 24.6.1 Burst Mode Example
      2. 24.6.2 Burst Mode Priority Example
    7. 24.7  EOC and Interrupt Operation
      1. 24.7.1 Interrupt Overflow
      2. 24.7.2 Continue to Interrupt Mode
      3. 24.7.3 Early Interrupt Configuration Mode
    8. 24.8  Post-Processing Blocks
      1. 24.8.1 PPB Offset Correction
      2. 24.8.2 PPB Error Calculation
      3. 24.8.3 PPB Result Delta Calculation
      4. 24.8.4 PPB Limit Detection and Zero-Crossing Detection
        1. 24.8.4.1 PPB Digital Trip Filter
      5. 24.8.5 PPB Sample Delay Capture
      6. 24.8.6 PPB Oversampling
        1. 24.8.6.1 Accumulation, Minimum, Maximum, and Average Functions
        2. 24.8.6.2 Outlier Rejection
    9. 24.9  Result Safety Checker
      1. 24.9.1 Result Safety Checker Operation
      2. 24.9.2 Result Safety Checker Interrupts and Events
    10. 24.10 Opens/Shorts Detection Circuit (OSDETECT)
      1. 24.10.1 Implementation
      2. 24.10.2 Detecting an Open Input Pin
      3. 24.10.3 Detecting a Shorted Input Pin
    11. 24.11 Power-Up Sequence
    12. 24.12 ADC Calibration
      1. 24.12.1 ADC Zero Offset Calibration
    13. 24.13 ADC Timings
      1. 24.13.1 ADC Timing Diagrams
      2. 24.13.2 Post-Processing Block Timings
    14. 24.14 Additional Information
      1. 24.14.1 Ensuring Synchronous Operation
        1. 24.14.1.1 Basic Synchronous Operation
        2. 24.14.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 24.14.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 24.14.1.4 Synchronous Operation with Different Resolutions
        5. 24.14.1.5 Non-overlapping Conversions
      2. 24.14.2 Choosing an Acquisition Window Duration
      3. 24.14.3 Achieving Simultaneous Sampling
      4. 24.14.4 Result Register Mapping
      5. 24.14.5 Internal Temperature Sensor
      6. 24.14.6 Designing an External Reference Circuit
      7. 24.14.7 Internal Test Mode
      8. 24.14.8 ADC Gain and Offset Calibration
    15. 24.15 Software
      1. 24.15.1 ADC Registers to Driverlib Functions
      2. 24.15.2 ADC Examples
        1. 24.15.2.1  ADC Software Triggering - SINGLE_CORE
        2. 24.15.2.2  ADC ePWM Triggering - SINGLE_CORE
        3. 24.15.2.3  ADC Temperature Sensor Conversion - SINGLE_CORE
        4. 24.15.2.4  ADC Synchronous SOC Software Force (adc_soc_software_sync) - SINGLE_CORE
        5. 24.15.2.5  ADC Continuous Triggering (adc_soc_continuous) - SINGLE_CORE
        6. 24.15.2.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma) - SINGLE_CORE
        7. 24.15.2.7  ADC PPB Offset (adc_ppb_offset) - SINGLE_CORE
        8. 24.15.2.8  ADC PPB Limits (adc_ppb_limits) - SINGLE_CORE
        9. 24.15.2.9  ADC PPB Delay Capture (adc_ppb_delay) - SINGLE_CORE
        10. 24.15.2.10 ADC ePWM Triggering Multiple SOC - SINGLE_CORE
        11. 24.15.2.11 ADC Burst Mode - SINGLE_CORE
        12. 24.15.2.12 ADC Burst Mode Oversampling - SINGLE_CORE
        13. 24.15.2.13 ADC SOC Oversampling - SINGLE_CORE
        14. 24.15.2.14 ADC PPB PWM trip (adc_ppb_pwm_trip) - SINGLE_CORE
        15. 24.15.2.15 ADC Trigger Repeater Oversampling - SINGLE_CORE
        16. 24.15.2.16 ADC Trigger Repeater Undersampling - SINGLE_CORE
        17. 24.15.2.17 ADC Safety Checker - SINGLE_CORE
    16. 24.16 ADC Registers
      1. 24.16.1 ADC Base Address Table
      2. 24.16.2 ADC_RESULT_REGS Registers
      3. 24.16.3 ADC_REGS Registers
      4. 24.16.4 ADC_SAFECHECK_REGS Registers
      5. 24.16.5 ADC_SAFECHECK_INTEVT_REGS Registers
      6. 24.16.6 ADC_GLOBAL_REGS Registers
  27. 25Buffered Digital-to-Analog Converter (DAC)
    1. 25.1 Introduction
      1. 25.1.1 DAC Related Collateral
      2. 25.1.2 Features
      3. 25.1.3 Block Diagram
    2. 25.2 Using the DAC
      1. 25.2.1 Initialization Sequence
      2. 25.2.2 DAC Offset Adjustment
      3. 25.2.3 EPWMSYNCPER Signal
    3. 25.3 Lock Registers
    4. 25.4 Software
      1. 25.4.1 DAC Registers to Driverlib Functions
      2. 25.4.2 DAC Examples
        1. 25.4.2.1 Buffered DAC Enable - SINGLE_CORE
        2. 25.4.2.2 Buffered DAC Random - SINGLE_CORE
    5. 25.5 DAC Registers
      1. 25.5.1 DAC Base Address Table
      2. 25.5.2 DAC_REGS Registers
  28. 26Comparator Subsystem (CMPSS)
    1. 26.1 Introduction
      1. 26.1.1 CMPSS Related Collateral
      2. 26.1.2 Features
      3. 26.1.3 Block Diagram
    2. 26.2 Comparator
    3. 26.3 Reference DAC
    4. 26.4 Ramp Generator
      1. 26.4.1 Ramp Generator Overview
      2. 26.4.2 Ramp Generator Behavior
      3. 26.4.3 Ramp Generator Behavior at Corner Cases
    5. 26.5 Digital Filter
      1. 26.5.1 Filter Initialization Sequence
    6. 26.6 Using the CMPSS
      1. 26.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 26.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 26.6.3 Calibrating the CMPSS
      4. 26.6.4 Enabling and Disabling the CMPSS Clock
    7. 26.7 Software
      1. 26.7.1 CMPSS Registers to Driverlib Functions
      2. 26.7.2 CMPSS Examples
        1. 26.7.2.1 CMPSS Asynchronous Trip - SINGLE_CORE
        2. 26.7.2.2 CMPSS Digital Filter Configuration - SINGLE_CORE
    8. 26.8 CMPSS Registers
      1. 26.8.1 CMPSS Base Address Table
      2. 26.8.2 CMPSS_REGS Registers
  29. 27â–º CONTROL PERIPHERALS
    1.     Technical Reference Manual Overview
  30. 28Enhanced Capture (eCAP)
    1. 28.1 Introduction
      1. 28.1.1 Features
      2. 28.1.2 ECAP Related Collateral
    2. 28.2 Description
    3. 28.3 Configuring Device Pins for the eCAP
    4. 28.4 Capture and APWM Operating Mode
    5. 28.5 Capture Mode Description
      1. 28.5.1  Event Prescaler
      2. 28.5.2  Glitch Filter
      3. 28.5.3  Edge Polarity Select and Qualifier
      4. 28.5.4  Continuous/One-Shot Control
      5. 28.5.5  32-Bit Counter and Phase Control
      6. 28.5.6  CAP1-CAP4 Registers
      7. 28.5.7  eCAP Synchronization
        1. 28.5.7.1 Example 1 - Using SWSYNC with ECAP Module
      8. 28.5.8  Interrupt Control
      9. 28.5.9  RTDMA Interrupt
      10. 28.5.10 ADC SOC Event
      11. 28.5.11 Shadow Load and Lockout Control
      12. 28.5.12 APWM Mode Operation
      13. 28.5.13 Signal Monitoring Unit
        1. 28.5.13.1 Pulse Width and Period Monitoring
        2. 28.5.13.2 Edge Monitoring
    6. 28.6 Application of the eCAP Module
      1. 28.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 28.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 28.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 28.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 28.7 Application of the APWM Mode
      1. 28.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 28.8 Software
      1. 28.8.1 ECAP Registers to Driverlib Functions
      2. 28.8.2 ECAP Examples
        1. 28.8.2.1 eCAP APWM Example - SINGLE_CORE
        2. 28.8.2.2 eCAP Capture PWM Example - SINGLE_CORE
        3. 28.8.2.3 eCAP APWM Phase-shift Example - SINGLE_CORE
    9. 28.9 ECAP Registers
      1. 28.9.1 ECAP Base Address Table
      2. 28.9.2 ECAP_REGS Registers
      3. 28.9.3 ECAP_SIGNAL_MONITORING Registers
      4. 28.9.4 HRCAP_REGS Registers
  31. 29High Resolution Capture (HRCAP)
    1. 29.1 Introduction
      1. 29.1.1 HRCAP Related Collateral
      2. 29.1.2 Features
      3. 29.1.3 Description
    2. 29.2 Operational Details
      1. 29.2.1 HRCAP Clocking
      2. 29.2.2 HRCAP Initialization Sequence
      3. 29.2.3 HRCAP Interrupts
      4. 29.2.4 HRCAP Calibration
        1. 29.2.4.1 Applying the Scale Factor
    3. 29.3 Known Exceptions
    4. 29.4 Software
      1. 29.4.1 HRCAP Examples
        1. 29.4.1.1 HRCAP Capture and Calibration Example - SINGLE_CORE
    5. 29.5 HRCAP Registers
      1. 29.5.1 HRCAP Base Address Table
      2. 29.5.2 HRCAP_REGS Registers
  32. 30Enhanced Pulse Width Modulator (ePWM)
    1. 30.1  Introduction
      1. 30.1.1 EPWM Related Collateral
      2. 30.1.2 Submodule Overview
    2. 30.2  Configuring Device Pins
    3. 30.3  ePWM Modules Overview
    4. 30.4  Time-Base (TB) Submodule
      1. 30.4.1 Purpose of the Time-Base Submodule
      2. 30.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 30.4.3 Calculating PWM Period and Frequency
        1. 30.4.3.1 Time-Base Period Shadow Register
        2. 30.4.3.2 Time-Base Clock Synchronization
        3. 30.4.3.3 Time-Base Counter Synchronization
        4. 30.4.3.4 ePWM SYNC Selection
      4. 30.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 30.4.5 Simultaneous Writes Between ePWM Register Instances
      6. 30.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 30.4.7 Global Load
        1. 30.4.7.1 Global Load Pulse Pre-Scalar
        2. 30.4.7.2 One-Shot Load Mode
        3. 30.4.7.3 One-Shot Sync Mode
    5. 30.5  Counter-Compare (CC) Submodule
      1. 30.5.1 Purpose of the Counter-Compare Submodule
      2. 30.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 30.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 30.5.4 Count Mode Timing Waveforms
    6. 30.6  Action-Qualifier (AQ) Submodule
      1. 30.6.1 Purpose of the Action-Qualifier Submodule
      2. 30.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 30.6.3 Action-Qualifier Event Priority
      4. 30.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 30.6.5 Configuration Requirements for Common Waveforms
    7. 30.7  XCMP Complex Waveform Generator Mode
      1. 30.7.1 XCMP Allocation to CMPA and CMPB
      2. 30.7.2 XCMP Shadow Buffers
      3. 30.7.3 XCMP Operation
    8. 30.8  Dead-Band Generator (DB) Submodule
      1. 30.8.1 Purpose of the Dead-Band Submodule
      2. 30.8.2 Dead-band Submodule Additional Operating Modes
      3. 30.8.3 Operational Highlights for the Dead-Band Submodule
    9. 30.9  PWM Chopper (PC) Submodule
      1. 30.9.1 Purpose of the PWM Chopper Submodule
      2. 30.9.2 Operational Highlights for the PWM Chopper Submodule
      3. 30.9.3 Waveforms
        1. 30.9.3.1 One-Shot Pulse
        2. 30.9.3.2 Duty Cycle Control
    10. 30.10 Trip-Zone (TZ) Submodule
      1. 30.10.1 Purpose of the Trip-Zone Submodule
      2. 30.10.2 Operational Highlights for the Trip-Zone Submodule
        1. 30.10.2.1 Trip-Zone Configurations
      3. 30.10.3 Generating Trip Event Interrupts
    11. 30.11 Diode Emulation (DE) Submodule
      1. 30.11.1 DEACTIVE Mode
      2. 30.11.2 Exiting DE Mode
      3. 30.11.3 Re-Entering DE Mode
      4. 30.11.4 DE Monitor
    12. 30.12 Minimum Dead-Band (MINDB) + Illegal Combination Logic (ICL) Submodules
      1. 30.12.1 Minimum Dead-Band (MINDB)
      2. 30.12.2 Illegal Combo Logic (ICL)
    13. 30.13 Event-Trigger (ET) Submodule
      1. 30.13.1 Operational Overview of the ePWM Event-Trigger Submodule
    14. 30.14 Digital Compare (DC) Submodule
      1. 30.14.1 Purpose of the Digital Compare Submodule
      2. 30.14.2 Enhanced Trip Action Using CMPSS
      3. 30.14.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 30.14.4 Operation Highlights of the Digital Compare Submodule
        1. 30.14.4.1 Digital Compare Events
        2. 30.14.4.2 Event Filtering
        3. 30.14.4.3 Valley Switching
        4. 30.14.4.4 Event Detection
          1. 30.14.4.4.1 Input Signal Detection
          2. 30.14.4.4.2 MIN and MAX Detection Circuit
    15. 30.15 ePWM Crossbar (X-BAR)
    16. 30.16 Applications to Power Topologies
      1. 30.16.1  Overview of Multiple Modules
      2. 30.16.2  Key Configuration Capabilities
      3. 30.16.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 30.16.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 30.16.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 30.16.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 30.16.7  Practical Applications Using Phase Control Between PWM Modules
      8. 30.16.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 30.16.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 30.16.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 30.16.11 Controlling H-Bridge LLC Resonant Converter
    17. 30.17 Register Lock Protection
    18. 30.18 High-Resolution Pulse Width Modulator (HRPWM)
      1. 30.18.1 Operational Description of HRPWM
        1. 30.18.1.1 Controlling the HRPWM Capabilities
        2. 30.18.1.2 HRPWM Source Clock
        3. 30.18.1.3 Configuring the HRPWM
        4. 30.18.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 30.18.1.5 Principle of Operation
          1. 30.18.1.5.1 Edge Positioning
          2. 30.18.1.5.2 Scaling Considerations
          3. 30.18.1.5.3 Duty Cycle Range Limitation
          4. 30.18.1.5.4 High-Resolution Period
            1. 30.18.1.5.4.1 High-Resolution Period Configuration
        6. 30.18.1.6 Deadband High-Resolution Operation
        7. 30.18.1.7 Scale Factor Optimizing Software (SFO)
        8. 30.18.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 30.18.1.8.1 #Defines for HRPWM Header Files
          2. 30.18.1.8.2 Implementing a Simple Buck Converter
            1. 30.18.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 30.18.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 30.18.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 30.18.1.8.3.1 PWM DAC Function Initialization Code
            2. 30.18.1.8.3.2 PWM DAC Function Run-Time Code
      2. 30.18.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 30.18.2.1 Scale Factor Optimizer Function - int SFO()
        2. 30.18.2.2 Software Usage
          1. 30.18.2.2.1 A Sample of How to Add "Include" Files
          2.        1131
          3. 30.18.2.2.2 Declaring an Element
          4.        1133
          5. 30.18.2.2.3 Initializing With a Scale Factor Value
          6.        1135
          7. 30.18.2.2.4 SFO Function Calls
    19. 30.19 Software
      1. 30.19.1 EPWM Registers to Driverlib Functions
      2. 30.19.2 HRPWMCAL Registers to Driverlib Functions
      3. 30.19.3 EPWM Examples
        1. 30.19.3.1  ePWM Trip Zone - SINGLE_CORE
        2. 30.19.3.2  ePWM Up Down Count Action Qualifier - SINGLE_CORE
        3. 30.19.3.3  ePWM Synchronization - SINGLE_CORE
        4. 30.19.3.4  ePWM Digital Compare - SINGLE_CORE
        5. 30.19.3.5  ePWM Digital Compare Event Filter Blanking Window - SINGLE_CORE
        6. 30.19.3.6  ePWM Valley Switching - SINGLE_CORE
        7. 30.19.3.7  ePWM Digital Compare Edge Filter - SINGLE_CORE
        8. 30.19.3.8  ePWM Deadband - SINGLE_CORE
        9. 30.19.3.9  ePWM DMA - SINGLE_CORE
        10. 30.19.3.10 ePWM Chopper - SINGLE_CORE
        11. 30.19.3.11 EPWM Configure Signal - SINGLE_CORE
        12. 30.19.3.12 Realization of Monoshot mode - SINGLE_CORE
        13. 30.19.3.13 EPWM Action Qualifier (epwm_up_aq) - SINGLE_CORE
        14. 30.19.3.14 ePWM XCMP Mode - SINGLE_CORE
        15. 30.19.3.15 ePWM Event Detection - SINGLE_CORE
    20. 30.20 EPWM Registers
      1. 30.20.1 EPWM Base Address Table
      2. 30.20.2 EPWM_REGS Registers
      3. 30.20.3 EPWM_XCMP_REGS Registers
      4. 30.20.4 DE_REGS Registers
      5. 30.20.5 MINDB_LUT_REGS Registers
      6. 30.20.6 HRPWMCAL_REGS Registers
  33. 31Enhanced Quadrature Encoder Pulse (eQEP)
    1. 31.1  Introduction
      1. 31.1.1 EQEP Related Collateral
    2. 31.2  Configuring Device Pins
    3. 31.3  Description
      1. 31.3.1 EQEP Inputs
      2. 31.3.2 Functional Description
      3. 31.3.3 eQEP Memory Map
    4. 31.4  Quadrature Decoder Unit (QDU)
      1. 31.4.1 Position Counter Input Modes
        1. 31.4.1.1 Quadrature Count Mode
        2. 31.4.1.2 Direction-Count Mode
        3. 31.4.1.3 Up-Count Mode
        4. 31.4.1.4 Down-Count Mode
      2. 31.4.2 eQEP Input Polarity Selection
      3. 31.4.3 Position-Compare Sync Output
    5. 31.5  Position Counter and Control Unit (PCCU)
      1. 31.5.1 Position Counter Operating Modes
        1. 31.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 31.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 31.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 31.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 31.5.2 Position Counter Latch
        1. 31.5.2.1 Index Event Latch
        2. 31.5.2.2 Strobe Event Latch
      3. 31.5.3 Position Counter Initialization
      4. 31.5.4 eQEP Position-compare Unit
    6. 31.6  eQEP Edge Capture Unit
    7. 31.7  eQEP Watchdog
    8. 31.8  eQEP Unit Timer Base
    9. 31.9  QMA Module
      1. 31.9.1 Modes of Operation
        1. 31.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 31.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 31.9.2 Interrupt and Error Generation
    10. 31.10 eQEP Interrupt Structure
    11. 31.11 Software
      1. 31.11.1 EQEP Registers to Driverlib Functions
      2. 31.11.2 EQEP Examples
        1. 31.11.2.1 Frequency Measurement Using eQEP via unit timeout interrupt - SINGLE_CORE
        2. 31.11.2.2 Motor speed and direction measurement using eQEP via unit timeout interrupt - SINGLE_CORE
    12. 31.12 EQEP Registers
      1. 31.12.1 EQEP Base Address Table
      2. 31.12.2 EQEP_REGS Registers
  34. 32Sigma Delta Filter Module (SDFM)
    1. 32.1  Introduction
      1. 32.1.1 SDFM Related Collateral
      2. 32.1.2 Features
      3. 32.1.3 Block Diagram
    2. 32.2  Configuring Device Pins
    3. 32.3  Input Qualification
    4. 32.4  Input Control Unit
    5. 32.5  SDFM Clock Control
    6. 32.6  Sinc Filter
      1. 32.6.1 Data Rate and Latency of the Sinc Filter
    7. 32.7  Data (Primary) Filter Unit
      1. 32.7.1 32-bit or 16-bit Data Filter Output Representation
      2. 32.7.2 Data FIFO
      3. 32.7.3 SDSYNC Event
    8. 32.8  Comparator (Secondary) Filter Unit
      1. 32.8.1 Higher Threshold (HLT) Comparators
      2. 32.8.2 Lower Threshold (LLT) Comparators
      3. 32.8.3 Digital Filter
    9. 32.9  Theoretical SDFM Filter Output
    10. 32.10 Interrupt Unit
      1. 32.10.1 SDFM (SDyERR) Interrupt Sources
      2. 32.10.2 Data Ready (DRINT) Interrupt Sources
    11. 32.11 Software
      1. 32.11.1 SDFM Registers to Driverlib Functions
      2. 32.11.2 SDFM Examples
    12. 32.12 SDFM Registers
      1. 32.12.1 SDFM Base Address Table
      2. 32.12.2 SDFM_REGS Registers
  35. 33â–º COMMUNICATION PERIPHERALS
    1.     Technical Reference Manual Overview
  36. 34Modular Controller Area Network (MCAN)
    1. 34.1 MCAN Introduction
      1. 34.1.1 MCAN Related Collateral
      2. 34.1.2 MCAN Features
    2. 34.2 MCAN Environment
    3. 34.3 CAN Network Basics
    4. 34.4 MCAN Integration
    5. 34.5 MCAN Functional Description
      1. 34.5.1  Module Clocking Requirements
      2. 34.5.2  Interrupt Requests
      3. 34.5.3  Operating Modes
        1. 34.5.3.1 Software Initialization
        2. 34.5.3.2 Normal Operation
        3. 34.5.3.3 CAN FD Operation
      4. 34.5.4  Transmitter Delay Compensation
        1. 34.5.4.1 Description
        2. 34.5.4.2 Transmitter Delay Compensation Measurement
      5. 34.5.5  Restricted Operation Mode
      6. 34.5.6  Bus Monitoring Mode
      7. 34.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 34.5.7.1 Frame Transmission in DAR Mode
      8. 34.5.8  Clock Stop Mode
        1. 34.5.8.1 Suspend Mode
        2. 34.5.8.2 Wakeup Request
      9. 34.5.9  Test Modes
        1. 34.5.9.1 External Loop Back Mode
        2. 34.5.9.2 Internal Loop Back Mode
      10. 34.5.10 Timestamp Generation
        1. 34.5.10.1 External Timestamp Counter
      11. 34.5.11 Timeout Counter
      12. 34.5.12 Safety
        1. 34.5.12.1 ECC Wrapper
        2. 34.5.12.2 ECC Aggregator
          1. 34.5.12.2.1 ECC Aggregator Overview
          2. 34.5.12.2.2 ECC Aggregator Registers
        3. 34.5.12.3 Reads to ECC Control and Status Registers
        4. 34.5.12.4 ECC Interrupts
      13. 34.5.13 Rx Handling
        1. 34.5.13.1 Acceptance Filtering
          1. 34.5.13.1.1 Range Filter
          2. 34.5.13.1.2 Filter for Specific IDs
          3. 34.5.13.1.3 Classic Bit Mask Filter
          4. 34.5.13.1.4 Standard Message ID Filtering
          5. 34.5.13.1.5 Extended Message ID Filtering
        2. 34.5.13.2 Rx FIFOs
          1. 34.5.13.2.1 Rx FIFO Blocking Mode
          2. 34.5.13.2.2 Rx FIFO Overwrite Mode
        3. 34.5.13.3 Dedicated Rx Buffers
          1. 34.5.13.3.1 Rx Buffer Handling
      14. 34.5.14 Tx Handling
        1. 34.5.14.1 Transmit Pause
        2. 34.5.14.2 Dedicated Tx Buffers
        3. 34.5.14.3 Tx FIFO
        4. 34.5.14.4 Tx Queue
        5. 34.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 34.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 34.5.14.7 Transmit Cancellation
        8. 34.5.14.8 Tx Event Handling
      15. 34.5.15 FIFO Acknowledge Handling
      16. 34.5.16 Message RAM
        1. 34.5.16.1 Message RAM Configuration
        2. 34.5.16.2 Rx Buffer and FIFO Element
        3. 34.5.16.3 Tx Buffer Element
        4. 34.5.16.4 Tx Event FIFO Element
        5. 34.5.16.5 Standard Message ID Filter Element
        6. 34.5.16.6 Extended Message ID Filter Element
    6. 34.6 Software
      1. 34.6.1 MCAN Examples
        1. 34.6.1.1 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
        2. 34.6.1.2 MCAN Loopback with Polling Example Using SYSCONFIG Tool - SINGLE_CORE
        3. 34.6.1.3 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
    7. 34.7 MCAN Registers
      1. 34.7.1 MCAN Base Address Table
      2. 34.7.2 MCANSS_REGS Registers
      3. 34.7.3 MCAN_REGS Registers
      4. 34.7.4 MCAN_ERROR_REGS Registers
  37. 35EtherCAT® SubordinateDevice Controller (ESC)
    1. 35.1 Introduction
      1. 35.1.1  EtherCAT Related Collateral
      2. 35.1.2  ESC Features
      3. 35.1.3  ESC Subsystem Integrated Features
      4. 35.1.4  ESC versus Beckhoff ET1100
      5. 35.1.5  EtherCAT IP Block Diagram
      6. 35.1.6  ESC Functional Blocks
        1. 35.1.6.1  Interface to EtherCAT MainDevice
        2. 35.1.6.2  Process Data Interface
        3. 35.1.6.3  General-Purpose Inputs and Outputs
        4. 35.1.6.4  EtherCAT Processing Unit (EPU)
        5. 35.1.6.5  Fieldbus Memory Management Unit (FMMU)
        6. 35.1.6.6  Sync Manager
        7. 35.1.6.7  Monitoring
        8. 35.1.6.8  Reset Controller
        9. 35.1.6.9  PHY Management
        10. 35.1.6.10 Distributed Clock (DC)
        11. 35.1.6.11 EEPROM
        12. 35.1.6.12 Status / LEDs
      7. 35.1.7  EtherCAT Physical Layer
        1. 35.1.7.1 MII Interface
        2. 35.1.7.2 PHY Management Interface
          1. 35.1.7.2.1 PHY Address Configuration
          2. 35.1.7.2.2 PHY Reset Signal
          3. 35.1.7.2.3 PHY Clock
      8. 35.1.8  EtherCAT Protocol
      9. 35.1.9  EtherCAT State Machine (ESM)
      10. 35.1.10 More Information on EtherCAT
      11. 35.1.11 Beckhoff® Automation EtherCAT IP Errata
    2. 35.2 ESC and ESCSS Description
      1. 35.2.1  ESC RAM Parity and Memory Address Maps
        1. 35.2.1.1 ESC RAM Parity Logic
        2. 35.2.1.2 CPU1 ESC Memory Address Map
        3. 35.2.1.3 CPU2 ESC Memory Address Map
      2. 35.2.2  Local Host Communication
        1. 35.2.2.1 Byte Accessibility Through PDI
        2. 35.2.2.2 Software Details for Operation Across Clock Domains
      3. 35.2.3  Debug Emulation Mode Operation
      4. 35.2.4  ESC SubSystem
        1. 35.2.4.1 CPU1 Bus Interface
        2. 35.2.4.2 CPU2/CPU3 Bus Interface
      5. 35.2.5  Interrupts and Interrupt Mapping
      6. 35.2.6  Power, Clocks, and Resets
        1. 35.2.6.1 Power
        2. 35.2.6.2 Clocking
        3. 35.2.6.3 Resets
          1. 35.2.6.3.1 Chip-Level Reset
          2. 35.2.6.3.2 EtherCAT Soft Resets
          3. 35.2.6.3.3 Reset Out (RESET_OUT)
      7. 35.2.7  LED Controls
      8. 35.2.8  SubordinateDevice Node Configuration and EEPROM
      9. 35.2.9  General-Purpose Inputs and Outputs
        1. 35.2.9.1 General-Purpose Inputs
        2. 35.2.9.2 General-Purpose Output
      10. 35.2.10 Distributed Clocks – Sync and Latch
        1. 35.2.10.1 Clock Synchronization
        2. 35.2.10.2 SYNC Signals
          1. 35.2.10.2.1 Seeking Host Intervention
        3. 35.2.10.3 LATCH Signals
          1. 35.2.10.3.1 Timestamping
        4. 35.2.10.4 Device Control and Synchronization
          1. 35.2.10.4.1 Synchronization of PWM
          2. 35.2.10.4.2 ECAP SYNC Inputs
          3. 35.2.10.4.3 SYNC Signal Conditioning and Rerouting
    3. 35.3 Software Initialization Sequence and Allocating Ownership
    4. 35.4 ESC Configuration Constants
    5. 35.5 Software
      1. 35.5.1 ECAT_SS Registers to Driverlib Functions
      2. 35.5.2 ETHERNET Examples
    6. 35.6 ETHERCAT Registers
      1. 35.6.1 ETHERCAT Base Address Table
      2. 35.6.2 ESCSS_REGS Registers
      3. 35.6.3 ESCSS_CONFIG_REGS Registers
  38. 36Fast Serial Interface (FSI)
    1. 36.1 Introduction
      1. 36.1.1 FSI Related Collateral
      2. 36.1.2 FSI Features
    2. 36.2 System-level Integration
      1. 36.2.1 CPU Interface
      2. 36.2.2 Signal Description
        1. 36.2.2.1 Configuring Device Pins
      3. 36.2.3 FSI Interrupts
        1. 36.2.3.1 Transmitter Interrupts
        2. 36.2.3.2 Receiver Interrupts
        3. 36.2.3.3 Configuring Interrupts
        4. 36.2.3.4 Handling Interrupts
      4. 36.2.4 RTDMA Interface
      5. 36.2.5 External Frame Trigger Mux
    3. 36.3 FSI Functional Description
      1. 36.3.1 Introduction to Operation
      2. 36.3.2 FSI Transmitter Module
        1. 36.3.2.1 Initialization
        2. 36.3.2.2 FSI_TX Clocking
        3. 36.3.2.3 Transmitting Frames
          1. 36.3.2.3.1 Software Triggered Frames
          2. 36.3.2.3.2 Externally Triggered Frames
          3. 36.3.2.3.3 Ping Frame Generation
            1. 36.3.2.3.3.1 Automatic Ping Frames
            2. 36.3.2.3.3.2 Software Triggered Ping Frame
            3. 36.3.2.3.3.3 Externally Triggered Ping Frame
          4. 36.3.2.3.4 Transmitting Frames with RTDMA
        4. 36.3.2.4 Transmit Buffer Management
        5. 36.3.2.5 CRC Submodule
        6. 36.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 36.3.2.7 Reset
      3. 36.3.3 FSI Receiver Module
        1. 36.3.3.1  Initialization
        2. 36.3.3.2  FSI_RX Clocking
        3. 36.3.3.3  Receiving Frames
          1. 36.3.3.3.1 Receiving Frames with RTDMA
        4. 36.3.3.4  Ping Frame Watchdog
        5. 36.3.3.5  Frame Watchdog
        6. 36.3.3.6  Delay Line Control
        7. 36.3.3.7  Buffer Management
        8. 36.3.3.8  CRC Submodule
        9. 36.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 36.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 36.3.3.11 FSI_RX Reset
      4. 36.3.4 Frame Format
        1. 36.3.4.1 FSI Frame Phases
        2. 36.3.4.2 Frame Types
          1. 36.3.4.2.1 Ping Frames
          2. 36.3.4.2.2 Error Frames
          3. 36.3.4.2.3 Data Frames
        3. 36.3.4.3 Multi-Lane Transmission
      5. 36.3.5 Flush Sequence
      6. 36.3.6 Internal Loopback
      7. 36.3.7 CRC Generation
      8. 36.3.8 ECC Module
      9. 36.3.9 FSI-SPI Compatibility Mode
        1. 36.3.9.1 Available SPI Modes
          1. 36.3.9.1.1 FSITX as SPI Controller, Transmit Only
            1. 36.3.9.1.1.1 Initialization
            2. 36.3.9.1.1.2 Operation
          2. 36.3.9.1.2 FSIRX as SPI Peripheral, Receive Only
            1. 36.3.9.1.2.1 Initialization
            2. 36.3.9.1.2.2 Operation
          3. 36.3.9.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
            1. 36.3.9.1.3.1 Initialization
            2. 36.3.9.1.3.2 Operation
    4. 36.4 FSI Programing Guide
      1. 36.4.1 Establishing the Communication Link
        1. 36.4.1.1 Establishing the Communication Link from the Main Device
        2. 36.4.1.2 Establishing the Communication Link from the Remote Device
      2. 36.4.2 Register Protection
      3. 36.4.3 Emulation Mode
    5. 36.5 Software
      1. 36.5.1 FSI Registers to Driverlib Functions
      2. 36.5.2 FSI Examples
        1. 36.5.2.1 FSI Loopback:CPU Control - SINGLE_CORE
        2. 36.5.2.2 FSI data transfers upon CPU Timer event - SINGLE_CORE
    6. 36.6 FSI Registers
      1. 36.6.1 FSI Base Address Table
      2. 36.6.2 FSI_TX_REGS Registers
      3. 36.6.3 FSI_RX_REGS Registers
  39. 37Inter-Integrated Circuit Module (I2C)
    1. 37.1 Introduction
      1. 37.1.1 I2C Related Collateral
      2. 37.1.2 Features
      3. 37.1.3 Features Not Supported
      4. 37.1.4 Functional Overview
      5. 37.1.5 Clock Generation
      6. 37.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 37.1.6.1 Formula for the Controller Clock Period
    2. 37.2 Configuring Device Pins
    3. 37.3 I2C Module Operational Details
      1. 37.3.1  Input and Output Voltage Levels
      2. 37.3.2  Selecting Pullup Resistors
      3. 37.3.3  Data Validity
      4. 37.3.4  Operating Modes
      5. 37.3.5  I2C Module START and STOP Conditions
      6. 37.3.6  Non-repeat Mode versus Repeat Mode
      7. 37.3.7  Serial Data Formats
        1. 37.3.7.1 7-Bit Addressing Format
        2. 37.3.7.2 10-Bit Addressing Format
        3. 37.3.7.3 Free Data Format
        4. 37.3.7.4 Using a Repeated START Condition
      8. 37.3.8  Clock Synchronization
      9. 37.3.9  Clock Stretching
      10. 37.3.10 Arbitration
      11. 37.3.11 Digital Loopback Mode
      12. 37.3.12 NACK Bit Generation
    4. 37.4 Interrupt Requests Generated by the I2C Module
      1. 37.4.1 Basic I2C Interrupt Requests
      2. 37.4.2 I2C FIFO Interrupts
    5. 37.5 Resetting or Disabling the I2C Module
    6. 37.6 Software
      1. 37.6.1 I2C Registers to Driverlib Functions
      2. 37.6.2 I2C Examples
        1. 37.6.2.1 I2C Digital Loopback with FIFO Interrupts - SINGLE_CORE
        2. 37.6.2.2 I2C EEPROM - SINGLE_CORE
        3. 37.6.2.3 I2C Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        4. 37.6.2.4 I2C Extended Clock Stretching Controller TX - SINGLE_CORE
        5. 37.6.2.5 I2C Extended Clock Stretching Target RX - SINGLE_CORE
    7. 37.7 I2C Registers
      1. 37.7.1 I2C Base Address Table
      2. 37.7.2 I2C_REGS Registers
  40. 38Power Management Bus Module (PMBus)
    1. 38.1 Introduction
      1. 38.1.1 PMBUS Related Collateral
      2. 38.1.2 Features
      3. 38.1.3 Block Diagram
    2. 38.2 Configuring Device Pins
    3. 38.3 Target Mode Operation
      1. 38.3.1 Configuration
      2. 38.3.2 Message Handling
        1. 38.3.2.1  Quick Command
        2. 38.3.2.2  Send Byte
        3. 38.3.2.3  Receive Byte
        4. 38.3.2.4  Write Byte and Write Word
        5. 38.3.2.5  Read Byte and Read Word
        6. 38.3.2.6  Process Call
        7. 38.3.2.7  Block Write
        8. 38.3.2.8  Block Read
        9. 38.3.2.9  Block Write-Block Read Process Call
        10. 38.3.2.10 Alert Response
        11. 38.3.2.11 Extended Command
        12. 38.3.2.12 Group Command
    4. 38.4 Controller Mode Operation
      1. 38.4.1 Configuration
      2. 38.4.2 Message Handling
        1. 38.4.2.1  Quick Command
        2. 38.4.2.2  Send Byte
        3. 38.4.2.3  Receive Byte
        4. 38.4.2.4  Write Byte and Write Word
        5. 38.4.2.5  Read Byte and Read Word
        6. 38.4.2.6  Process Call
        7. 38.4.2.7  Block Write
        8. 38.4.2.8  Block Read
        9. 38.4.2.9  Block Write-Block Read Process Call
        10. 38.4.2.10 Alert Response
        11. 38.4.2.11 Extended Command
        12. 38.4.2.12 Group Command
    5. 38.5 Software
      1. 38.5.1 PMBUS Registers to Driverlib Functions
    6. 38.6 PMBUS Registers
      1. 38.6.1 PMBUS Base Address Table
      2. 38.6.2 PMBUS_REGS Registers
  41. 39Universal Asynchronous Receiver/Transmitter (UART)
    1. 39.1 Introduction
      1. 39.1.1 Features
      2. 39.1.2 UART Related Collateral
      3. 39.1.3 Block Diagram
    2. 39.2 Functional Description
      1. 39.2.1 Transmit and Receive Logic
      2. 39.2.2 Baud-Rate Generation
      3. 39.2.3 Data Transmission
      4. 39.2.4 Serial IR (SIR)
      5. 39.2.5 9-Bit UART Mode
      6. 39.2.6 FIFO Operation
      7. 39.2.7 Interrupts
      8. 39.2.8 Loopback Operation
      9. 39.2.9 RTDMA Operation
        1. 39.2.9.1 Receiving Data Using UART with RTDMA
        2. 39.2.9.2 Transmitting Data Using UART with RTDMA
    3. 39.3 Initialization and Configuration
    4. 39.4 Software
      1. 39.4.1 UART Registers to Driverlib Functions
      2. 39.4.2 UART Examples
        1. 39.4.2.1 UART Loopback - SINGLE_CORE
        2. 39.4.2.2 UART Loopback with Interrupt - SINGLE_CORE
        3. 39.4.2.3 UART Loopback with DMA - SINGLE_CORE
        4. 39.4.2.4 UART Echoback - SINGLE_CORE
    5. 39.5 UART Registers
      1. 39.5.1 UART Base Address Table
      2. 39.5.2 UART_REGS Registers
      3. 39.5.3 UART_REGS_WRITE Registers
  42. 40Local Interconnect Network (LIN)
    1. 40.1 LIN Overview
      1. 40.1.1 LIN Mode Features
      2. 40.1.2 SCI Mode Features
      3. 40.1.3 Block Diagram
    2. 40.2 Serial Communications Interface Module
      1. 40.2.1 SCI Communication Formats
        1. 40.2.1.1 SCI Frame Formats
        2. 40.2.1.2 SCI Asynchronous Timing Mode
        3. 40.2.1.3 SCI Baud Rate
          1. 40.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 40.2.1.4 SCI Multiprocessor Communication Modes
          1. 40.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 40.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 40.2.1.5 SCI Multibuffered Mode
      2. 40.2.2 SCI Interrupts
        1. 40.2.2.1 Transmit Interrupt
        2. 40.2.2.2 Receive Interrupt
        3. 40.2.2.3 WakeUp Interrupt
        4. 40.2.2.4 Error Interrupts
      3. 40.2.3 SCI RTDMA Interface
        1. 40.2.3.1 Receive RTDMA Requests
        2. 40.2.3.2 Transmit RTDMA Requests
      4. 40.2.4 SCI Configurations
        1. 40.2.4.1 Receiving Data
          1. 40.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 40.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 40.2.4.2 Transmitting Data
          1. 40.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 40.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 40.2.5 SCI Low-Power Mode
        1. 40.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 40.3 Local Interconnect Network Module
      1. 40.3.1 LIN Communication Formats
        1. 40.3.1.1  LIN Standards
        2. 40.3.1.2  Message Frame
          1. 40.3.1.2.1 Message Header
          2. 40.3.1.2.2 Response
        3. 40.3.1.3  Synchronizer
        4. 40.3.1.4  Baud Rate
          1. 40.3.1.4.1 Fractional Divider
          2. 40.3.1.4.2 Superfractional Divider
            1. 40.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 40.3.1.5  Header Generation
          1. 40.3.1.5.1 Event Triggered Frame Handling
          2. 40.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 40.3.1.6  Extended Frames Handling
        7. 40.3.1.7  Timeout Control
          1. 40.3.1.7.1 No-Response Error (NRE)
          2. 40.3.1.7.2 Bus Idle Detection
          3. 40.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 40.3.1.8  TXRX Error Detector (TED)
          1. 40.3.1.8.1 Bit Errors
          2. 40.3.1.8.2 Physical Bus Errors
          3. 40.3.1.8.3 ID Parity Errors
          4. 40.3.1.8.4 Checksum Errors
        9. 40.3.1.9  Message Filtering and Validation
        10. 40.3.1.10 Receive Buffers
        11. 40.3.1.11 Transmit Buffers
      2. 40.3.2 LIN Interrupts
      3. 40.3.3 Servicing LIN Interrupts
      4. 40.3.4 LIN RTDMA Interface
        1. 40.3.4.1 LIN Receive RTDMA Requests
        2. 40.3.4.2 LIN Transmit RTDMA Requests
      5. 40.3.5 LIN Configurations
        1. 40.3.5.1 Receiving Data
          1. 40.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 40.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 40.3.5.2 Transmitting Data
          1. 40.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 40.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 40.4 Low-Power Mode
      1. 40.4.1 Entering Sleep Mode
      2. 40.4.2 Wakeup
      3. 40.4.3 Wakeup Timeouts
    5. 40.5 Emulation Mode
    6. 40.6 Software
      1. 40.6.1 LIN Registers to Driverlib Functions
      2. 40.6.2 LIN Examples
        1. 40.6.2.1 LIN Internal Loopback with Interrupts - SINGLE_CORE
        2. 40.6.2.2 LIN SCI Mode Internal Loopback with Interrupts - SINGLE_CORE
        3. 40.6.2.3 LIN SCI MODE Internal Loopback with DMA - SINGLE_CORE
        4. 40.6.2.4 LIN Internal Loopback without interrupts (polled mode) - SINGLE_CORE
        5. 40.6.2.5 LIN SCI MODE (Single Buffer) Internal Loopback with DMA - SINGLE_CORE
    7. 40.7 LIN Registers
      1. 40.7.1 LIN Base Address Table
      2. 40.7.2 LIN_REGS Registers
  43. 41Serial Peripheral Interface (SPI)
    1. 41.1 Introduction
      1. 41.1.1 Features
      2. 41.1.2 Block Diagram
    2. 41.2 System-Level Integration
      1. 41.2.1 SPI Module Signals
      2. 41.2.2 Configuring Device Pins
        1. 41.2.2.1 GPIOs Required for High-Speed Mode
      3. 41.2.3 SPI Interrupts
      4. 41.2.4 RTDMA Support
    3. 41.3 SPI Operation
      1. 41.3.1  Introduction to Operation
      2. 41.3.2  Controller Mode
      3. 41.3.3  Peripheral Mode
      4. 41.3.4  Data Format
        1. 41.3.4.1 Transmission of Bit from SPIRXBUF
      5. 41.3.5  Baud Rate Selection
        1. 41.3.5.1 Baud Rate Determination
        2. 41.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
        3. 41.3.5.3 Baud Rate Calculation
      6. 41.3.6  SPI Clocking Schemes
      7. 41.3.7  SPI FIFO Description
      8. 41.3.8  SPI RTDMA Transfers
        1. 41.3.8.1 Transmitting Data Using SPI with RTDMA
        2. 41.3.8.2 Receiving Data Using SPI with RTDMA
      9. 41.3.9  SPI High-Speed Mode
      10. 41.3.10 SPI 3-Wire Mode Description
    4. 41.4 Programming Procedure
      1. 41.4.1 Initialization Upon Reset
      2. 41.4.2 Configuring the SPI
      3. 41.4.3 Configuring the SPI for High-Speed Mode
      4. 41.4.4 Data Transfer Example
      5. 41.4.5 SPI 3-Wire Mode Code Examples
        1. 41.4.5.1 3-Wire Controller Mode Transmit
        2.       1703
          1. 41.4.5.2.1 3-Wire Controller Mode Receive
        3.       1705
          1. 41.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       1707
          1. 41.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 41.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 41.5 Software
      1. 41.5.1 SPI Registers to Driverlib Functions
      2. 41.5.2 SPI Examples
        1. 41.5.2.1 SPI Digital Loopback - SINGLE_CORE
        2. 41.5.2.2 SPI Digital Loopback with FIFO Interrupts - SINGLE_CORE
        3. 41.5.2.3 SPI Digital External Loopback without FIFO Interrupts - SINGLE_CORE
        4. 41.5.2.4 SPI Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        5. 41.5.2.5 SPI Digital Loopback with DMA - SINGLE_CORE
    6. 41.6 SPI Registers
      1. 41.6.1 SPI Base Address Table
      2. 41.6.2 SPI_REGS Registers
  44. 42Single Edge Nibble Transmission (SENT)
    1. 42.1 Introduction
      1. 42.1.1 Features
      2. 42.1.2 SENT Related Collateral
    2. 42.2 Advanced Topologies: MTPG
      1. 42.2.1 MTPG Features
      2. 42.2.2 MTPG Description
      3. 42.2.3 Channel Triggers
      4. 42.2.4 Timeout
    3. 42.3 Protocol Description
      1. 42.3.1 Nibble Frame Format
      2. 42.3.2 CRC
      3. 42.3.3 Short Serial Message Format
      4. 42.3.4 Enhanced Serial Message Format
      5. 42.3.5 Enhanced Serial Message Format CRC
      6. 42.3.6 Receive Modes
    4. 42.4 RTDMA Trigger
    5. 42.5 Interrupts Configuration
    6. 42.6 Glitch Filter
    7. 42.7 Software
      1. 42.7.1 SENT Registers to Driverlib Functions
      2. 42.7.2 SENT Examples
        1. 42.7.2.1 SENT Single Sensor - SINGLE_CORE
    8. 42.8 SENT Registers
      1. 42.8.1 SENT Base Address Table
      2. 42.8.2 SENT_CFG Registers
      3. 42.8.3 SENT_MEM Registers
      4. 42.8.4 SENT_MTPG Registers
  45. 43â–º SECURITY PERIPHERALS
    1.     Technical Reference Manual Overview
  46. 44Security Modules
    1. 44.1 Hardware Security Module (HSM)
      1. 44.1.1 HSM Related Collateral
    2. 44.2 Cryptographic Accelerators
  47. 45Revision History

17.8.1.1 ERAD_REGS Registers

Table 17-6 lists the memory-mapped registers for the ERAD_REGS registers. All register offset addresses not listed in Table 17-6 should be considered as reserved locations and the register contents should not be modified.

Table 17-6 ERAD_REGS Registers
OffsetAcronymRegister NameProtection
0hGLBL_ERAD_IDDebug Peripheral ID
4hGLBL_EVENT_STATGlobal Event Status Register
40h + formulaEBC_OWNER_jEBC Owner Register
44h + formulaEBC_CNTL_jEBC Control Register
48h + formulaEBC_STATUS_jEBC Status Register
4Ch + formulaEBC_STATUSCLEAR_jEBC Clear Register
50h + formulaEBC_REFL_jEBC Reference Low Register
54h + formulaEBC_REFH_jEBC Reference High Register
58h + formulaEBC_MASKL_jEBC Mask Low Register
5Ch + formulaEBC_MASKH_jEBC Mask High Register
60h + formulaEBC_WP_PC_jEBC Watchpoint PC Register
440h + formulaSEC_OWNER_jSEC Owner Register
444h + formulaSEC_CNTL_jSEC Control Register
448h + formulaSEC_STATUS_jSEC Status Register
44Ch + formulaSEC_STATUSCLEAR_jSEC Clear Register
450h + formulaSEC_REF_jSEC Reference Register
454h + formulaSEC_INPUT_SEL1_jSEC Input Select Register1
458h + formulaSEC_INPUT_SEL2_jSEC Input Select Register2
45Ch + formulaSEC_INPUT_COND_jSEC Input Conditioning Register
460h + formulaSEC_COUNT_jSEC Counter Register
464h + formulaSEC_MAX_COUNT_jSEC Max Count Register
468h + formulaSEC_MIN_COUNT_jSEC Min Count Register
640h + formulaAND_MASK_OWNER_jAND Owner Register
644h + formulaAND_MASK_CTL_jAND Control Register
648h + formulaEVENT_AND_MASK_jAND Event Selection Register
740h + formulaOR_MASK_OWNER_jOR Owner Register
744h + formulaOR_MASK_CTL_jOR Control Register
748h + formulaEVENT_OR_MASK_jOR Event Selection Register
840hPCTRACE_OWNEROwner Register
844hPCTRACE_GLOBALGlobal Control Register
848hPCTRACE_BUFFERTrace Buffer pointer register
84ChPCTRACE_QUAL1Trace Qualifier register 1
850hPCTRACE_QUAL2Trace Qualifier register 2
854hPCTRACE_LOGPC_SOFTENABLEPC when PC Trace was last enabled by software
858hPCTRACE_LOGPC_SOFTDISABLEPC when PC Trace was last disabled by software
1000h + formulaPCTRACE_BUFFER_BASE_yTrace Buffer Base address

Complex bit access types are encoded to fit into small table cells. Table 17-7 shows the codes that are used for access types in this section.

Table 17-7 ERAD_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

8.1.1.1 GLBL_ERAD_ID Register (Offset = 0h) [Reset = 62090000h]

GLBL_ERAD_ID is shown in Figure 17-9 and described in Table 17-8.

Return to the Summary Table.

Debug Peripheral ID

Figure 17-9 GLBL_ERAD_ID Register
3130292827262524
RESERVEDRESERVEDFUNC
R-1hR-2hR-209h
2322212019181716
FUNC
R-209h
15141312111098
RESERVEDMAJOR
R-0hR-0h
76543210
CUSTOMMINOR
R-0hR-0h
Table 17-8 GLBL_ERAD_ID Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR1hReserved
29-28RESERVEDR2hReserved
27-16FUNCR209h0x209 => C29 Embedded Real-Time Analysis and Diagnostics

Reset type: SYSRSn

15-11RESERVEDR0hReserved
10-8MAJORR0hBased on RTL Version

Reset type: SYSRSn

7-6CUSTOMR0hBased on RTL Version

Reset type: SYSRSn

5-0MINORR0hBased on RTL Version

Reset type: SYSRSn

8.1.1.2 GLBL_EVENT_STAT Register (Offset = 4h) [Reset = 00000000h]

GLBL_EVENT_STAT is shown in Figure 17-10 and described in Table 17-9.

Return to the Summary Table.

Global Event Status Register

Figure 17-10 GLBL_EVENT_STAT Register
313029282726252423222120191817161514131211109876543210
SECEBC
R-0hR-0h
Table 17-9 GLBL_EVENT_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-16SECR0hThis bit directly reflects the state of the EVENT_FIRED bit of the SEC unit x.
0 No Event
1 Event Fired
Bit-16 SEC1
Bit-17 SEC2
....
Bit-(n-15) SECn

Reset type: ERAD_RESET

15-0EBCR0hThis bit directly reflects the state of the EVENT_FIRED bit of the EBC unit x.
0 No Event
1 Event Fired
Bit-0 EBC1
Bit-1 EBC2
....
Bit-n EBCn

Reset type: ERAD_RESET

8.1.1.3 EBC_OWNER_j Register (Offset = 40h + formula) [Reset = 00000000h]

EBC_OWNER_j is shown in Figure 17-11 and described in Table 17-10.

Return to the Summary Table.

EBC Owner Register

Offset = 40h + (j * 40h); where j = 0h to 7h

Figure 17-11 EBC_OWNER_j Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCONFIGSEM
R-0hR-0hR-0h
15141312111098
RESERVEDSROOTZONE
R-0hR-0hR-0h
76543210
RESERVEDOWNER
R-0hR/W-0h
Table 17-10 EBC_OWNER_j Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18-17CONFIGR0h00 => EBC Full
01 => EBC Lite
Others => Reserved

Reset type: ERAD_RESET

16SEMR0h1 => Access and owner from same zone (Additionally if SROOT LINK owns the block and access originated from SROOTLINK area)
0 => Access and owner from different zone (Additionally if SROOT LINK owns the block, but access originated from a non SROOT LINK area)
These bits are only valid when OWNER = 10 (App owned)

Reset type: ERAD_RESET

15-13RESERVEDR0hReserved
12SROOTR0h0 => This block is not owned by SROOT LINK
1 => This block is owned by SROOT LINK

Reset type: ERAD_RESET

11-8ZONER0h0000 => Zone-0
0001 => Zone-1
0010 => Zone-2
0011 => Zone-3
All others => Reserved
These bits are only valid when OWNER = 10 (App owned)

Reset type: ERAD_RESET

7-2RESERVEDR0hReserved
1-0OWNERR/W0h00 => No Owner
01 => Debug Owned
10 => App Owned
11 => Reserved
Debugger :
Read-> Returns current ownership ID
Writes -> Allowed only if current value is 00 or 01
Application:
Read-> Returns current ownership ID
Writes -> Allowed only if current value is 00 or 10
NOTE : When a 00 gets successfully written, all the rest of control/status registers gets reset/cleared

Reset type: ERAD_RESET

8.1.1.4 EBC_CNTL_j Register (Offset = 44h + formula) [Reset = 00000000h]

EBC_CNTL_j is shown in Figure 17-12 and described in Table 17-11.

Return to the Summary Table.

EBC Control Register

Offset = 44h + (j * 40h); where j = 0h to 7h

Figure 17-12 EBC_CNTL_j Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDSPSEL
R-0hR/W-0h
15141312111098
SPSELSPSEL_MATCH_ENSTACK_QUALCOMP_MODENMI_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
INTERRUPTHALTBUS_SELEN
R/W-0hR/W-0hR/W-0hR/W-0h
Table 17-11 EBC_CNTL_j Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17-14SPSELR/W0hStack pointer Select value to be used for SPSEL match.

Reset type: ERAD_RESET

13SPSEL_MATCH_ENR/W0h0 = SPSEL match disabled
1 = SPSEL match enabled
This bit is relevant only for data read and data write address comparison.
When enabled, SPSEL match will additionally be considered to generate a match.

Reset type: ERAD_RESET

12STACK_QUALR/W0h0 = Stack access qualifier disabled
1 = Stack access qualifier enabled
This bit is relevant only for data read and data write address comparison.
When enabled, the corresponding stack access qualifier will additionally be considered to generate a match.

Reset type: ERAD_RESET

11-9COMP_MODER/W0hEBC compare modes:

000 Regular masked compare
EBC_MSK will be ignored for the following modes:
100 Bus value GT EBC_REF
101 Bus value GE EBC_REF
110 Bus value LT EBC_REF
111 Bus value LE EBC_REF
GT means Greater Than
GE means Greater or Equal
LT means Less Than
LE means Lesser or Equal

Reset type: ERAD_RESET

8NMI_ENR/W0h0 = Will assert ERAD interrupt
1 = Will assert NMI (With only exception of BUS_SEL = PAB, which will not generate any interrupt or event or NMI. This is only used for breakpoints by debug controller)

Reset type: ERAD_RESET

7INTERRUPTR/W0hThis bit decides whether the EBC unit will generate interrupt when event matches occur.
Note that the event outputs will always be generated regardless of the state of this bit.

0 The EBC unit will not cause any action towards the CPU.
1 The EBC unit will assert NMI/ERAD interrupt based on NMI_EN bit for matching data accesses (With only exception of BUS_SEL = PAB, which will not generate any interrupt or event or NMI. This is only used for breakpoints by debug controller)

Reset type: ERAD_RESET

6HALTR/W0hThis bit decides whether the EBC unit will generate CPU halting signals when event matches occur. Note that the event outputs will always be generated regardless of the state of this bit.

0 The EBC unit will not cause any action towards halting the CPU.
1 The EBC unit will assert break tags for matching program fetches(Breakpoint) and Halt request rest of the matching accesses(Watchpoint). These can cause the CPU to HALT

Reset type: ERAD_RESET

5-1BUS_SELR/W0h00000 PAB for instruction fetches
00001 DWAB for data write accesses
00101 DRAB_W address aligned with RDATA1/RDATA2 (either DRAB1_W/DRAB2_W)
00110 DRAB1_W address aligned with RDATA1
00111 DRAB2_W address aligned with RDATA2
01000 DWDB for write data match
01001 DRDB for read data match (either DRDB1/2)
01010 DRDB1 for read data match (RDATA1)
01011 DRDB2 for read data match (RDATA1)
01100 VPC Instruction aligned match (VPC for R1 phase)
01110 VPC W aligned match (VPC for Write address/data phase/Read data phase)
Others Reserved

Reset type: ERAD_RESET

0ENR/W0h0 = EBC Disabled
1 = EBC Enabled

Reset type: ERAD_RESET

8.1.1.5 EBC_STATUS_j Register (Offset = 48h + formula) [Reset = 00000000h]

EBC_STATUS_j is shown in Figure 17-13 and described in Table 17-12.

Return to the Summary Table.

EBC Status Register

Offset = 48h + (j * 40h); where j = 0h to 7h

Figure 17-13 EBC_STATUS_j Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDSTATUS
R-0hR-0h
76543210
RESERVEDEVENT_FIRED
R-0hR-0h
Table 17-12 EBC_STATUS_j Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-8STATUSR0hEBC status:
00 Idle
10 Enabled
11 Completed

Reset type: ERAD_RESET

7-1RESERVEDR0hReserved
0EVENT_FIREDR0hThis is a sticky bit which gets set every time the EBC unit generates a match event. This will be used by software to figure out whether this EBC module fired an event or not. This bit will get cleared by writing a '1' to bit 0 of the EBC_STATUSCLEAR register.

Reset type: ERAD_RESET

8.1.1.6 EBC_STATUSCLEAR_j Register (Offset = 4Ch + formula) [Reset = 00000000h]

EBC_STATUSCLEAR_j is shown in Figure 17-14 and described in Table 17-13.

Return to the Summary Table.

EBC Clear Register

Offset = 4Ch + (j * 40h); where j = 0h to 7h

Figure 17-14 EBC_STATUSCLEAR_j Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEVENT_FIRED
R-0hW1C-0h
Table 17-13 EBC_STATUSCLEAR_j Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0EVENT_FIREDW1C0hEvent Clear register:

0 No action.
1 A write with this bit set to 1 will clear the sticky EVENT_FIRED bit in the EBC_STATUS register and bring the EBC statemachine status back to ENABLED state if EBC is enabled or IDLE state if EBC is disabled.
Reads of this bit position will always return a 0.
Note : If hardware is trying to set EVENT_FIRED bit at the same cycle software is trying to clear, then the clear will be ignored and status will remain set

Reset type: ERAD_RESET

8.1.1.7 EBC_REFL_j Register (Offset = 50h + formula) [Reset = 00000000h]

EBC_REFL_j is shown in Figure 17-15 and described in Table 17-14.

Return to the Summary Table.

EBC Reference Low Register

Offset = 50h + (j * 40h); where j = 0h to 7h

Figure 17-15 EBC_REFL_j Register
313029282726252423222120191817161514131211109876543210
REF
R/W-0h
Table 17-14 EBC_REFL_j Register Field Descriptions
BitFieldTypeResetDescription
31-0REFR/W0hThis register contains the lower 32-bits of the 64-bit reference used for comparison. The contents of this register are used along with the mask register to determine the address match. The equation used to determine a match is as follows. Match is true if,
(compare bus | mask) == (reference | mask)
This register is writable by CPU only if application owns the unit. Otherwise, the writes are ignored. The register is writable by the debugger only if the debugger owns this unit. Otherwise, debugger writes are ignored.
Note : compare bus = {REFH[31:0],REFL{31:0}
REFH and REFL are used in conjunction for 64-bit bus compares. So always disable, program the reference registers H,L and then re-enable for 64-bit comparison.

Reset type: ERAD_RESET

8.1.1.8 EBC_REFH_j Register (Offset = 54h + formula) [Reset = 00000000h]

EBC_REFH_j is shown in Figure 17-16 and described in Table 17-15.

Return to the Summary Table.

EBC Reference High Register

Offset = 54h + (j * 40h); where j = 0h to 7h

Figure 17-16 EBC_REFH_j Register
313029282726252423222120191817161514131211109876543210
REF
R/W-0h
Table 17-15 EBC_REFH_j Register Field Descriptions
BitFieldTypeResetDescription
31-0REFR/W0hThis register contains the top 32-bits of the 64-bit reference used for comparison. The contents of this register are used along with the mask register to determine the address match. The equation used to determine a match is as follows. Match is true if,
(compare bus | mask) == (reference | mask)
This register is writable by CPU only if application owns the unit. Otherwise, the writes are ignored. The register is writable by the debugger only if the debugger owns this unit. Otherwise, debugger writes are ignored.
Note : compare bus = {REFH[31:0],REFL{31:0}
REFH and REFL are used in conjunction for 64-bit bus compares. So always disable, program the reference registers H,L and then re-enable for 64-bit comparison.

Reset type: ERAD_RESET

8.1.1.9 EBC_MASKL_j Register (Offset = 58h + formula) [Reset = 00000000h]

EBC_MASKL_j is shown in Figure 17-17 and described in Table 17-16.

Return to the Summary Table.

EBC Mask Low Register

Offset = 58h + (j * 40h); where j = 0h to 7h

Figure 17-17 EBC_MASKL_j Register
313029282726252423222120191817161514131211109876543210
MASK
R/W-0h
Table 17-16 EBC_MASKL_j Register Field Descriptions
BitFieldTypeResetDescription
31-0MASKR/W0hThis register contains the lower 32-bits of the 64-bit mask used for comparison. The contents of this register are used along with the reference register to determine the address match. The equation used to determine a match is as follows. Match is true if,
(compare bus | mask) == (reference | mask)
This register is writable by CPU only if application owns the unit. Otherwise, the writes are ignored. The register is writable by the debugger only if the debugger owns this unit. Otherwise, the writes are ignored.
Note : mask = {MASKH[31:0],MASKL{31:0}
MASKH and MASKL are used in conjunction for 64-bit bus compares. So always disable, program the reference registers H,L and then re-enable for 64-bit comparison.
Important Note : If PAB is chosen for comparison and masks are enabled, then the following restriction apply. MASKL[3:0] can only take one of the following values 0x0, 0x1, 0x3, 0x7 & 0xF. Rest of the mask bits can be chosen freely based on need.

Reset type: ERAD_RESET

8.1.1.10 EBC_MASKH_j Register (Offset = 5Ch + formula) [Reset = 00000000h]

EBC_MASKH_j is shown in Figure 17-18 and described in Table 17-17.

Return to the Summary Table.

EBC Mask High Register

Offset = 5Ch + (j * 40h); where j = 0h to 7h

Figure 17-18 EBC_MASKH_j Register
313029282726252423222120191817161514131211109876543210
MASK
R/W-0h
Table 17-17 EBC_MASKH_j Register Field Descriptions
BitFieldTypeResetDescription
31-0MASKR/W0hThis register contains the higher 32-bits of the 64-bit mask used for comparison. The contents of this register are used along with the reference register to determine the address match. The equation used to determine a match is as follows. Match is true if,
(compare bus | mask) == (reference | mask)
This register is writable by CPU only if application owns the unit. Otherwise, the writes are ignored. The register is writable by the debugger only if the debugger owns this unit. Otherwise, the writes are ignored.
Note : mask = {MASKH[31:0],MASKL{31:0}
MASKH and MASKL are used in conjunction for 64-bit bus compares. So always disable, program the reference registers H,L and then re-enable for 64-bit comparison.

Reset type: ERAD_RESET

8.1.1.11 EBC_WP_PC_j Register (Offset = 60h + formula) [Reset = 00000000h]

EBC_WP_PC_j is shown in Figure 17-19 and described in Table 17-18.

Return to the Summary Table.

EBC Watchpoint PC Register

Offset = 60h + (j * 40h); where j = 0h to 7h

Figure 17-19 EBC_WP_PC_j Register
313029282726252423222120191817161514131211109876543210
PC
R-0h
Table 17-18 EBC_WP_PC_j Register Field Descriptions
BitFieldTypeResetDescription
31-0PCR0hThis register captures the PC of instruction which caused the watchpoint. This is valid for Data read/write related bus selects only

Reset type: ERAD_RESET

8.1.1.12 SEC_OWNER_j Register (Offset = 440h + formula) [Reset = 00000000h]

SEC_OWNER_j is shown in Figure 17-20 and described in Table 17-19.

Return to the Summary Table.

SEC Owner Register

Offset = 440h + (j * 40h); where j = 0h to 3h

Figure 17-20 SEC_OWNER_j Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCONFIGSEM
R-0hR-0hR-0h
15141312111098
RESERVEDSROOTZONE
R-0hR-0hR-0h
76543210
RESERVEDOWNER
R-0hR/W-0h
Table 17-19 SEC_OWNER_j Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18-17CONFIGR0h00 => SEC Full
01 => SEC Lite
Others => Reserved

Reset type: ERAD_RESET

16SEMR0h1 => Access and owner from same zone (Additionally if SROOT LINK owns the block and access originated from SROOTLINK area)
0 => Access and owner from different zone (Additionally if SROOT LINK owns the block, but access originated from a non SROOT LINK area)
These bits are only valid when OWNER = 10 (App owned)

Reset type: ERAD_RESET

15-13RESERVEDR0hReserved
12SROOTR0h0 => This block is not owned by SROOT LINK
1 => This block is owned by SROOT LINK

Reset type: ERAD_RESET

11-8ZONER0h0000 => Zone-0
0001 => Zone-1
0010 => Zone-2
0011 => Zone-3
All others => Reserved
These bits are only valid when OWNER = 10 (App owned)

Reset type: ERAD_RESET

7-2RESERVEDR0hReserved
1-0OWNERR/W0h00 => No Owner
01 => Debug Owned
10 => App Owned
11 => Reserved
Debugger :
Read-> Returns current ownership ID
Writes -> Allowed only if current value is 00 or 01
Application:
Read-> Returns current ownership ID
Writes -> Allowed only if current value is 00 or 10
NOTE : When a 00 gets successfully written, all the rest of control/status registers gets reset/cleared

Reset type: ERAD_RESET

8.1.1.13 SEC_CNTL_j Register (Offset = 444h + formula) [Reset = 00000000h]

SEC_CNTL_j is shown in Figure 17-21 and described in Table 17-20.

Return to the Summary Table.

SEC Control Register

Offset = 444h + (j * 40h); where j = 0h to 3h

Figure 17-21 SEC_CNTL_j Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDFREE_RUNRST_INP_SEL_ENCNT_INP_SEL_EN
R-0hR/W-0hR/W-0hR/W-0h
76543210
NMI_ENINTERRUPTHALTRST_ON_MATCHSTART_STOP_CUMULATIVESTART_STOP_MODEEDGE_LEVELEN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 17-20 SEC_CNTL_j Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10FREE_RUNR/W0h0 = CPU halt is ignored by the SEC counter all times
1 = CPU halt with stop the counter until CPU is halted. i.e. If counter gets enabled by SEC to count and CPU is halted then the counter stops counting until CPU is in halt state. Once the CPU resumes execution out of halt mode, then Counter will be active again.

Reset type: ERAD_RESET

9RST_INP_SEL_ENR/W0hThis bit decides if the reset input is enabled or not. Setting this to 1 will cause the counter to reset to zero whenever the selected reset input
goes active high. No event will be generated when the counter is reset. Setting this bit to 0 will cause the counter to ignore the reset inputs.

Reset type: ERAD_RESET

8CNT_INP_SEL_ENR/W0h0 = Disable using the input_select register for the count input. The counter will always count CPU cycles.
1 = Enable using the input_select register for the count input. The counter will count the event selected by the count input register.

Reset type: ERAD_RESET

7NMI_ENR/W0h0 = Will assert ERAD interrupt
1 = Will assert NMI

Reset type: ERAD_RESET

6INTERRUPTR/W0hThis bit decides whether the counter module will generate interrupt when count value matches the reference.
Note that the event outputs will always be generated regardless of the state of this bit.

0 SEC unit will not cause any action towards the CPU.
1 SEC unit will assert NMI/ERAD interrupt based on NMI_EN bit when the counter value matches the reference value.

Reset type: ERAD_RESET

5HALTR/W0hThis bit decides whether the counter module will generate a watchpoint to the CPU when the count value matches the reference.
Note that the event outputs will always be generated regardless of the state of this bit.

0 SEC unit will not cause any action towards halting the CPU.
1 SEC unit will assert Halt request rest of the matching accesses(Watchpoint). These can cause the CPU to HALT

Reset type: ERAD_RESET

4RST_ON_MATCHR/W0hThis bit is used to decide whether the counter will reset to zero once it reaches the reference value.

0 Counter will stay at the reference value and the counter will go to COMPLETED state and further counting will be stopped.
1 The counter will reset to zero once it reaches the match value and will stay enabled.

Reset type: ERAD_RESET

3START_STOP_CUMULATIVER/W0hThis bit decides whether the counter counts to give the cumulative cycle count for 'n' number of successive start stop events or clears the counter on very stop event to record the MAX_COUNT across successive start stop sequences.

0 When in START_STOP mode counter gets cleared on every stop event and MAX_COUNT records the max value
1 When in START_STOP mode counter keeps counting between successive start stop events to generate a cumulative count w/o clearing the counter on any stop events. MAX_COUNT register is invalid when this bit is set.

Reset type: ERAD_RESET

2START_STOP_MODER/W0hThis bit is used to decide whether the counter will count in the START_STOP mode or not.

0 Normal count mode. The counter will not depend on the START and STOP events
1 This is the START-STOP mode of the counter. The counter will start counting only after the START input has been asserted. It will continue to count the selected event till the STOP event is seen.

Reset type: ERAD_RESET

1EDGE_LEVELR/W0hThis bit is used to decide whether the counter will count the level of the event or the edge of the event.

0 Counter will increment the count as long as the count input is active high.
1 The counter will count only on the rising edge of the count input.
Note: If the selected counter input signal was already high when SEC{#}_INPUT_SEL1.CNT_INP_SEL gets configured, the counter will increment by 1 when enabled, even if edge counting mode is selected

Reset type: ERAD_RESET

0ENR/W0h0 = SEC Disabled
1 = SEC Enabled

Reset type: ERAD_RESET

8.1.1.14 SEC_STATUS_j Register (Offset = 448h + formula) [Reset = 00000000h]

SEC_STATUS_j is shown in Figure 17-22 and described in Table 17-21.

Return to the Summary Table.

SEC Status Register

Offset = 448h + (j * 40h); where j = 0h to 3h

Figure 17-22 SEC_STATUS_j Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDSTATUS
R-0hR-0h
76543210
RESERVEDOVERFLOWEVENT_FIRED
R-0hR-0hR-0h
Table 17-21 SEC_STATUS_j Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-8STATUSR0hSEC unit status
00 Idle
10 Enabled
11 Completed

Reset type: ERAD_RESET

7-2RESERVEDR0hReserved
1OVERFLOWR0hThis is a sticky bit which gets set every time the counter overflows and wraps around after reaching 0xffffffff.
This bit will get cleared by writing a '1' to OVERFLOW of SEC_STATUSCLEAR register.
Note : If hardware is trying to set OVERFLOW bit at the same cycle software is trying to clear, then the clear will be ignored and status will remain set

Reset type: ERAD_RESET

0EVENT_FIREDR0hThis is a sticky bit which gets set every time the SEC unit generates a match event. This will be used by software to figure out whether this SEC module fired an event or not.
This bit will get cleared by writing a '1' to EVENT of SEC_STATUSCLEAR register.
Note : If hardware is trying to set EVENT_FIRED bit at the same cycle software is trying to clear, then the clear will be ignored and status will remain set

Reset type: ERAD_RESET

8.1.1.15 SEC_STATUSCLEAR_j Register (Offset = 44Ch + formula) [Reset = 00000000h]

SEC_STATUSCLEAR_j is shown in Figure 17-23 and described in Table 17-22.

Return to the Summary Table.

SEC Clear Register

Offset = 44Ch + (j * 40h); where j = 0h to 3h

Figure 17-23 SEC_STATUSCLEAR_j Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDOVERFLOWEVENT_FIRED
R-0hW1C-0hW1C-0h
Table 17-22 SEC_STATUSCLEAR_j Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1OVERFLOWW1C0hClear OVERFLOW:

0 No action.
1 A write with this bit set to 1 will clear the sticky OVERFLOW bit in the SEC_STATUS register.
Reads of this bit position will always return a 0.

Reset type: ERAD_RESET

0EVENT_FIREDW1C0hClear EVENT_FIRED:

0 No action.
1 A write with this bit set to 1 will clear the sticky EVENT_FIRED bit in the SEC_STATUS register and bring the Breakpoint Module statemachine status back to ENABLED state if SEC is enable or IDLE state if SEC is disabled.
Reads of this bit position will always return a 0.

Reset type: ERAD_RESET

8.1.1.16 SEC_REF_j Register (Offset = 450h + formula) [Reset = FFFFFFFFh]

SEC_REF_j is shown in Figure 17-24 and described in Table 17-23.

Return to the Summary Table.

SEC Reference Register

Offset = 450h + (j * 40h); where j = 0h to 3h

Figure 17-24 SEC_REF_j Register
313029282726252423222120191817161514131211109876543210
REF
R/W-FFFFFFFFh
Table 17-23 SEC_REF_j Register Field Descriptions
BitFieldTypeResetDescription
31-0REFR/WFFFFFFFFhThis register contains the counter reference value for comparison. The counter will generate an event if the count value matches the reference register.
This register is writable by CPU only if application owns the unit, the writes are ignored.
The register is writable by the debugger only if the debugger owns this unit. Otherwise, the writes are ignored.

Reset type: ERAD_RESET

8.1.1.17 SEC_INPUT_SEL1_j Register (Offset = 454h + formula) [Reset = 00000000h]

SEC_INPUT_SEL1_j is shown in Figure 17-25 and described in Table 17-24.

Return to the Summary Table.

SEC Input Select Register1

Offset = 454h + (j * 40h); where j = 0h to 3h

Figure 17-25 SEC_INPUT_SEL1_j Register
31302928272625242322212019181716
RESERVEDRST_INP_SEL
R-0hR/W-0h
1514131211109876543210
RESERVEDCNT_INP_SEL
R-0hR/W-0h
Table 17-24 SEC_INPUT_SEL1_j Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16RST_INP_SELR/W0hThese bits decide are used to select the event input that will be used as the reset input. These bits matter only if the Enable Reset bit is set to 1.

Reset type: ERAD_RESET

15-8RESERVEDR0hReserved
7-0CNT_INP_SELR/W0hThese bits decide which of the inputs will be selected to enable counting. These inputs will be hooked up to the event outputs from the breakpoint module, counter module and to other system events

Reset type: ERAD_RESET

8.1.1.18 SEC_INPUT_SEL2_j Register (Offset = 458h + formula) [Reset = 00000000h]

SEC_INPUT_SEL2_j is shown in Figure 17-26 and described in Table 17-25.

Return to the Summary Table.

SEC Input Select Register2

Offset = 458h + (j * 40h); where j = 0h to 3h

Figure 17-26 SEC_INPUT_SEL2_j Register
31302928272625242322212019181716
RESERVEDSTO_INP_SEL
R-0hR/W-0h
1514131211109876543210
RESERVEDSTA_INP_SEL
R-0hR/W-0h
Table 17-25 SEC_INPUT_SEL2_j Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16STO_INP_SELR/W0hThese bits decide which of the inputs will be selected as the STOP event for the counter. These inputs will be hooked up to the event outputs from the breakpoint module, counter module and to other system events. The usage of these bits are relevant only in the START_STOP mode of counting.

Reset type: ERAD_RESET

15-8RESERVEDR0hReserved
7-0STA_INP_SELR/W0hThese bits decide which of the inputs will be selected as the START event for the counter. These inputs will be hooked up to the event outputs from the breakpoint module, counter module and to other system events. The usage of these bits are relevant only in the START_STOP mode of counting.

Reset type: ERAD_RESET

8.1.1.19 SEC_INPUT_COND_j Register (Offset = 45Ch + formula) [Reset = 00000000h]

SEC_INPUT_COND_j is shown in Figure 17-27 and described in Table 17-26.

Return to the Summary Table.

SEC Input Conditioning Register

Offset = 45Ch + (j * 40h); where j = 0h to 3h

Figure 17-27 SEC_INPUT_COND_j Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRST_INP_INVRESERVEDRESERVEDSTO_INP_INV
R-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDSTA_INP_INVRESERVEDRESERVEDSEC_INP_INV
R-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h
Table 17-26 SEC_INPUT_COND_j Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13RESERVEDR/W0hReserved
12RST_INP_INVR/W0hInvert the Selected Reset input

Reset type: ERAD_RESET

11-10RESERVEDR0hReserved
9RESERVEDR/W0hReserved
8STO_INP_INVR/W0hInvert the Selected Stop input

Reset type: ERAD_RESET

7-6RESERVEDR0hReserved
5RESERVEDR/W0hReserved
4STA_INP_INVR/W0hInvert the Selected Start input

Reset type: ERAD_RESET

3-2RESERVEDR0hReserved
1RESERVEDR/W0hReserved
0SEC_INP_INVR/W0hInvert the Selected Counter input

Reset type: ERAD_RESET

8.1.1.20 SEC_COUNT_j Register (Offset = 460h + formula) [Reset = 00000000h]

SEC_COUNT_j is shown in Figure 17-28 and described in Table 17-27.

Return to the Summary Table.

SEC Counter Register

Offset = 460h + (j * 40h); where j = 0h to 3h

Figure 17-28 SEC_COUNT_j Register
313029282726252423222120191817161514131211109876543210
COUNT
R/W-0h
Table 17-27 SEC_COUNT_j Register Field Descriptions
BitFieldTypeResetDescription
31-0COUNTR/W0hThis register contains the current count value.
The counter will generate an event if the count value matches the reference register (considering both upper and lower half of the register).

This register is writable by CPU only if application owns the unit. Otherwise, the writes are ignored.
The register is writable by the debugger only if the debugger owns this unit. Otherwise, the writes are ignored.
NOTE : CPU and Debugger writes based on ownership are given for clearing these registers for fresh start's. If attempted when hardware is also updating, then register writes are given lower priority.

Reset type: ERAD_RESET

8.1.1.21 SEC_MAX_COUNT_j Register (Offset = 464h + formula) [Reset = 00000000h]

SEC_MAX_COUNT_j is shown in Figure 17-29 and described in Table 17-28.

Return to the Summary Table.

SEC Max Count Register

Offset = 464h + (j * 40h); where j = 0h to 3h

Figure 17-29 SEC_MAX_COUNT_j Register
313029282726252423222120191817161514131211109876543210
MAX_COUNT
R/W-0h
Table 17-28 SEC_MAX_COUNT_j Register Field Descriptions
BitFieldTypeResetDescription
31-0MAX_COUNTR/W0hThis register contains the maximum recorded counter value. This is relevant only in the Start Stop mode of operation.
NOTE : CPU and Debugger writes based on ownership are given for clearing these registers for fresh start's. If attempted when hardware is also updating, then register writes are given lower priority.

Reset type: ERAD_RESET

8.1.1.22 SEC_MIN_COUNT_j Register (Offset = 468h + formula) [Reset = FFFFFFFFh]

SEC_MIN_COUNT_j is shown in Figure 17-30 and described in Table 17-29.

Return to the Summary Table.

SEC Min Count Register

Offset = 468h + (j * 40h); where j = 0h to 3h

Figure 17-30 SEC_MIN_COUNT_j Register
313029282726252423222120191817161514131211109876543210
MIN_COUNT
R/W-FFFFFFFFh
Table 17-29 SEC_MIN_COUNT_j Register Field Descriptions
BitFieldTypeResetDescription
31-0MIN_COUNTR/WFFFFFFFFhThis register contains the minimum recorded counter value. This is relevant only in the Start Stop mode of operation.
NOTE : CPU and Debugger writes based on ownership are given for clearing these registers for fresh start's. If attempted when hardware is also updating, then register writes are given lower priority.

Reset type: ERAD_RESET

8.1.1.23 AND_MASK_OWNER_j Register (Offset = 640h + formula) [Reset = 00000000h]

AND_MASK_OWNER_j is shown in Figure 17-31 and described in Table 17-30.

Return to the Summary Table.

AND Owner Register

Offset = 640h + (j * 20h); where j = 0h to 3h

Figure 17-31 AND_MASK_OWNER_j Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDSEM
R-0hR-0h
15141312111098
RESERVEDSROOTZONE
R-0hR-0hR-0h
76543210
RESERVEDOWNER
R-0hR/W-0h
Table 17-30 AND_MASK_OWNER_j Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16SEMR0h1 => Access and owner from same zone (Additionally if SROOT LINK owns the block and access originated from SROOTLINK area)
0 => Access and owner from different zone (Additionally if SROOT LINK owns the block, but access originated from a non SROOT LINK area)
These bits are only valid when OWNER = 10 (App owned)

Reset type: ERAD_RESET

15-13RESERVEDR0hReserved
12SROOTR0h0 => This block is not owned by SROOT LINK
1 => This block is owned by SROOT LINK

Reset type: ERAD_RESET

11-8ZONER0h0000 => Zone-0
0001 => Zone-1
0010 => Zone-2
0011 => Zone-3
All others => Reserved
These bits are only valid when OWNER = 10 (App owned)

Reset type: ERAD_RESET

7-2RESERVEDR0hReserved
1-0OWNERR/W0h00 => No Owner
01 => Debug Owned
10 => App Owned
11 => Reserved
Debugger :
Read-> Returns current ownership ID
Writes -> Allowed only if current value is 00 or 01
Application:
Read-> Returns current ownership ID
Writes -> Allowed only if current value is 00 or 10
NOTE : When a 00 gets successfully written, all the rest of control/status registers gets reset/cleared

Reset type: ERAD_RESET

8.1.1.24 AND_MASK_CTL_j Register (Offset = 644h + formula) [Reset = 00000000h]

AND_MASK_CTL_j is shown in Figure 17-32 and described in Table 17-31.

Return to the Summary Table.

AND Control Register

Offset = 644h + (j * 20h); where j = 0h to 3h

Figure 17-32 AND_MASK_CTL_j Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDNMI_ENINTERRUPTHALT
R-0hR/W-0hR/W-0hR/W-0h
Table 17-31 AND_MASK_CTL_j Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2NMI_ENR/W0h0 = Will assert ERAD interrupt
1 = Will assert NMI

Reset type: ERAD_RESET

1INTERRUPTR/W0hThis bit decides whether this unit will generate interrupt when event matches occur.
Note that the event outputs will always be generated regardless of the state of this bit.

0 This unit will not cause any action towards the CPU.
1 This unit will assert NMI/ERAD interrupt based on NMI_EN bit

Reset type: ERAD_RESET

0HALTR/W0hThis bit decides whether this unit will generate CPU halting signals when event matches occur.
Note that the event outputs will always be generated regardless of the state of this bit.

0 This unit will not cause any action towards halting the CPU.
1 This unit will assert Halt request rest of the matching accesses(Watchpoint). These can cause the CPU to HALT

Reset type: ERAD_RESET

8.1.1.25 EVENT_AND_MASK_j Register (Offset = 648h + formula) [Reset = 00FFFFFFh]

EVENT_AND_MASK_j is shown in Figure 17-33 and described in Table 17-32.

Return to the Summary Table.

AND Event Selection Register

Offset = 648h + (j * 20h); where j = 0h to 3h

Figure 17-33 EVENT_AND_MASK_j Register
313029282726252423222120191817161514131211109876543210
RESERVEDMASK_EBC
R-0hR/W-00FFFFFFh
Table 17-32 EVENT_AND_MASK_j Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0MASK_EBCR/W00FFFFFFhAND event mask
0 Corresponding EVENT is enabled for EBC_EVENT_AND1 output
1 Corresponding EVENT is masked for EBC_EVENT_AND1 output

Bit-0 EBC1
Bit-1 EBC2
....
Bit-15 EBC15

Bit-16 SEC1
Bit-17 SEC2
....
Bit-(23) SEC8

Reset type: ERAD_RESET

8.1.1.26 OR_MASK_OWNER_j Register (Offset = 740h + formula) [Reset = 00000000h]

OR_MASK_OWNER_j is shown in Figure 17-34 and described in Table 17-33.

Return to the Summary Table.

OR Owner Register

Offset = 740h + (j * 20h); where j = 0h to 3h

Figure 17-34 OR_MASK_OWNER_j Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDSEM
R-0hR-0h
15141312111098
RESERVEDSROOTZONE
R-0hR-0hR-0h
76543210
RESERVEDOWNER
R-0hR/W-0h
Table 17-33 OR_MASK_OWNER_j Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16SEMR0h1 => Access and owner from same zone (Additionally if SROOT LINK owns the block and access originated from SROOTLINK area)
0 => Access and owner from different zone (Additionally if SROOT LINK owns the block, but access originated from a non SROOT LINK area)
These bits are only valid when OWNER = 10 (App owned)

Reset type: ERAD_RESET

15-13RESERVEDR0hReserved
12SROOTR0h0 => This block is not owned by SROOT LINK
1 => This block is owned by SROOT LINK

Reset type: ERAD_RESET

11-8ZONER0h0000 => Zone-0
0001 => Zone-1
0010 => Zone-2
0011 => Zone-3
All others => Reserved
These bits are only valid when OWNER = 10 (App owned)

Reset type: ERAD_RESET

7-2RESERVEDR0hReserved
1-0OWNERR/W0h00 => No Owner
01 => Debug Owned
10 => App Owned
11 => Reserved
Debugger :
Read-> Returns current ownership ID
Writes -> Allowed only if current value is 00 or 01
Application:
Read-> Returns current ownership ID
Writes -> Allowed only if current value is 00 or 10
NOTE : When a 00 gets successfully written, all the rest of control/status registers gets reset/cleared

Reset type: ERAD_RESET

8.1.1.27 OR_MASK_CTL_j Register (Offset = 744h + formula) [Reset = 00000000h]

OR_MASK_CTL_j is shown in Figure 17-35 and described in Table 17-34.

Return to the Summary Table.

OR Control Register

Offset = 744h + (j * 20h); where j = 0h to 3h

Figure 17-35 OR_MASK_CTL_j Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDNMI_ENINTERRUPTHALT
R-0hR/W-0hR/W-0hR/W-0h
Table 17-34 OR_MASK_CTL_j Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2NMI_ENR/W0h0 = Will assert ERAD interrupt
1 = Will assert NMI

Reset type: ERAD_RESET

1INTERRUPTR/W0hThis bit decides whether this unit will generate interrupt when event matches occur.
Note that the event outputs will always be generated regardless of the state of this bit.

0 This unit will not cause any action towards the CPU.
1 This unit will assert NMI/ERAD interrupt based on NMI_EN bit

Reset type: ERAD_RESET

0HALTR/W0hThis bit decides whether this unit will generate CPU halting signals when event matches occur.
Note that the event outputs will always be generated regardless of the state of this bit.

0 This unit will not cause any action towards halting the CPU.
1 This unit will assert Halt request rest of the matching accesses(Watchpoint). These can cause the CPU to HALT

Reset type: ERAD_RESET

8.1.1.28 EVENT_OR_MASK_j Register (Offset = 748h + formula) [Reset = 00FFFFFFh]

EVENT_OR_MASK_j is shown in Figure 17-36 and described in Table 17-35.

Return to the Summary Table.

OR Event Selection Register

Offset = 748h + (j * 20h); where j = 0h to 3h

Figure 17-36 EVENT_OR_MASK_j Register
313029282726252423222120191817161514131211109876543210
RESERVEDMASK_EBC
R-0hR/W-00FFFFFFh
Table 17-35 EVENT_OR_MASK_j Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0MASK_EBCR/W00FFFFFFhOR event mask
0 Corresponding EVENT is enabled for EBC_EVENT_OR1 output
1 Corresponding EVENT is masked for EBC_EVENT_OR1 output

Bit-0 EBC1
Bit-1 EBC2
....
Bit-15 EBC15

Bit-16 SEC1
Bit-17 SEC2
....
Bit-(23) SECn

Reset type: ERAD_RESET

8.1.1.29 PCTRACE_OWNER Register (Offset = 840h) [Reset = 00000000h]

PCTRACE_OWNER is shown in Figure 17-37 and described in Table 17-36.

Return to the Summary Table.

Owner Register

Figure 17-37 PCTRACE_OWNER Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDSEM
R-0hR-0h
15141312111098
RESERVEDSROOTZONE
R-0hR-0hR-0h
76543210
RESERVEDOWNER
R-0hR/W-0h
Table 17-36 PCTRACE_OWNER Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16SEMR0h1 => Access and owner from same zone (Additionally if SROOT LINK owns the block and access originated from SROOTLINK area)
0 => Access and owner from different zone (Additionally if SROOT LINK owns the block, but access originated from a non SROOT LINK area)
These bits are only valid when OWNER = 10 (App owned)

Reset type: ERAD_RESET

15-13RESERVEDR0hReserved
12SROOTR0h0 => This block is not owned by SROOT LINK
1 => This block is owned by SROOT LINK

Reset type: ERAD_RESET

11-8ZONER0h0000 => Zone-0
0001 => Zone-1
0010 => Zone-2
0011 => Zone-3
All others => Reserved
These bits are only valid when OWNER = 10 (App owned)

Reset type: ERAD_RESET

7-2RESERVEDR0hReserved
1-0OWNERR/W0h00 => No Owner
01 => Debug Owned
10 => App Owned
11 => Reserved
Debugger :
Read-> Returns current ownership ID
Writes -> Allowed only if current value is 00 or 01
Application:
Read-> Returns current ownership ID
Writes -> Allowed only if current value is 00 or 10
NOTE : When a 00 gets successfully written, all the rest of control/status registers gets reset/cleared

Reset type: ERAD_RESET

8.1.1.30 PCTRACE_GLOBAL Register (Offset = 844h) [Reset = 00000000h]

PCTRACE_GLOBAL is shown in Figure 17-38 and described in Table 17-37.

Return to the Summary Table.

Global Control Register

Figure 17-38 PCTRACE_GLOBAL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDBUFFER_SIZE
R-0hR-0h
15141312111098
RESERVEDINIT
R-0hW1C-0h
76543210
RESERVEDEN
R-0hR/W-0h
Table 17-37 PCTRACE_GLOBAL Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17-16BUFFER_SIZER0hTrace buffer size
00 = 1 Kbyte
01 = 2 kbyte
10 = 3 kbyte
11 = 4 kbyte

Reset type: ERAD_RESET

15-9RESERVEDR0hReserved
8INITW1C0h0 = No action
1 = Trace module is initialized for a fresh trace start with buffer pointer(PTR) reset and BUFFER_FULL flags cleared along with PC_SOFTENABLE and PC_SOFTDISABLE
Reads of this bit position always returns zero

Reset type: ERAD_RESET

7-1RESERVEDR0hReserved
0ENR/W0h0 = PC Trace Disabled
1 = PC Trace Enabled

Reset type: ERAD_RESET

8.1.1.31 PCTRACE_BUFFER Register (Offset = 848h) [Reset = 00000000h]

PCTRACE_BUFFER is shown in Figure 17-39 and described in Table 17-38.

Return to the Summary Table.

Trace Buffer pointer register

Figure 17-39 PCTRACE_BUFFER Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDBUFFER_FULL
R-0hR-0h
15141312111098
PTR
R-0h
76543210
PTR
R-0h
Table 17-38 PCTRACE_BUFFER Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16BUFFER_FULLR0h0 = Trace Buffer Never became full/Overflowed after init
1 = Indicates Trace Buffer became full/Overflowed
This bit also gets cleared when INIT is performed via PCTRACE_GLOBAL.INIT

Reset type: ERAD_RESET

15-0PTRR0hCurrent Pointer to the Trace Buffer.
If PTR=0 => there is no trace data in buffer (when BUFFER_FULL=0)
If PTR=2,4,6. there is fresh trace data in buffer
Buffer pointer gets incremented by 2 for every new trace storage, since two 32-bit values get stored for every discontinuity.
For ex : 2 => Locations 0,1 of trace buffer have valid data (SRC,DST)
4 => Locations 0,1,2,3 have valid data (SRC,DST,SRC,DST)
and so on
Thhese bits also gets cleared when INIT is performed via PCTRACE_GLOBAL.INIT

Reset type: ERAD_RESET

8.1.1.32 PCTRACE_QUAL1 Register (Offset = 84Ch) [Reset = 00000000h]

PCTRACE_QUAL1 is shown in Figure 17-40 and described in Table 17-39.

Return to the Summary Table.

Trace Qualifier register 1

Figure 17-40 PCTRACE_QUAL1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDSTOP_INP_INVRESERVEDSTART_INP_INVRESERVEDWINDOWED_INP_INVTRACE_MODE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
WINDOWED_INP_SEL
R/W-0h
Table 17-39 PCTRACE_QUAL1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23RESERVEDR/W0hReserved
22STOP_INP_INVR/W0hInvert the Selected Stop input

Reset type: ERAD_RESET

21RESERVEDR/W0hReserved
20START_INP_INVR/W0hInvert the Selected Start input

Reset type: ERAD_RESET

19RESERVEDR/W0hReserved
18WINDOWED_INP_INVR/W0hInvert the Selected trace input

Reset type: ERAD_RESET

17-16TRACE_MODER/W0h0x = Trace without any hardware qualifiers
10 = Trace using Windowed mode
11 = Trace using Start/Stop mode
These two bits are valid only when PCTRACE_GLOBAL.EN is set to '1'

Reset type: ERAD_RESET

15-8RESERVEDR0hReserved
7-0WINDOWED_INP_SELR/W0hThese bits decide which of the inputs will be selected to enable tracing.These inputs will be hooked up to the event outputs from the bus comparator module, counter module and other system events. The usage of these bits are relevant only in the Windowed mode of trace module. Pls refer to the device spec for complete list of signals

Reset type: ERAD_RESET

8.1.1.33 PCTRACE_QUAL2 Register (Offset = 850h) [Reset = 00000000h]

PCTRACE_QUAL2 is shown in Figure 17-41 and described in Table 17-40.

Return to the Summary Table.

Trace Qualifier register 2

Figure 17-41 PCTRACE_QUAL2 Register
31302928272625242322212019181716
RESERVEDSTOP_INP_SEL
R-0hR/W-0h
1514131211109876543210
RESERVEDSTART_INP_SEL
R-0hR/W-0h
Table 17-40 PCTRACE_QUAL2 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16STOP_INP_SELR/W0hThese bits decide which of the inputs will be selected as the STOP event for trace. These inputs will be hooked up to the event outputs from the bus comparator module, counter module and other system events. The usage of these bits are relevant only in the Start/Stop mode of trace module. Pls refer to the device spec for complete list of signals

Reset type: ERAD_RESET

15-8RESERVEDR0hReserved
7-0START_INP_SELR/W0hThese bits decide which of the inputs will be selected as the START event for trace. These inputs will be hooked up to the event outputs from the bus comparator module, counter module and other system events. The usage of these bits are relevant only in the Start/Stop mode of trace module. Pls refer to the device spec for complete list of signals

Reset type: ERAD_RESET

8.1.1.34 PCTRACE_LOGPC_SOFTENABLE Register (Offset = 854h) [Reset = 00000000h]

PCTRACE_LOGPC_SOFTENABLE is shown in Figure 17-42 and described in Table 17-41.

Return to the Summary Table.

PC when PC Trace was last enabled by software

Figure 17-42 PCTRACE_LOGPC_SOFTENABLE Register
313029282726252423222120191817161514131211109876543210
PC_SOFTENABLE
R-0h
Table 17-41 PCTRACE_LOGPC_SOFTENABLE Register Field Descriptions
BitFieldTypeResetDescription
31-0PC_SOFTENABLER0hThese bits reflect the value of PC when trace module enable bit was last written with '1' (PCTRACE_GLOBAL.EN).These registers are primarily used by ccs drivers while displaying the trace to give a logical start from where tracing was enabled. This register also gets cleared when INIT is performed via PCTRACE_GLOBAL.INIT

Reset type: ERAD_RESET

8.1.1.35 PCTRACE_LOGPC_SOFTDISABLE Register (Offset = 858h) [Reset = 00000000h]

PCTRACE_LOGPC_SOFTDISABLE is shown in Figure 17-43 and described in Table 17-42.

Return to the Summary Table.

PC when PC Trace was last disabled by software

Figure 17-43 PCTRACE_LOGPC_SOFTDISABLE Register
313029282726252423222120191817161514131211109876543210
PC_SOFTDISABLE
R-0h
Table 17-42 PCTRACE_LOGPC_SOFTDISABLE Register Field Descriptions
BitFieldTypeResetDescription
31-0PC_SOFTDISABLER0hThese bits reflect the value of PC when trace module enable bit was last written with '0' (PCTRACE_GLOBAL.EN).These registers are primarily used by ccs drivers while displaying the trace to give a logical end to where tracing block was disabled. This register also gets cleared when INIT is performed via PCTRACE_GLOBAL.INIT

Reset type: ERAD_RESET

8.1.1.36 PCTRACE_BUFFER_BASE_y Register (Offset = 1000h + formula) [Reset = 00000000h]

PCTRACE_BUFFER_BASE_y is shown in Figure 17-44 and described in Table 17-43.

Return to the Summary Table.

Trace Buffer Base address

Offset = 1000h + (y * 4h); where y = 0h to FFh

Figure 17-44 PCTRACE_BUFFER_BASE_y Register
3130292827262524
PROGRAM_COUNTER
R-0h
2322212019181716
PROGRAM_COUNTER
R-0h
15141312111098
PROGRAM_COUNTER
R-0h
76543210
PROGRAM_COUNTERBLOCKED
R-0hR-0h
Table 17-43 PCTRACE_BUFFER_BASE_y Register Field Descriptions
BitFieldTypeResetDescription
31-1PROGRAM_COUNTERR0hProgram Counter[31:1] value where discontinuity occurred
Note: PC values are aligned for min 16-bit instruction size so bit 0 of program counter is always 0. 32 bit PC value will be {PCTRACE_BUFFER_BASE.PROGRAM_COUNTER,1'b0}

Reset type: ERAD_RESET

0BLOCKEDR0h1 = PROGRAM_COUNTER[31:1] is not valid due to security permissions
0 = PROGRAM_COUNTER[31:1] is valid

Reset type: ERAD_RESET