SPRUJ79 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 â–º C29x SYSTEM RESOURCES
    1.     Technical Reference Manual Overview
  4. 2 F29x Processor
    1. 2.1 CPU Architecture
      1. 2.1.1 C29x Related Collateral
    2. 2.2 Lock and Commit Registers
    3. 2.3 C29x CPU Registers
      1. 2.3.1 C29CPU Base Address Table
      2. 2.3.2 C29_RTINT_STACK Registers
      3. 2.3.3 C29_SECCALL_STACK Registers
      4. 2.3.4 C29_SECURE_REGS Registers
      5. 2.3.5 C29_DIAG_REGS Registers
      6. 2.3.6 C29_SELFTEST_REGS Registers
  5. 3 System Control and Interrupts
    1. 3.1  C29x System Control Introduction
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
      2. 3.2.2 Device Configuration Registers
    3. 3.3  Resets
      1. 3.3.1 Reset Sources
      2. 3.3.2 External Reset (XRS)
      3. 3.3.3 Simulate External Reset
      4. 3.3.4 Power-On Reset (POR)
      5. 3.3.5 Debugger Reset (SYSRS)
      6. 3.3.6 Watchdog Reset (WDRS)
      7. 3.3.7 ESM NMI Watchdog Reset (NMIWDRS)
      8. 3.3.8 EtherCAT Slave Controller (ESC) Module Reset Output
    4. 3.4  Safety Features
      1. 3.4.1 Write Protection on Registers
        1. 3.4.1.1 LOCK Protection on System Configuration Registers
        2. 3.4.1.2 EALLOW Protection
      2. 3.4.2 PIPE Vector Address Validity Check
      3. 3.4.3 NMIWDs
      4. 3.4.4 System Control Registers Parity Protection
      5. 3.4.5 ECC Enabled RAMs, Shared RAMs Protection
      6. 3.4.6 ECC Enabled Flash Memory
      7. 3.4.7 ERRORSTS Pin
    5. 3.5  Clocking
      1. 3.5.1 Clock Sources
        1. 3.5.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.5.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.5.1.3 External Oscillator (XTAL)
        4. 3.5.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.5.2 Derived Clocks
        1. 3.5.2.1 Oscillator Clock (OSCCLK)
        2. 3.5.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.5.3 Device Clock Domains
        1. 3.5.3.1 System Clock (PLLSYSCLK)
        2. 3.5.3.2 CPU Clock (CPUCLK)
        3. 3.5.3.3 Peripheral Clock (PERx.SYSCLK)
        4. 3.5.3.4 MCAN Bit Clock
        5. 3.5.3.5 CPU Timer2 Clock (TIMER2CLK)
      4. 3.5.4 External Clock Output (XCLKOUT)
      5. 3.5.5 Clock Connectivity
      6. 3.5.6 Using an External Crystal or Resonator
        1. 3.5.6.1 X1/X2 Precondition Circuit
      7. 3.5.7 PLL
        1. 3.5.7.1 System Clock Setup
        2. 3.5.7.2 SYS PLL Bypass
      8. 3.5.8 Clock (OSCCLK) Failure Detection
        1. 3.5.8.1 Missing Clock Detection Logic
        2. 3.5.8.2 Dual Clock Comparator (DCC)
    6. 3.6  Bus Architecture
      1. 3.6.1 Safe Interconnect
        1. 3.6.1.1 Safe Interconnect for Read Operation
        2. 3.6.1.2 Safe Interconnect for Write Operation
      2. 3.6.2 Peripheral Access Configuration using FRAMESEL
      3. 3.6.3 Bus Arbitration
    7. 3.7  32-Bit CPU Timers 0/1/2
    8. 3.8  Watchdog Timers
      1. 3.8.1 Servicing the Watchdog Timer
      2. 3.8.2 Minimum Window Check
      3. 3.8.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.8.4 Watchdog Operation in Low-Power Modes
      5. 3.8.5 Emulation Considerations
    9. 3.9  Low-Power Modes
      1. 3.9.1 IDLE
      2. 3.9.2 STANDBY
    10. 3.10 Memory Subsystem (MEMSS)
      1. 3.10.1 Introduction
      2. 3.10.2 Features
      3. 3.10.3 Configuration Bits
        1. 3.10.3.1 Memory Initialization
      4. 3.10.4 RAM
        1. 3.10.4.1  MEMSS Architecture
        2. 3.10.4.2  RAM Memory Controller Overview
        3. 3.10.4.3  Memory Controllers
          1. 3.10.4.3.1 128-Bit LPx and CPx Memory Controller
          2. 3.10.4.3.2 64-Bit LDx and CDx Memory Controller
          3. 3.10.4.3.3 M0 Memory Controller
        4. 3.10.4.4  RTDMA Burst Support
        5. 3.10.4.5  Atomic Memory Operations
        6. 3.10.4.6  RAM ECC
        7. 3.10.4.7  Read-Modify-Write Operations
        8. 3.10.4.8  Dataline Buffer
        9. 3.10.4.9  HSM Sync Bridge
        10. 3.10.4.10 Access Bridges
          1. 3.10.4.10.1 Debug Access Bridge
          2. 3.10.4.10.2 Global Access Bridge
          3. 3.10.4.10.3 Program Access Bridge
      5. 3.10.5 ROM
        1. 3.10.5.1 ROM Dataline Buffer
        2. 3.10.5.2 ROM Prefetch
      6. 3.10.6 Arbitration
      7. 3.10.7 Test Modes
      8. 3.10.8 Emulation Mode
    11. 3.11 System Control Register Configuration Restrictions
    12. 3.12 Software
      1. 3.12.1  SYSCTL Registers to Driverlib Functions
      2. 3.12.2  MEMSS Registers to Driverlib Functions
      3. 3.12.3  CPU Registers to Driverlib Functions
      4. 3.12.4  WD Registers to Driverlib Functions
      5. 3.12.5  CPUTIMER Registers to Driverlib Functions
      6. 3.12.6  XINT Registers to Driverlib Functions
      7. 3.12.7  LPOST Registers to Driverlib Functions
      8. 3.12.8  SYSCTL Examples
        1. 3.12.8.1 Missing clock detection (MCD) - SINGLE_CORE
        2. 3.12.8.2 XCLKOUT (External Clock Output) Configuration - SINGLE_CORE
      9. 3.12.9  TIMER Examples
        1. 3.12.9.1 Timer Academy Lab - SINGLE_CORE
        2. 3.12.9.2 CPU Timers - SINGLE_CORE
        3. 3.12.9.3 CPU Timers - SINGLE_CORE
      10. 3.12.10 WATCHDOG Examples
        1. 3.12.10.1 Watchdog - SINGLE_CORE
      11. 3.12.11 LPM Examples
        1. 3.12.11.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO - SINGLE_CORE
        2. 3.12.11.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog - SINGLE_CORE
        3. 3.12.11.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO - SINGLE_CORE
        4. 3.12.11.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog - SINGLE_CORE
    13. 3.13 SYSCTRL Registers
      1. 3.13.1  SYSCTRL Base Address Table
      2. 3.13.2  DEV_CFG_REGS Registers
      3. 3.13.3  MEMSS_L_CONFIG_REGS Registers
      4. 3.13.4  MEMSS_C_CONFIG_REGS Registers
      5. 3.13.5  MEMSS_M_CONFIG_REGS Registers
      6. 3.13.6  MEMSS_MISCI_REGS Registers
      7. 3.13.7  CPU_SYS_REGS Registers
      8. 3.13.8  CPU_PER_CFG_REGS Registers
      9. 3.13.9  WD_REGS Registers
      10. 3.13.10 CPUTIMER_REGS Registers
      11. 3.13.11 XINT_REGS Registers
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Device Boot Flow
      2. 4.5.2 CPU1 Boot Flow
      3. 4.5.3 Emulation Boot Flow
      4. 4.5.4 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 MPOST and LPOST Configurations
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Memory Maps
        1. 4.7.4.1 Boot ROM Memory-Maps
        2. 4.7.4.2 Reserved RAM Memory-Maps
      5. 4.7.5  ROM Structure and Status Information
      6. 4.7.6  Boot Modes and Loaders
        1. 4.7.6.1 Boot Modes
          1. 4.7.6.1.1 Flash Boot
          2. 4.7.6.1.2 RAM Boot
          3. 4.7.6.1.3 Wait Boot
        2. 4.7.6.2 Bootloaders
          1. 4.7.6.2.1 SPI Boot Mode
          2. 4.7.6.2.2 I2C Boot Mode
          3. 4.7.6.2.3 Parallel Boot Mode
          4. 4.7.6.2.4 CAN Boot Mode
          5. 4.7.6.2.5 CAN-FD Boot Mode
          6. 4.7.6.2.6 UART Boot Mode
      7. 4.7.7  GPIO Assignments
      8. 4.7.8  HSM and C29 ROM Task Ownership and Interactions
        1. 4.7.8.1 Application Authentication by HSM
      9. 4.7.9  Boot Status Information
        1. 4.7.9.1 Booting Status
      10. 4.7.10 BootROM Timing
    8. 4.8 Software
      1. 4.8.1 BOOT Examples
  7. 5 Lockstep Compare Module (LCM)
    1. 5.1 Introduction
      1. 5.1.1 Features
      2. 5.1.2 Block Diagram
      3. 5.1.3 Lockstep Compare Modules
    2. 5.2 Enabling LCM Comparators
    3. 5.3 LCM Redundant Module Configuration
    4. 5.4 LCM Error Handling
    5. 5.5 Debug Mode with LCM
    6. 5.6 Register Parity Error Protection
    7. 5.7 Functional Logic
      1. 5.7.1 Comparator Logic
      2. 5.7.2 Self-Test Logic
        1. 5.7.2.1 Match Test Mode
        2. 5.7.2.2 Mismatch Test Mode
      3. 5.7.3 Error Injection Tests
        1. 5.7.3.1 Comparator Error Force Test
        2. 5.7.3.2 Register Parity Error Test
    8. 5.8 Software
      1. 5.8.1 LCM Registers to Driverlib Functions
    9. 5.9 LCM Registers
      1. 5.9.1 LCM Base Address Table
      2. 5.9.2 LCM_REGS Registers
  8. 6 Peripheral Interrupt Priority and Expansion (PIPE)
    1. 6.1 Introduction
      1. 6.1.1 Features
      2. 6.1.2 Interrupt Concepts
      3. 6.1.3 PIPE Related Collateral
    2. 6.2 Interrupt Architecture
      1. 6.2.1 Dynamic Priority Arbitration Block
      2. 6.2.2 Post Processing Block
      3. 6.2.3 Memory-Mapped Registers
    3. 6.3 Interrupt Propagation
    4. 6.4 Configuring Interrupts
      1. 6.4.1 Enabling and Disabling Interrupts
      2. 6.4.2 Prioritization
        1. 6.4.2.1 User-Configured Interrupt Priority
        2. 6.4.2.2 Index-Based Fixed Interrupt Priority
      3. 6.4.3 Nesting and Priority Grouping
      4. 6.4.4 Stack Protection
      5. 6.4.5 Context
    5. 6.5 Safety and Security
      1. 6.5.1 Access Control
      2. 6.5.2 PIPE Errors
      3. 6.5.3 Register Data Integrity and Safety
      4. 6.5.4 Self-Test and Diagnostics
    6. 6.6 Software
      1. 6.6.1 PIPE Registers to Driverlib Functions
      2. 6.6.2 INTERRUPT Examples
        1. 6.6.2.1 RTINT vs INT Latency example - SINGLE_CORE
        2. 6.6.2.2 INT and RTINT Nesting Example - SINGLE_CORE
    7. 6.7 PIPE Registers
      1. 6.7.1 PIPE Base Address Table
      2. 6.7.2 PIPE_REGS Registers
  9. 7  Error Signaling Module (ESM_C29)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 ESM Related Collateral
    2. 7.2 ESM Subsystem
      1. 7.2.1 System ESM
        1. 7.2.1.1 Error Pin Monitor Event
      2. 7.2.2 Safety Aggregator
        1. 7.2.2.1 EDC Controller Interface Description
          1. 7.2.2.1.1 EDC_REGS Registers
        2. 7.2.2.2 Read Operation on EDC Controller
        3. 7.2.2.3 Write Operation on EDC Controller
        4. 7.2.2.4 Safety Aggregator Error Injection
      3. 7.2.3 ESM Subsystem Integration View
    3. 7.3 ESM Functional Description
      1. 7.3.1 Error Event Inputs
      2. 7.3.2 Error Interrupt Outputs
        1. 7.3.2.1 High Priority Watchdog
        2. 7.3.2.2 Critical Priority Interrupt Output
      3. 7.3.3 Error Pin Output (ERR_O/ERRORSTS)
        1. 7.3.3.1 Minimum Time Interval
        2. 7.3.3.2 PWM Mode
      4. 7.3.4 Reset Type Information for ESM Registers
      5. 7.3.5 Clock Stop
      6. 7.3.6 Commit/Lock for MMRs
      7. 7.3.7 Safety Protection for MMRs
      8. 7.3.8 Register Configuration Tieoffs
        1. 7.3.8.1 Group0 High Priority Tieoff
        2. 7.3.8.2 High Priority Watchdog Enable Tieoff
    4. 7.4 ESM Configuration Guide
    5. 7.5 Interrupt Condition Control and Handling
      1. 7.5.1 ESM Low Priority Error Interrupt
      2. 7.5.2 ESM High Priority Error Interrupt
      3. 7.5.3 Critical Priority Error Interrupt
      4. 7.5.4 High Priority Watchdog Interrupt
      5. 7.5.5 Safety Aggregator Interrupt Control and Handling
    6. 7.6 Software
      1. 7.6.1 ESM_CPU Registers to Driverlib Functions
      2. 7.6.2 ESM_SYS Registers to Driverlib Functions
      3. 7.6.3 ESM_SAFETY_AGGREGATOR Registers to Driverlib Functions
      4. 7.6.4 ESM Examples
        1. 7.6.4.1 ESM Multicore Example (CPU1,CPU3) - MULTI_CORE
        2. 7.6.4.2 ESM Multicore Example (CPU1,CPU3) - MULTI_CORE
        3. 7.6.4.3 ESM - SINGLE_CORE
        4. 7.6.4.4 ESM - SINGLE_CORE
    7. 7.7 ESM Registers
      1. 7.7.1 ESM Base Address Table
      2. 7.7.2 ESM_CPU_REGS Registers
      3. 7.7.3 ESM_SYSTEM_REGS Registers
      4. 7.7.4 ESM_SAFETYAGG_REGS Registers
  10. 8  Error Aggregator
    1. 8.1 Introduction
    2. 8.2 Error Aggregator Modules
    3. 8.3 Error Propagation Path from Source to CPU
    4. 8.4 Error Aggregator Interface
      1. 8.4.1 Functional Description
    5. 8.5 Error Condition Handling User Guide
    6. 8.6 Error Type Information
    7. 8.7 Error Sources Information
    8. 8.8 Software
      1. 8.8.1 ERROR_AGGREGATOR Registers to Driverlib Functions
    9. 8.9 ERRORAGGREGATOR Registers
      1. 8.9.1 ERRORAGGREGATOR Base Address Table
      2. 8.9.2 HSM_ERROR_AGGREGATOR_CONFIG_REGS Registers
      3. 8.9.3 ERROR_AGGREGATOR_CONFIG_REGS Registers
  11. 9 Flash Module
    1. 9.1 Introduction to Flash Memory
      1. 9.1.1 FLASH Related Collateral
      2. 9.1.2 Features
      3. 9.1.3 Flash Tools
      4. 9.1.4 Block Diagram
    2. 9.2 Flash Subsystem Overview
    3. 9.3 Flash Banks and Pumps
    4. 9.4 Flash Read Interfaces
      1. 9.4.1 Bank Modes and Swapping
      2. 9.4.2 Flash Wait States
      3. 9.4.3 Buffer and Cache Mechanisms
        1. 9.4.3.1 Prefetch Mechanism and Block Cache
        2. 9.4.3.2 Data Line Buffer
        3. 9.4.3.3 Sequential Data Pre-read Mode
      4. 9.4.4 Flash Read Arbitration
      5. 9.4.5 Error Correction Code (ECC) Protection
      6. 9.4.6 Procedure to Change Flash Read Interface Registers
    5. 9.5 Flash Erase and Program
      1. 9.5.1 Flash Semaphore and Update Protection
      2. 9.5.2 Erase
      3. 9.5.3 Program
    6. 9.6 Migrating an Application from RAM to Flash
    7. 9.7 Flash Registers
      1. 9.7.1 FLASH Base Address Table
      2. 9.7.2 FLASH_CMD_REGS_FLC1 Registers
      3. 9.7.3 FLASH_CMD_REGS_FLC2 Registers
      4. 9.7.4 FRI_CTRL_REGS Registers
  12. 10Safety and Security Unit (SSU)
    1. 10.1  Introduction
      1. 10.1.1 SSU Related Collateral
      2. 10.1.2 Block Diagram
      3. 10.1.3 System SSU Configuration Example
    2. 10.2  Access Protection Ranges
      1. 10.2.1 Access Protection Inheritance
    3. 10.3  LINKs
    4. 10.4  STACKs
    5. 10.5  ZONEs
    6. 10.6  SSU-CPU Interface
      1. 10.6.1 SSU Operation in Lockstep Mode
    7. 10.7  SSU Operation Modes
    8. 10.8  Security Configuration and Flash Management
      1. 10.8.1 BANKMGMT Sectors
      2. 10.8.2 SECCFG Sectors
      3. 10.8.3 SECCFG Sector Address Mapping
      4. 10.8.4 SECCFG Sector Memory Map
      5. 10.8.5 SECCFG CRC
    9. 10.9  Flash Write/Erase Access Control
      1. 10.9.1 Permanent Flash Lock (Write/Erase Protection)
      2. 10.9.2 Updating Flash MAIN Sectors
      3. 10.9.3 Firmware-Over-The-Air Updates (FOTA)
      4. 10.9.4 Updating Flash SECCFG Sectors
      5. 10.9.5 Reading Flash SECCFG Sectors
    10. 10.10 RAMOPEN Feature
    11. 10.11 Debug Authorization
      1. 10.11.1 Global CPU Debug Enable
      2. 10.11.2 ZONE Debug
      3. 10.11.3 Authentication for Debug Access
        1. 10.11.3.1 Password-based Authentication
        2. 10.11.3.2 CPU-based Authentication
    12. 10.12 Hardcoded Protections
    13. 10.13 SSU Register Access Permissions
      1. 10.13.1 Permissions for SSU General Control Registers
      2. 10.13.2 Permissions for SSU CPU1 Configuration Registers
      3. 10.13.3 Permissions for SSU CPU2+ Configuration Registers
      4. 10.13.4 Permissions for CPU1 Access Protection Registers
      5. 10.13.5 Permissions for CPU2+ Access Protection Registers
    14. 10.14 SSU Fault Signals
    15. 10.15 Software
      1. 10.15.1 SSU Registers to Driverlib Functions
    16. 10.16 SSU Registers
      1. 10.16.1 SSU Base Address Table
      2. 10.16.2 SSU_GEN_REGS Registers
      3. 10.16.3 SSU_CPU1_CFG_REGS Registers
      4. 10.16.4 SSU_CPU2_CFG_REGS Registers
      5. 10.16.5 SSU_CPU3_CFG_REGS Registers
      6. 10.16.6 SSU_CPU1_AP_REGS Registers
      7. 10.16.7 SSU_CPU2_AP_REGS Registers
      8. 10.16.8 SSU_CPU3_AP_REGS Registers
  13. 11Configurable Logic Block (CLB)
    1. 11.1  Introduction
      1. 11.1.1 CLB Related Collateral
    2. 11.2  Description
      1. 11.2.1 CLB Clock
    3. 11.3  CLB Input/Output Connection
      1. 11.3.1 Overview
      2. 11.3.2 CLB Input Selection
      3. 11.3.3 CLB Output Selection
      4. 11.3.4 CLB Output Signal Multiplexer
    4. 11.4  CLB Tile
      1. 11.4.1 Static Switch Block
      2. 11.4.2 Counter Block
        1. 11.4.2.1 Counter Description
        2. 11.4.2.2 Counter Operation
        3. 11.4.2.3 Serializer Mode
        4. 11.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 11.4.3 FSM Block
      4. 11.4.4 LUT4 Block
      5. 11.4.5 Output LUT Block
      6. 11.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 11.4.7 High Level Controller (HLC)
        1. 11.4.7.1 High Level Controller Events
        2. 11.4.7.2 High Level Controller Instructions
        3. 11.4.7.3 <Src> and <Dest>
        4. 11.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 11.5  CPU Interface
      1. 11.5.1 Register Description
      2. 11.5.2 Non-Memory Mapped Registers
    6. 11.6  RTDMA Access
    7. 11.7  CLB Data Export Through SPI RX Buffer
    8. 11.8  CLB Pipeline Mode
    9. 11.9  Software
      1. 11.9.1 CLB Registers to Driverlib Functions
      2. 11.9.2 CLB Examples
    10. 11.10 CLB Registers
      1. 11.10.1 CLB Base Address Table
      2. 11.10.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 11.10.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 11.10.4 CLB_DATA_EXCHANGE_REGS Registers
  14. 12Dual-Clock Comparator (DCC)
    1. 12.1 Introduction
      1. 12.1.1 Features
      2. 12.1.2 Block Diagram
    2. 12.2 Module Operation
      1. 12.2.1 Configuring DCC Counters
      2. 12.2.2 Single-Shot Measurement Mode
      3. 12.2.3 Continuous Monitoring Mode
      4. 12.2.4 Error Conditions
    3. 12.3 Interrupts
    4. 12.4 Software
      1. 12.4.1 DCC Registers to Driverlib Functions
      2. 12.4.2 DCC Examples
        1. 12.4.2.1 DCC Single shot Clock verification - SINGLE_CORE
        2. 12.4.2.2 DCC Single shot Clock measurement - SINGLE_CORE
        3. 12.4.2.3 DCC Continuous clock monitoring - SINGLE_CORE
    5. 12.5 DCC Registers
      1. 12.5.1 DCC Base Address Table
      2. 12.5.2 DCC_REGS Registers
  15. 13Real-Time Direct Memory Access (RTDMA)
    1. 13.1  Introduction
      1. 13.1.1 Features
      2. 13.1.2 RTDMA Related Collateral
      3. 13.1.3 Block Diagram
    2. 13.2  RTDMA Trigger Source Options
    3. 13.3  RTDMA Bus
    4. 13.4  Address Pointer and Transfer Control
    5. 13.5  Pipeline Timing and Throughput
    6. 13.6  Channel Priority
      1. 13.6.1 Round-Robin Mode
      2. 13.6.2 Software Configurable Priority of Channels
    7. 13.7  Overrun Detection Feature
    8. 13.8  Burst Mode
    9. 13.9  Safety and Security
      1. 13.9.1 Safety
        1. 13.9.1.1 Lockstep Mode
        2. 13.9.1.2 Memory Protection Unit (MPU)
          1. 13.9.1.2.1 MPU Errors
      2. 13.9.2 Security
      3. 13.9.3 RTDMA Errors
      4. 13.9.4 Self-Test and Diagnostics
    10. 13.10 Software
      1. 13.10.1 RTDMA Registers to Driverlib Functions
      2. 13.10.2 RTDMA Examples
        1. 13.10.2.1 RTDMA Academy Lab - SINGLE_CORE
        2. 13.10.2.2 RTDMA Transfer - SINGLE_CORE
        3. 13.10.2.3 RTDMA Transfer with MPU - SINGLE_CORE
    11. 13.11 RTDMA Registers
      1. 13.11.1 RTDMA Base Address Table
      2. 13.11.2 RTDMA_REGS Registers
      3. 13.11.3 RTDMA_DIAG_REGS Registers
      4. 13.11.4 RTDMA_SELFTEST_REGS Registers
      5. 13.11.5 RTDMA_MPU_REGS Registers
      6. 13.11.6 RTDMA_CH_REGS Registers
  16. 14External Memory Interface (EMIF)
    1. 14.1 Introduction
      1. 14.1.1 Purpose of the Peripheral
      2. 14.1.2 Features
        1. 14.1.2.1 Asynchronous Memory Support
        2. 14.1.2.2 Synchronous DRAM Memory Support
      3. 14.1.3 Functional Block Diagram
      4. 14.1.4 Configuring Device Pins
    2. 14.2 EMIF Module Architecture
      1. 14.2.1  EMIF Clock Control
      2. 14.2.2  EMIF Requests
      3. 14.2.3  EMIF Signal Descriptions
      4. 14.2.4  EMIF Signal Multiplexing Control
      5. 14.2.5  SDRAM Controller and Interface
        1. 14.2.5.1  SDRAM Commands
        2. 14.2.5.2  Interfacing to SDRAM
        3. 14.2.5.3  SDRAM Configuration Registers
        4. 14.2.5.4  SDRAM Auto-Initialization Sequence
        5. 14.2.5.5  SDRAM Configuration Procedure
        6. 14.2.5.6  EMIF Refresh Controller
          1. 14.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 14.2.5.7  Self-Refresh Mode
        8. 14.2.5.8  Power-Down Mode
        9. 14.2.5.9  SDRAM Read Operation
        10. 14.2.5.10 SDRAM Write Operations
        11. 14.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 14.2.6  Asynchronous Controller and Interface
        1. 14.2.6.1 Interfacing to Asynchronous Memory
        2. 14.2.6.2 Accessing Larger Asynchronous Memories
        3. 14.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 14.2.6.4 Read and Write Operations in Normal Mode
          1. 14.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 14.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 14.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 14.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 14.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 14.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 14.2.7  Data Bus Parking
      8. 14.2.8  Reset and Initialization Considerations
      9. 14.2.9  Interrupt Support
        1. 14.2.9.1 Interrupt Events
      10. 14.2.10 RTDMA Event Support
      11. 14.2.11 EMIF Signal Multiplexing
      12. 14.2.12 Memory Map
      13. 14.2.13 Priority and Arbitration
      14. 14.2.14 System Considerations
        1. 14.2.14.1 Asynchronous Request Times
      15. 14.2.15 Power Management
        1. 14.2.15.1 Power Management Using Self-Refresh Mode
        2. 14.2.15.2 Power Management Using Power Down Mode
      16. 14.2.16 Emulation Considerations
    3. 14.3 EMIF Subsystem (EMIFSS)
      1. 14.3.1 Burst Support
      2. 14.3.2 EMIFSS Performance Improvement
      3. 14.3.3 Buffer Module
        1. 14.3.3.1 CPU Write FIFO
      4. 14.3.4 Emulation Mode
    4. 14.4 Example Configuration
      1. 14.4.1 Hardware Interface
      2. 14.4.2 Software Configuration
        1. 14.4.2.1 Configuring the SDRAM Interface
          1. 14.4.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 14.4.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 14.4.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 14.4.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 14.4.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 14.4.2.2 Configuring the Flash Interface
          1. 14.4.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    5. 14.5 Software
      1. 14.5.1 EMIF Registers to Driverlib Functions
      2. 14.5.2 EMIF Examples
    6. 14.6 EMIF Registers
      1. 14.6.1 EMIF Base Address Table
      2. 14.6.2 EMIF_REGS Registers
  17. 15General-Purpose Input/Output (GPIO)
    1. 15.1  Introduction
      1. 15.1.1 GPIO Related Collateral
    2. 15.2  Configuration Overview
    3. 15.3  Digital Inputs on ADC Pins (AIOs)
    4. 15.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 15.5  Digital General-Purpose I/O Control
    6. 15.6  Input Qualification
      1. 15.6.1 No Synchronization (Asynchronous Input)
      2. 15.6.2 Synchronization to SYSCLKOUT Only
      3. 15.6.3 Qualification Using a Sampling Window
    7. 15.7  PMBUS and I2C Signals
    8. 15.8  GPIO and Peripheral Muxing
      1. 15.8.1 GPIO Muxing
      2. 15.8.2 Peripheral Muxing
    9. 15.9  Internal Pullup Configuration Requirements
    10. 15.10 Software
      1. 15.10.1 GPIO Registers to Driverlib Functions
      2. 15.10.2 GPIO Examples
        1. 15.10.2.1 Device GPIO Toggle - SINGLE_CORE
        2. 15.10.2.2 XINT/XBAR example - SINGLE_CORE
      3. 15.10.3 LED Examples
        1. 15.10.3.1 LED Blinky Example - MULTI_CORE
        2. 15.10.3.2 LED Blinky Example (CPU1,CPU3) - MULTI_CORE
        3. 15.10.3.3 LED Blinky example - SINGLE_CORE
        4. 15.10.3.4 LED Blinky Example (CPU1|CPU2|CPU3) - MULTI_CORE
        5. 15.10.3.5 LED Blinky Example (CPU2) - MULTI_CORE
        6. 15.10.3.6 LED Blinky Example (CPU3) - MULTI_CORE
    11. 15.11 GPIO Registers
      1. 15.11.1 GPIO Base Address Table
      2. 15.11.2 GPIO_CTRL_REGS Registers
      3. 15.11.3 GPIO_DATA_REGS Registers
      4. 15.11.4 GPIO_DATA_READ_REGS Registers
  18. 16Interprocessor Communication (IPC)
    1. 16.1 Introduction
    2. 16.2 IPC Flags and Interrupts
    3. 16.3 IPC Command Registers
    4. 16.4 Free-Running Counter
    5. 16.5 IPC Communication Protocol
    6. 16.6 Software
      1. 16.6.1 IPC Registers to Driverlib Functions
      2. 16.6.2 IPC Examples
        1. 16.6.2.1 IPC basic message passing example with interrupt - MULTI_CORE
        2. 16.6.2.2 IPC basic message passing example with interrupt - MULTI_CORE
        3. 16.6.2.3 IPC basic message passing example with interrupt - MULTI_CORE
        4. 16.6.2.4 IPC basic message passing example with interrupt - MULTI_CORE
    7. 16.7 IPC Registers
      1. 16.7.1 IPC Base Address Table
      2. 16.7.2 IPC_COUNTER_REGS Registers
      3. 16.7.3 CPU1_IPC_SEND_REGS Registers
      4. 16.7.4 CPU2_IPC_SEND_REGS Registers
      5. 16.7.5 CPU3_IPC_SEND_REGS Registers
      6. 16.7.6 CPU1_IPC_RCV_REGS Registers
      7. 16.7.7 CPU2_IPC_RCV_REGS Registers
      8. 16.7.8 CPU3_IPC_RCV_REGS Registers
  19. 17Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 17.1 Introduction
    2. 17.2 Enhanced Bus Comparator Unit
      1. 17.2.1 Enhanced Bus Comparator Unit Operations
      2. 17.2.2 Stack Qualification
      3. 17.2.3 Event Masking and Exporting
    3. 17.3 System Event Counter Unit
      1. 17.3.1 System Event Counter Modes
        1. 17.3.1.1 Counting Active Levels Versus Edges
        2. 17.3.1.2 Max and Min Mode
        3. 17.3.1.3 Cumulative Mode
        4. 17.3.1.4 Input Signal Selection
      2. 17.3.2 Reset on Event
      3. 17.3.3 Operation Conditions
    4. 17.4 Program Counter Trace
      1. 17.4.1 Functional Block Diagram
      2. 17.4.2 Trace Qualification Modes
        1. 17.4.2.1 Trace Input Signal Conditioning
      3. 17.4.3 Trace Memory
      4. 17.4.4 PC Trace Software Operation
      5. 17.4.5 Trace Operation in Debug Mode
    5. 17.5 ERAD Ownership, Initialization, and Reset
      1. 17.5.1 Feature Level Ownership
      2. 17.5.2 Feature Access Security Mechanism
      3. 17.5.3 PC Trace Access Security Mechanism
    6. 17.6 ERAD Programming Sequence
      1. 17.6.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 17.6.2 Timer and Counter Programming Sequence
    7. 17.7 Software
      1. 17.7.1 ERAD Registers to Driverlib Functions
    8. 17.8 ERAD Registers
      1. 17.8.1 ERAD Base Address Table
        1. 17.8.1.1 ERAD_REGS Registers
  20. 18Data Logger and Trace (DLT)
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 DLT Related Collateral
      3. 18.1.3 Interfaces
        1. 18.1.3.1 Block Diagram
    2. 18.2 Functional Overview
      1. 18.2.1 DLT Configuration
        1. 18.2.1.1 LINK Filter
        2. 18.2.1.2 TAG Filter
        3. 18.2.1.3 ERAD Event Trigger
        4. 18.2.1.4 Concurrent FILTERING modes
      2. 18.2.2 Time-stamping
      3. 18.2.3 FIFO Construction
        1. 18.2.3.1 FIFO Interrupt
    3. 18.3 Software
      1. 18.3.1 DLT Registers to Driverlib Functions
      2. 18.3.2 DLT Examples
        1. 18.3.2.1 DLT TAG filter example - SINGLE_CORE
        2. 18.3.2.2 DLT TAG filter example - SINGLE_CORE
        3. 18.3.2.3 DLT ERAD filter example - SINGLE_CORE
    4. 18.4 DLT Registers
      1. 18.4.1 DLT Base Address Table
      2. 18.4.2 DLT_CORE_REGS Registers
      3. 18.4.3 DLT_FIFO_REGS Registers
  21. 19Waveform Analyzer Diagnostic (WADI)
    1. 19.1 WADI Overview
      1. 19.1.1 Features
      2. 19.1.2 WADI Related Collateral
      3. 19.1.3 Block Diagram
      4. 19.1.4 Description
    2. 19.2 Signal and Trigger Input Configuration
      1. 19.2.1 SIG1 and SIG2 Configuration
      2. 19.2.2 Trigger 1 and Trigger 2
    3. 19.3 WADI Block
      1. 19.3.1 Overview
      2. 19.3.2 Counters
      3. 19.3.3 Pulse Width
        1. 19.3.3.1 Pulse Width Single Measurement
        2. 19.3.3.2 Pulse Width Aggregation
        3. 19.3.3.3 Pulse Width Average and Peak
      4. 19.3.4 Edge Count
        1. 19.3.4.1 Edge Count with Fixed Window
        2. 19.3.4.2 Edge Count with Moving Window
      5. 19.3.5 Signal1 to Signal2 Comparison
      6. 19.3.6 Dead Band and Phase
      7. 19.3.7 Simultaneous Measurement
    4. 19.4 Safe State Sequencer (SSS)
      1. 19.4.1 SSS Configuration
    5. 19.5 Lock and Commit Registers
    6. 19.6 Interrupt and Error Handling
    7. 19.7 RTDMA Interfaces
      1. 19.7.1 RTDMA Trigger
    8. 19.8 Software
      1. 19.8.1 WADI Registers to Driverlib Functions
      2. 19.8.2 WADI Examples
        1. 19.8.2.1 WADI Duty and Frequency check - SINGLE_CORE
    9. 19.9 WADI Registers
      1. 19.9.1 WADI Base Address Table
      2. 19.9.2 WADI_CONFIG_REGS Registers
      3. 19.9.3 WADI_OPER_SSS_REGS Registers
  22. 20Crossbar (X-BAR)
    1. 20.1 X-BAR Related Collateral
    2. 20.2 Input X-BAR, ICL XBAR, MINDB XBAR,
      1. 20.2.1 ICL and MINDB X-BAR
    3. 20.3 ePWM , CLB, and GPIO Output X-BAR
      1. 20.3.1 ePWM X-BAR
        1. 20.3.1.1 ePWM X-BAR Architecture
      2. 20.3.2 CLB X-BAR
        1. 20.3.2.1 CLB X-BAR Architecture
      3. 20.3.3 GPIO Output X-BAR
        1. 20.3.3.1 GPIO Output X-BAR Architecture
      4. 20.3.4 X-BAR Flags
    4. 20.4 Software
      1. 20.4.1 INPUT_XBAR Registers to Driverlib Functions
      2. 20.4.2 EPWM_XBAR Registers to Driverlib Functions
      3. 20.4.3 CLB_XBAR Registers to Driverlib Functions
      4. 20.4.4 OUTPUT_XBAR Registers to Driverlib Functions
      5. 20.4.5 MDL_XBAR Registers to Driverlib Functions
      6. 20.4.6 ICL_XBAR Registers to Driverlib Functions
      7. 20.4.7 XBAR Registers to Driverlib Functions
      8. 20.4.8 XBAR Examples
        1. 20.4.8.1 Input XBAR to Output XBAR Connection - SINGLE_CORE
        2. 20.4.8.2 Output XBAR Pulse Stretch - SINGLE_CORE
    5. 20.5 XBAR Registers
      1. 20.5.1 XBAR Base Address Table
      2. 20.5.2 INPUT_XBAR_REGS Registers
      3. 20.5.3 EPWM_XBAR_REGS Registers
      4. 20.5.4 CLB_XBAR_REGS Registers
      5. 20.5.5 OUTPUTXBAR_REGS Registers
      6. 20.5.6 MDL_XBAR_REGS Registers
      7. 20.5.7 ICL_XBAR_REGS Registers
      8. 20.5.8 OUTPUTXBAR_FLAG_REGS Registers
      9. 20.5.9 XBAR_REGS Registers
  23. 21Embedded Pattern Generator (EPG)
    1. 21.1 Introduction
      1. 21.1.1 Features
      2. 21.1.2 EPG Block Diagram
      3. 21.1.3 EPG Related Collateral
    2. 21.2 Clock Generator Modules
      1. 21.2.1 DCLK (50% duty cycle clock)
      2. 21.2.2 Clock Stop
    3. 21.3 Signal Generator Module
    4. 21.4 EPG Peripheral Signal Mux Selection
    5. 21.5 Application Software Notes
    6. 21.6 EPG Example Use Cases
      1. 21.6.1 EPG Example: Synchronous Clocks with Offset
        1. 21.6.1.1 Synchronous Clocks with Offset Register Configuration
      2. 21.6.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 21.6.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 21.6.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 21.6.3.1 Serial Data Bit Stream (MSB first) Register Configuration
      4. 21.6.4 EPG Example: Clock and Data Pair
        1. 21.6.4.1 Clock and Data Pair Register Configuration
      5. 21.6.5 EPG Example: Clock and Skewed Data Pair
        1. 21.6.5.1 Clock and Skewed Data Pair Register Configuration
      6. 21.6.6 EPG Example: Capturing Serial Data with a Known Baud Rate
        1. 21.6.6.1 Capturing Serial Data with a Known Baud Rate Register Configuration
    7. 21.7 EPG Interrupt
    8. 21.8 Software
      1. 21.8.1 EPG Registers to Driverlib Functions
      2. 21.8.2 EPG Examples
        1. 21.8.2.1 EPG Generating Synchronous Clocks - SINGLE_CORE
        2. 21.8.2.2 EPG Generating Two Offset Clocks - SINGLE_CORE
        3. 21.8.2.3 EPG Generating Two Offset Clocks With SIGGEN - SINGLE_CORE
        4. 21.8.2.4 EPG Generate Serial Data - SINGLE_CORE
        5. 21.8.2.5 EPG Generate Serial Data Shift Mode - SINGLE_CORE
    9. 21.9 EPG Registers
      1. 21.9.1 EPG Base Address Table
      2. 21.9.2 EPG_REGS Registers
      3. 21.9.3 EPG_MUX_REGS Registers
  24. 22â–º ANALOG PERIPHERALS
    1.     Technical Reference Manual Overview
  25. 23Analog Subsystem
    1. 23.1 Introduction
      1. 23.1.1 Features
      2. 23.1.2 Block Diagram
    2. 23.2 Optimizing Power-Up Time
    3. 23.3 Digital Inputs on ADC Pins (AIOs)
    4. 23.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 23.5 Analog Pins and Internal Connections
    6. 23.6 Software
      1. 23.6.1 ASYSCTL Registers to Driverlib Functions
    7. 23.7 Lock Registers
    8. 23.8 ASBSYS Registers
      1. 23.8.1 ASBSYS Base Address Table
      2. 23.8.2 ANALOG_SUBSYS_REGS Registers
  26. 24Analog-to-Digital Converter (ADC)
    1. 24.1  Introduction
      1. 24.1.1 ADC Related Collateral
      2. 24.1.2 Features
      3. 24.1.3 Block Diagram
    2. 24.2  ADC Configurability
      1. 24.2.1 Clock Configuration
      2. 24.2.2 Resolution
      3. 24.2.3 Voltage Reference
        1. 24.2.3.1 External Reference Mode
        2. 24.2.3.2 Internal Reference Mode
        3. 24.2.3.3 Ganged References
        4. 24.2.3.4 Selecting Reference Mode
      4. 24.2.4 Signal Mode
      5. 24.2.5 Expected Conversion Results
      6. 24.2.6 Interpreting Conversion Results
    3. 24.3  SOC Principle of Operation
      1. 24.3.1 SOC Configuration
      2. 24.3.2 Trigger Operation
        1. 24.3.2.1 Global Software Trigger
        2. 24.3.2.2 Trigger Repeaters
          1. 24.3.2.2.1 Oversampling Mode
          2. 24.3.2.2.2 Undersampling Mode
          3. 24.3.2.2.3 Trigger Phase Delay
          4. 24.3.2.2.4 Re-trigger Spread
          5. 24.3.2.2.5 Trigger Repeater Configuration
            1. 24.3.2.2.5.1 Register Shadow Updates
          6. 24.3.2.2.6 Re-Trigger Logic
          7. 24.3.2.2.7 Multi-Path Triggering Behavior
      3. 24.3.3 ADC Acquisition (Sample and Hold) Window
      4. 24.3.4 ADC Input Models
      5. 24.3.5 Channel Selection
        1. 24.3.5.1 External Channel Selection
          1. 24.3.5.1.1 External Channel Selection Timing
    4. 24.4  SOC Configuration Examples
      1. 24.4.1 Single Conversion from ePWM Trigger
      2. 24.4.2 Oversampled Conversion from ePWM Trigger
      3. 24.4.3 Multiple Conversions from CPU Timer Trigger
      4. 24.4.4 Software Triggering of SOCs
    5. 24.5  ADC Conversion Priority
    6. 24.6  Burst Mode
      1. 24.6.1 Burst Mode Example
      2. 24.6.2 Burst Mode Priority Example
    7. 24.7  EOC and Interrupt Operation
      1. 24.7.1 Interrupt Overflow
      2. 24.7.2 Continue to Interrupt Mode
      3. 24.7.3 Early Interrupt Configuration Mode
    8. 24.8  Post-Processing Blocks
      1. 24.8.1 PPB Offset Correction
      2. 24.8.2 PPB Error Calculation
      3. 24.8.3 PPB Result Delta Calculation
      4. 24.8.4 PPB Limit Detection and Zero-Crossing Detection
        1. 24.8.4.1 PPB Digital Trip Filter
      5. 24.8.5 PPB Sample Delay Capture
      6. 24.8.6 PPB Oversampling
        1. 24.8.6.1 Accumulation, Minimum, Maximum, and Average Functions
        2. 24.8.6.2 Outlier Rejection
    9. 24.9  Result Safety Checker
      1. 24.9.1 Result Safety Checker Operation
      2. 24.9.2 Result Safety Checker Interrupts and Events
    10. 24.10 Opens/Shorts Detection Circuit (OSDETECT)
      1. 24.10.1 Implementation
      2. 24.10.2 Detecting an Open Input Pin
      3. 24.10.3 Detecting a Shorted Input Pin
    11. 24.11 Power-Up Sequence
    12. 24.12 ADC Calibration
      1. 24.12.1 ADC Zero Offset Calibration
    13. 24.13 ADC Timings
      1. 24.13.1 ADC Timing Diagrams
      2. 24.13.2 Post-Processing Block Timings
    14. 24.14 Additional Information
      1. 24.14.1 Ensuring Synchronous Operation
        1. 24.14.1.1 Basic Synchronous Operation
        2. 24.14.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 24.14.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 24.14.1.4 Synchronous Operation with Different Resolutions
        5. 24.14.1.5 Non-overlapping Conversions
      2. 24.14.2 Choosing an Acquisition Window Duration
      3. 24.14.3 Achieving Simultaneous Sampling
      4. 24.14.4 Result Register Mapping
      5. 24.14.5 Internal Temperature Sensor
      6. 24.14.6 Designing an External Reference Circuit
      7. 24.14.7 Internal Test Mode
      8. 24.14.8 ADC Gain and Offset Calibration
    15. 24.15 Software
      1. 24.15.1 ADC Registers to Driverlib Functions
      2. 24.15.2 ADC Examples
        1. 24.15.2.1  ADC Software Triggering - SINGLE_CORE
        2. 24.15.2.2  ADC ePWM Triggering - SINGLE_CORE
        3. 24.15.2.3  ADC Temperature Sensor Conversion - SINGLE_CORE
        4. 24.15.2.4  ADC Synchronous SOC Software Force (adc_soc_software_sync) - SINGLE_CORE
        5. 24.15.2.5  ADC Continuous Triggering (adc_soc_continuous) - SINGLE_CORE
        6. 24.15.2.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma) - SINGLE_CORE
        7. 24.15.2.7  ADC PPB Offset (adc_ppb_offset) - SINGLE_CORE
        8. 24.15.2.8  ADC PPB Limits (adc_ppb_limits) - SINGLE_CORE
        9. 24.15.2.9  ADC PPB Delay Capture (adc_ppb_delay) - SINGLE_CORE
        10. 24.15.2.10 ADC ePWM Triggering Multiple SOC - SINGLE_CORE
        11. 24.15.2.11 ADC Burst Mode - SINGLE_CORE
        12. 24.15.2.12 ADC Burst Mode Oversampling - SINGLE_CORE
        13. 24.15.2.13 ADC SOC Oversampling - SINGLE_CORE
        14. 24.15.2.14 ADC PPB PWM trip (adc_ppb_pwm_trip) - SINGLE_CORE
        15. 24.15.2.15 ADC Trigger Repeater Oversampling - SINGLE_CORE
        16. 24.15.2.16 ADC Trigger Repeater Undersampling - SINGLE_CORE
        17. 24.15.2.17 ADC Safety Checker - SINGLE_CORE
    16. 24.16 ADC Registers
      1. 24.16.1 ADC Base Address Table
      2. 24.16.2 ADC_RESULT_REGS Registers
      3. 24.16.3 ADC_REGS Registers
      4. 24.16.4 ADC_SAFECHECK_REGS Registers
      5. 24.16.5 ADC_SAFECHECK_INTEVT_REGS Registers
      6. 24.16.6 ADC_GLOBAL_REGS Registers
  27. 25Buffered Digital-to-Analog Converter (DAC)
    1. 25.1 Introduction
      1. 25.1.1 DAC Related Collateral
      2. 25.1.2 Features
      3. 25.1.3 Block Diagram
    2. 25.2 Using the DAC
      1. 25.2.1 Initialization Sequence
      2. 25.2.2 DAC Offset Adjustment
      3. 25.2.3 EPWMSYNCPER Signal
    3. 25.3 Lock Registers
    4. 25.4 Software
      1. 25.4.1 DAC Registers to Driverlib Functions
      2. 25.4.2 DAC Examples
        1. 25.4.2.1 Buffered DAC Enable - SINGLE_CORE
        2. 25.4.2.2 Buffered DAC Random - SINGLE_CORE
    5. 25.5 DAC Registers
      1. 25.5.1 DAC Base Address Table
      2. 25.5.2 DAC_REGS Registers
  28. 26Comparator Subsystem (CMPSS)
    1. 26.1 Introduction
      1. 26.1.1 CMPSS Related Collateral
      2. 26.1.2 Features
      3. 26.1.3 Block Diagram
    2. 26.2 Comparator
    3. 26.3 Reference DAC
    4. 26.4 Ramp Generator
      1. 26.4.1 Ramp Generator Overview
      2. 26.4.2 Ramp Generator Behavior
      3. 26.4.3 Ramp Generator Behavior at Corner Cases
    5. 26.5 Digital Filter
      1. 26.5.1 Filter Initialization Sequence
    6. 26.6 Using the CMPSS
      1. 26.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 26.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 26.6.3 Calibrating the CMPSS
      4. 26.6.4 Enabling and Disabling the CMPSS Clock
    7. 26.7 Software
      1. 26.7.1 CMPSS Registers to Driverlib Functions
      2. 26.7.2 CMPSS Examples
        1. 26.7.2.1 CMPSS Asynchronous Trip - SINGLE_CORE
        2. 26.7.2.2 CMPSS Digital Filter Configuration - SINGLE_CORE
    8. 26.8 CMPSS Registers
      1. 26.8.1 CMPSS Base Address Table
      2. 26.8.2 CMPSS_REGS Registers
  29. 27â–º CONTROL PERIPHERALS
    1.     Technical Reference Manual Overview
  30. 28Enhanced Capture (eCAP)
    1. 28.1 Introduction
      1. 28.1.1 Features
      2. 28.1.2 ECAP Related Collateral
    2. 28.2 Description
    3. 28.3 Configuring Device Pins for the eCAP
    4. 28.4 Capture and APWM Operating Mode
    5. 28.5 Capture Mode Description
      1. 28.5.1  Event Prescaler
      2. 28.5.2  Glitch Filter
      3. 28.5.3  Edge Polarity Select and Qualifier
      4. 28.5.4  Continuous/One-Shot Control
      5. 28.5.5  32-Bit Counter and Phase Control
      6. 28.5.6  CAP1-CAP4 Registers
      7. 28.5.7  eCAP Synchronization
        1. 28.5.7.1 Example 1 - Using SWSYNC with ECAP Module
      8. 28.5.8  Interrupt Control
      9. 28.5.9  RTDMA Interrupt
      10. 28.5.10 ADC SOC Event
      11. 28.5.11 Shadow Load and Lockout Control
      12. 28.5.12 APWM Mode Operation
      13. 28.5.13 Signal Monitoring Unit
        1. 28.5.13.1 Pulse Width and Period Monitoring
        2. 28.5.13.2 Edge Monitoring
    6. 28.6 Application of the eCAP Module
      1. 28.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 28.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 28.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 28.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 28.7 Application of the APWM Mode
      1. 28.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 28.8 Software
      1. 28.8.1 ECAP Registers to Driverlib Functions
      2. 28.8.2 ECAP Examples
        1. 28.8.2.1 eCAP APWM Example - SINGLE_CORE
        2. 28.8.2.2 eCAP Capture PWM Example - SINGLE_CORE
        3. 28.8.2.3 eCAP APWM Phase-shift Example - SINGLE_CORE
    9. 28.9 ECAP Registers
      1. 28.9.1 ECAP Base Address Table
      2. 28.9.2 ECAP_REGS Registers
      3. 28.9.3 ECAP_SIGNAL_MONITORING Registers
      4. 28.9.4 HRCAP_REGS Registers
  31. 29High Resolution Capture (HRCAP)
    1. 29.1 Introduction
      1. 29.1.1 HRCAP Related Collateral
      2. 29.1.2 Features
      3. 29.1.3 Description
    2. 29.2 Operational Details
      1. 29.2.1 HRCAP Clocking
      2. 29.2.2 HRCAP Initialization Sequence
      3. 29.2.3 HRCAP Interrupts
      4. 29.2.4 HRCAP Calibration
        1. 29.2.4.1 Applying the Scale Factor
    3. 29.3 Known Exceptions
    4. 29.4 Software
      1. 29.4.1 HRCAP Examples
        1. 29.4.1.1 HRCAP Capture and Calibration Example - SINGLE_CORE
    5. 29.5 HRCAP Registers
      1. 29.5.1 HRCAP Base Address Table
      2. 29.5.2 HRCAP_REGS Registers
  32. 30Enhanced Pulse Width Modulator (ePWM)
    1. 30.1  Introduction
      1. 30.1.1 EPWM Related Collateral
      2. 30.1.2 Submodule Overview
    2. 30.2  Configuring Device Pins
    3. 30.3  ePWM Modules Overview
    4. 30.4  Time-Base (TB) Submodule
      1. 30.4.1 Purpose of the Time-Base Submodule
      2. 30.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 30.4.3 Calculating PWM Period and Frequency
        1. 30.4.3.1 Time-Base Period Shadow Register
        2. 30.4.3.2 Time-Base Clock Synchronization
        3. 30.4.3.3 Time-Base Counter Synchronization
        4. 30.4.3.4 ePWM SYNC Selection
      4. 30.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 30.4.5 Simultaneous Writes Between ePWM Register Instances
      6. 30.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 30.4.7 Global Load
        1. 30.4.7.1 Global Load Pulse Pre-Scalar
        2. 30.4.7.2 One-Shot Load Mode
        3. 30.4.7.3 One-Shot Sync Mode
    5. 30.5  Counter-Compare (CC) Submodule
      1. 30.5.1 Purpose of the Counter-Compare Submodule
      2. 30.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 30.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 30.5.4 Count Mode Timing Waveforms
    6. 30.6  Action-Qualifier (AQ) Submodule
      1. 30.6.1 Purpose of the Action-Qualifier Submodule
      2. 30.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 30.6.3 Action-Qualifier Event Priority
      4. 30.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 30.6.5 Configuration Requirements for Common Waveforms
    7. 30.7  XCMP Complex Waveform Generator Mode
      1. 30.7.1 XCMP Allocation to CMPA and CMPB
      2. 30.7.2 XCMP Shadow Buffers
      3. 30.7.3 XCMP Operation
    8. 30.8  Dead-Band Generator (DB) Submodule
      1. 30.8.1 Purpose of the Dead-Band Submodule
      2. 30.8.2 Dead-band Submodule Additional Operating Modes
      3. 30.8.3 Operational Highlights for the Dead-Band Submodule
    9. 30.9  PWM Chopper (PC) Submodule
      1. 30.9.1 Purpose of the PWM Chopper Submodule
      2. 30.9.2 Operational Highlights for the PWM Chopper Submodule
      3. 30.9.3 Waveforms
        1. 30.9.3.1 One-Shot Pulse
        2. 30.9.3.2 Duty Cycle Control
    10. 30.10 Trip-Zone (TZ) Submodule
      1. 30.10.1 Purpose of the Trip-Zone Submodule
      2. 30.10.2 Operational Highlights for the Trip-Zone Submodule
        1. 30.10.2.1 Trip-Zone Configurations
      3. 30.10.3 Generating Trip Event Interrupts
    11. 30.11 Diode Emulation (DE) Submodule
      1. 30.11.1 DEACTIVE Mode
      2. 30.11.2 Exiting DE Mode
      3. 30.11.3 Re-Entering DE Mode
      4. 30.11.4 DE Monitor
    12. 30.12 Minimum Dead-Band (MINDB) + Illegal Combination Logic (ICL) Submodules
      1. 30.12.1 Minimum Dead-Band (MINDB)
      2. 30.12.2 Illegal Combo Logic (ICL)
    13. 30.13 Event-Trigger (ET) Submodule
      1. 30.13.1 Operational Overview of the ePWM Event-Trigger Submodule
    14. 30.14 Digital Compare (DC) Submodule
      1. 30.14.1 Purpose of the Digital Compare Submodule
      2. 30.14.2 Enhanced Trip Action Using CMPSS
      3. 30.14.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 30.14.4 Operation Highlights of the Digital Compare Submodule
        1. 30.14.4.1 Digital Compare Events
        2. 30.14.4.2 Event Filtering
        3. 30.14.4.3 Valley Switching
        4. 30.14.4.4 Event Detection
          1. 30.14.4.4.1 Input Signal Detection
          2. 30.14.4.4.2 MIN and MAX Detection Circuit
    15. 30.15 ePWM Crossbar (X-BAR)
    16. 30.16 Applications to Power Topologies
      1. 30.16.1  Overview of Multiple Modules
      2. 30.16.2  Key Configuration Capabilities
      3. 30.16.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 30.16.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 30.16.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 30.16.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 30.16.7  Practical Applications Using Phase Control Between PWM Modules
      8. 30.16.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 30.16.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 30.16.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 30.16.11 Controlling H-Bridge LLC Resonant Converter
    17. 30.17 Register Lock Protection
    18. 30.18 High-Resolution Pulse Width Modulator (HRPWM)
      1. 30.18.1 Operational Description of HRPWM
        1. 30.18.1.1 Controlling the HRPWM Capabilities
        2. 30.18.1.2 HRPWM Source Clock
        3. 30.18.1.3 Configuring the HRPWM
        4. 30.18.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 30.18.1.5 Principle of Operation
          1. 30.18.1.5.1 Edge Positioning
          2. 30.18.1.5.2 Scaling Considerations
          3. 30.18.1.5.3 Duty Cycle Range Limitation
          4. 30.18.1.5.4 High-Resolution Period
            1. 30.18.1.5.4.1 High-Resolution Period Configuration
        6. 30.18.1.6 Deadband High-Resolution Operation
        7. 30.18.1.7 Scale Factor Optimizing Software (SFO)
        8. 30.18.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 30.18.1.8.1 #Defines for HRPWM Header Files
          2. 30.18.1.8.2 Implementing a Simple Buck Converter
            1. 30.18.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 30.18.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 30.18.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 30.18.1.8.3.1 PWM DAC Function Initialization Code
            2. 30.18.1.8.3.2 PWM DAC Function Run-Time Code
      2. 30.18.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 30.18.2.1 Scale Factor Optimizer Function - int SFO()
        2. 30.18.2.2 Software Usage
          1. 30.18.2.2.1 A Sample of How to Add "Include" Files
          2.        1131
          3. 30.18.2.2.2 Declaring an Element
          4.        1133
          5. 30.18.2.2.3 Initializing With a Scale Factor Value
          6.        1135
          7. 30.18.2.2.4 SFO Function Calls
    19. 30.19 Software
      1. 30.19.1 EPWM Registers to Driverlib Functions
      2. 30.19.2 HRPWMCAL Registers to Driverlib Functions
      3. 30.19.3 EPWM Examples
        1. 30.19.3.1  ePWM Trip Zone - SINGLE_CORE
        2. 30.19.3.2  ePWM Up Down Count Action Qualifier - SINGLE_CORE
        3. 30.19.3.3  ePWM Synchronization - SINGLE_CORE
        4. 30.19.3.4  ePWM Digital Compare - SINGLE_CORE
        5. 30.19.3.5  ePWM Digital Compare Event Filter Blanking Window - SINGLE_CORE
        6. 30.19.3.6  ePWM Valley Switching - SINGLE_CORE
        7. 30.19.3.7  ePWM Digital Compare Edge Filter - SINGLE_CORE
        8. 30.19.3.8  ePWM Deadband - SINGLE_CORE
        9. 30.19.3.9  ePWM DMA - SINGLE_CORE
        10. 30.19.3.10 ePWM Chopper - SINGLE_CORE
        11. 30.19.3.11 EPWM Configure Signal - SINGLE_CORE
        12. 30.19.3.12 Realization of Monoshot mode - SINGLE_CORE
        13. 30.19.3.13 EPWM Action Qualifier (epwm_up_aq) - SINGLE_CORE
        14. 30.19.3.14 ePWM XCMP Mode - SINGLE_CORE
        15. 30.19.3.15 ePWM Event Detection - SINGLE_CORE
    20. 30.20 EPWM Registers
      1. 30.20.1 EPWM Base Address Table
      2. 30.20.2 EPWM_REGS Registers
      3. 30.20.3 EPWM_XCMP_REGS Registers
      4. 30.20.4 DE_REGS Registers
      5. 30.20.5 MINDB_LUT_REGS Registers
      6. 30.20.6 HRPWMCAL_REGS Registers
  33. 31Enhanced Quadrature Encoder Pulse (eQEP)
    1. 31.1  Introduction
      1. 31.1.1 EQEP Related Collateral
    2. 31.2  Configuring Device Pins
    3. 31.3  Description
      1. 31.3.1 EQEP Inputs
      2. 31.3.2 Functional Description
      3. 31.3.3 eQEP Memory Map
    4. 31.4  Quadrature Decoder Unit (QDU)
      1. 31.4.1 Position Counter Input Modes
        1. 31.4.1.1 Quadrature Count Mode
        2. 31.4.1.2 Direction-Count Mode
        3. 31.4.1.3 Up-Count Mode
        4. 31.4.1.4 Down-Count Mode
      2. 31.4.2 eQEP Input Polarity Selection
      3. 31.4.3 Position-Compare Sync Output
    5. 31.5  Position Counter and Control Unit (PCCU)
      1. 31.5.1 Position Counter Operating Modes
        1. 31.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 31.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 31.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 31.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 31.5.2 Position Counter Latch
        1. 31.5.2.1 Index Event Latch
        2. 31.5.2.2 Strobe Event Latch
      3. 31.5.3 Position Counter Initialization
      4. 31.5.4 eQEP Position-compare Unit
    6. 31.6  eQEP Edge Capture Unit
    7. 31.7  eQEP Watchdog
    8. 31.8  eQEP Unit Timer Base
    9. 31.9  QMA Module
      1. 31.9.1 Modes of Operation
        1. 31.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 31.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 31.9.2 Interrupt and Error Generation
    10. 31.10 eQEP Interrupt Structure
    11. 31.11 Software
      1. 31.11.1 EQEP Registers to Driverlib Functions
      2. 31.11.2 EQEP Examples
        1. 31.11.2.1 Frequency Measurement Using eQEP via unit timeout interrupt - SINGLE_CORE
        2. 31.11.2.2 Motor speed and direction measurement using eQEP via unit timeout interrupt - SINGLE_CORE
    12. 31.12 EQEP Registers
      1. 31.12.1 EQEP Base Address Table
      2. 31.12.2 EQEP_REGS Registers
  34. 32Sigma Delta Filter Module (SDFM)
    1. 32.1  Introduction
      1. 32.1.1 SDFM Related Collateral
      2. 32.1.2 Features
      3. 32.1.3 Block Diagram
    2. 32.2  Configuring Device Pins
    3. 32.3  Input Qualification
    4. 32.4  Input Control Unit
    5. 32.5  SDFM Clock Control
    6. 32.6  Sinc Filter
      1. 32.6.1 Data Rate and Latency of the Sinc Filter
    7. 32.7  Data (Primary) Filter Unit
      1. 32.7.1 32-bit or 16-bit Data Filter Output Representation
      2. 32.7.2 Data FIFO
      3. 32.7.3 SDSYNC Event
    8. 32.8  Comparator (Secondary) Filter Unit
      1. 32.8.1 Higher Threshold (HLT) Comparators
      2. 32.8.2 Lower Threshold (LLT) Comparators
      3. 32.8.3 Digital Filter
    9. 32.9  Theoretical SDFM Filter Output
    10. 32.10 Interrupt Unit
      1. 32.10.1 SDFM (SDyERR) Interrupt Sources
      2. 32.10.2 Data Ready (DRINT) Interrupt Sources
    11. 32.11 Software
      1. 32.11.1 SDFM Registers to Driverlib Functions
      2. 32.11.2 SDFM Examples
    12. 32.12 SDFM Registers
      1. 32.12.1 SDFM Base Address Table
      2. 32.12.2 SDFM_REGS Registers
  35. 33â–º COMMUNICATION PERIPHERALS
    1.     Technical Reference Manual Overview
  36. 34Modular Controller Area Network (MCAN)
    1. 34.1 MCAN Introduction
      1. 34.1.1 MCAN Related Collateral
      2. 34.1.2 MCAN Features
    2. 34.2 MCAN Environment
    3. 34.3 CAN Network Basics
    4. 34.4 MCAN Integration
    5. 34.5 MCAN Functional Description
      1. 34.5.1  Module Clocking Requirements
      2. 34.5.2  Interrupt Requests
      3. 34.5.3  Operating Modes
        1. 34.5.3.1 Software Initialization
        2. 34.5.3.2 Normal Operation
        3. 34.5.3.3 CAN FD Operation
      4. 34.5.4  Transmitter Delay Compensation
        1. 34.5.4.1 Description
        2. 34.5.4.2 Transmitter Delay Compensation Measurement
      5. 34.5.5  Restricted Operation Mode
      6. 34.5.6  Bus Monitoring Mode
      7. 34.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 34.5.7.1 Frame Transmission in DAR Mode
      8. 34.5.8  Clock Stop Mode
        1. 34.5.8.1 Suspend Mode
        2. 34.5.8.2 Wakeup Request
      9. 34.5.9  Test Modes
        1. 34.5.9.1 External Loop Back Mode
        2. 34.5.9.2 Internal Loop Back Mode
      10. 34.5.10 Timestamp Generation
        1. 34.5.10.1 External Timestamp Counter
      11. 34.5.11 Timeout Counter
      12. 34.5.12 Safety
        1. 34.5.12.1 ECC Wrapper
        2. 34.5.12.2 ECC Aggregator
          1. 34.5.12.2.1 ECC Aggregator Overview
          2. 34.5.12.2.2 ECC Aggregator Registers
        3. 34.5.12.3 Reads to ECC Control and Status Registers
        4. 34.5.12.4 ECC Interrupts
      13. 34.5.13 Rx Handling
        1. 34.5.13.1 Acceptance Filtering
          1. 34.5.13.1.1 Range Filter
          2. 34.5.13.1.2 Filter for Specific IDs
          3. 34.5.13.1.3 Classic Bit Mask Filter
          4. 34.5.13.1.4 Standard Message ID Filtering
          5. 34.5.13.1.5 Extended Message ID Filtering
        2. 34.5.13.2 Rx FIFOs
          1. 34.5.13.2.1 Rx FIFO Blocking Mode
          2. 34.5.13.2.2 Rx FIFO Overwrite Mode
        3. 34.5.13.3 Dedicated Rx Buffers
          1. 34.5.13.3.1 Rx Buffer Handling
      14. 34.5.14 Tx Handling
        1. 34.5.14.1 Transmit Pause
        2. 34.5.14.2 Dedicated Tx Buffers
        3. 34.5.14.3 Tx FIFO
        4. 34.5.14.4 Tx Queue
        5. 34.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 34.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 34.5.14.7 Transmit Cancellation
        8. 34.5.14.8 Tx Event Handling
      15. 34.5.15 FIFO Acknowledge Handling
      16. 34.5.16 Message RAM
        1. 34.5.16.1 Message RAM Configuration
        2. 34.5.16.2 Rx Buffer and FIFO Element
        3. 34.5.16.3 Tx Buffer Element
        4. 34.5.16.4 Tx Event FIFO Element
        5. 34.5.16.5 Standard Message ID Filter Element
        6. 34.5.16.6 Extended Message ID Filter Element
    6. 34.6 Software
      1. 34.6.1 MCAN Examples
        1. 34.6.1.1 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
        2. 34.6.1.2 MCAN Loopback with Polling Example Using SYSCONFIG Tool - SINGLE_CORE
        3. 34.6.1.3 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
    7. 34.7 MCAN Registers
      1. 34.7.1 MCAN Base Address Table
      2. 34.7.2 MCANSS_REGS Registers
      3. 34.7.3 MCAN_REGS Registers
      4. 34.7.4 MCAN_ERROR_REGS Registers
  37. 35EtherCAT® SubordinateDevice Controller (ESC)
    1. 35.1 Introduction
      1. 35.1.1  EtherCAT Related Collateral
      2. 35.1.2  ESC Features
      3. 35.1.3  ESC Subsystem Integrated Features
      4. 35.1.4  ESC versus Beckhoff ET1100
      5. 35.1.5  EtherCAT IP Block Diagram
      6. 35.1.6  ESC Functional Blocks
        1. 35.1.6.1  Interface to EtherCAT MainDevice
        2. 35.1.6.2  Process Data Interface
        3. 35.1.6.3  General-Purpose Inputs and Outputs
        4. 35.1.6.4  EtherCAT Processing Unit (EPU)
        5. 35.1.6.5  Fieldbus Memory Management Unit (FMMU)
        6. 35.1.6.6  Sync Manager
        7. 35.1.6.7  Monitoring
        8. 35.1.6.8  Reset Controller
        9. 35.1.6.9  PHY Management
        10. 35.1.6.10 Distributed Clock (DC)
        11. 35.1.6.11 EEPROM
        12. 35.1.6.12 Status / LEDs
      7. 35.1.7  EtherCAT Physical Layer
        1. 35.1.7.1 MII Interface
        2. 35.1.7.2 PHY Management Interface
          1. 35.1.7.2.1 PHY Address Configuration
          2. 35.1.7.2.2 PHY Reset Signal
          3. 35.1.7.2.3 PHY Clock
      8. 35.1.8  EtherCAT Protocol
      9. 35.1.9  EtherCAT State Machine (ESM)
      10. 35.1.10 More Information on EtherCAT
      11. 35.1.11 Beckhoff® Automation EtherCAT IP Errata
    2. 35.2 ESC and ESCSS Description
      1. 35.2.1  ESC RAM Parity and Memory Address Maps
        1. 35.2.1.1 ESC RAM Parity Logic
        2. 35.2.1.2 CPU1 ESC Memory Address Map
        3. 35.2.1.3 CPU2 ESC Memory Address Map
      2. 35.2.2  Local Host Communication
        1. 35.2.2.1 Byte Accessibility Through PDI
        2. 35.2.2.2 Software Details for Operation Across Clock Domains
      3. 35.2.3  Debug Emulation Mode Operation
      4. 35.2.4  ESC SubSystem
        1. 35.2.4.1 CPU1 Bus Interface
        2. 35.2.4.2 CPU2/CPU3 Bus Interface
      5. 35.2.5  Interrupts and Interrupt Mapping
      6. 35.2.6  Power, Clocks, and Resets
        1. 35.2.6.1 Power
        2. 35.2.6.2 Clocking
        3. 35.2.6.3 Resets
          1. 35.2.6.3.1 Chip-Level Reset
          2. 35.2.6.3.2 EtherCAT Soft Resets
          3. 35.2.6.3.3 Reset Out (RESET_OUT)
      7. 35.2.7  LED Controls
      8. 35.2.8  SubordinateDevice Node Configuration and EEPROM
      9. 35.2.9  General-Purpose Inputs and Outputs
        1. 35.2.9.1 General-Purpose Inputs
        2. 35.2.9.2 General-Purpose Output
      10. 35.2.10 Distributed Clocks – Sync and Latch
        1. 35.2.10.1 Clock Synchronization
        2. 35.2.10.2 SYNC Signals
          1. 35.2.10.2.1 Seeking Host Intervention
        3. 35.2.10.3 LATCH Signals
          1. 35.2.10.3.1 Timestamping
        4. 35.2.10.4 Device Control and Synchronization
          1. 35.2.10.4.1 Synchronization of PWM
          2. 35.2.10.4.2 ECAP SYNC Inputs
          3. 35.2.10.4.3 SYNC Signal Conditioning and Rerouting
    3. 35.3 Software Initialization Sequence and Allocating Ownership
    4. 35.4 ESC Configuration Constants
    5. 35.5 Software
      1. 35.5.1 ECAT_SS Registers to Driverlib Functions
      2. 35.5.2 ETHERNET Examples
    6. 35.6 ETHERCAT Registers
      1. 35.6.1 ETHERCAT Base Address Table
      2. 35.6.2 ESCSS_REGS Registers
      3. 35.6.3 ESCSS_CONFIG_REGS Registers
  38. 36Fast Serial Interface (FSI)
    1. 36.1 Introduction
      1. 36.1.1 FSI Related Collateral
      2. 36.1.2 FSI Features
    2. 36.2 System-level Integration
      1. 36.2.1 CPU Interface
      2. 36.2.2 Signal Description
        1. 36.2.2.1 Configuring Device Pins
      3. 36.2.3 FSI Interrupts
        1. 36.2.3.1 Transmitter Interrupts
        2. 36.2.3.2 Receiver Interrupts
        3. 36.2.3.3 Configuring Interrupts
        4. 36.2.3.4 Handling Interrupts
      4. 36.2.4 RTDMA Interface
      5. 36.2.5 External Frame Trigger Mux
    3. 36.3 FSI Functional Description
      1. 36.3.1 Introduction to Operation
      2. 36.3.2 FSI Transmitter Module
        1. 36.3.2.1 Initialization
        2. 36.3.2.2 FSI_TX Clocking
        3. 36.3.2.3 Transmitting Frames
          1. 36.3.2.3.1 Software Triggered Frames
          2. 36.3.2.3.2 Externally Triggered Frames
          3. 36.3.2.3.3 Ping Frame Generation
            1. 36.3.2.3.3.1 Automatic Ping Frames
            2. 36.3.2.3.3.2 Software Triggered Ping Frame
            3. 36.3.2.3.3.3 Externally Triggered Ping Frame
          4. 36.3.2.3.4 Transmitting Frames with RTDMA
        4. 36.3.2.4 Transmit Buffer Management
        5. 36.3.2.5 CRC Submodule
        6. 36.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 36.3.2.7 Reset
      3. 36.3.3 FSI Receiver Module
        1. 36.3.3.1  Initialization
        2. 36.3.3.2  FSI_RX Clocking
        3. 36.3.3.3  Receiving Frames
          1. 36.3.3.3.1 Receiving Frames with RTDMA
        4. 36.3.3.4  Ping Frame Watchdog
        5. 36.3.3.5  Frame Watchdog
        6. 36.3.3.6  Delay Line Control
        7. 36.3.3.7  Buffer Management
        8. 36.3.3.8  CRC Submodule
        9. 36.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 36.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 36.3.3.11 FSI_RX Reset
      4. 36.3.4 Frame Format
        1. 36.3.4.1 FSI Frame Phases
        2. 36.3.4.2 Frame Types
          1. 36.3.4.2.1 Ping Frames
          2. 36.3.4.2.2 Error Frames
          3. 36.3.4.2.3 Data Frames
        3. 36.3.4.3 Multi-Lane Transmission
      5. 36.3.5 Flush Sequence
      6. 36.3.6 Internal Loopback
      7. 36.3.7 CRC Generation
      8. 36.3.8 ECC Module
      9. 36.3.9 FSI-SPI Compatibility Mode
        1. 36.3.9.1 Available SPI Modes
          1. 36.3.9.1.1 FSITX as SPI Controller, Transmit Only
            1. 36.3.9.1.1.1 Initialization
            2. 36.3.9.1.1.2 Operation
          2. 36.3.9.1.2 FSIRX as SPI Peripheral, Receive Only
            1. 36.3.9.1.2.1 Initialization
            2. 36.3.9.1.2.2 Operation
          3. 36.3.9.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
            1. 36.3.9.1.3.1 Initialization
            2. 36.3.9.1.3.2 Operation
    4. 36.4 FSI Programing Guide
      1. 36.4.1 Establishing the Communication Link
        1. 36.4.1.1 Establishing the Communication Link from the Main Device
        2. 36.4.1.2 Establishing the Communication Link from the Remote Device
      2. 36.4.2 Register Protection
      3. 36.4.3 Emulation Mode
    5. 36.5 Software
      1. 36.5.1 FSI Registers to Driverlib Functions
      2. 36.5.2 FSI Examples
        1. 36.5.2.1 FSI Loopback:CPU Control - SINGLE_CORE
        2. 36.5.2.2 FSI data transfers upon CPU Timer event - SINGLE_CORE
    6. 36.6 FSI Registers
      1. 36.6.1 FSI Base Address Table
      2. 36.6.2 FSI_TX_REGS Registers
      3. 36.6.3 FSI_RX_REGS Registers
  39. 37Inter-Integrated Circuit Module (I2C)
    1. 37.1 Introduction
      1. 37.1.1 I2C Related Collateral
      2. 37.1.2 Features
      3. 37.1.3 Features Not Supported
      4. 37.1.4 Functional Overview
      5. 37.1.5 Clock Generation
      6. 37.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 37.1.6.1 Formula for the Controller Clock Period
    2. 37.2 Configuring Device Pins
    3. 37.3 I2C Module Operational Details
      1. 37.3.1  Input and Output Voltage Levels
      2. 37.3.2  Selecting Pullup Resistors
      3. 37.3.3  Data Validity
      4. 37.3.4  Operating Modes
      5. 37.3.5  I2C Module START and STOP Conditions
      6. 37.3.6  Non-repeat Mode versus Repeat Mode
      7. 37.3.7  Serial Data Formats
        1. 37.3.7.1 7-Bit Addressing Format
        2. 37.3.7.2 10-Bit Addressing Format
        3. 37.3.7.3 Free Data Format
        4. 37.3.7.4 Using a Repeated START Condition
      8. 37.3.8  Clock Synchronization
      9. 37.3.9  Clock Stretching
      10. 37.3.10 Arbitration
      11. 37.3.11 Digital Loopback Mode
      12. 37.3.12 NACK Bit Generation
    4. 37.4 Interrupt Requests Generated by the I2C Module
      1. 37.4.1 Basic I2C Interrupt Requests
      2. 37.4.2 I2C FIFO Interrupts
    5. 37.5 Resetting or Disabling the I2C Module
    6. 37.6 Software
      1. 37.6.1 I2C Registers to Driverlib Functions
      2. 37.6.2 I2C Examples
        1. 37.6.2.1 I2C Digital Loopback with FIFO Interrupts - SINGLE_CORE
        2. 37.6.2.2 I2C EEPROM - SINGLE_CORE
        3. 37.6.2.3 I2C Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        4. 37.6.2.4 I2C Extended Clock Stretching Controller TX - SINGLE_CORE
        5. 37.6.2.5 I2C Extended Clock Stretching Target RX - SINGLE_CORE
    7. 37.7 I2C Registers
      1. 37.7.1 I2C Base Address Table
      2. 37.7.2 I2C_REGS Registers
  40. 38Power Management Bus Module (PMBus)
    1. 38.1 Introduction
      1. 38.1.1 PMBUS Related Collateral
      2. 38.1.2 Features
      3. 38.1.3 Block Diagram
    2. 38.2 Configuring Device Pins
    3. 38.3 Target Mode Operation
      1. 38.3.1 Configuration
      2. 38.3.2 Message Handling
        1. 38.3.2.1  Quick Command
        2. 38.3.2.2  Send Byte
        3. 38.3.2.3  Receive Byte
        4. 38.3.2.4  Write Byte and Write Word
        5. 38.3.2.5  Read Byte and Read Word
        6. 38.3.2.6  Process Call
        7. 38.3.2.7  Block Write
        8. 38.3.2.8  Block Read
        9. 38.3.2.9  Block Write-Block Read Process Call
        10. 38.3.2.10 Alert Response
        11. 38.3.2.11 Extended Command
        12. 38.3.2.12 Group Command
    4. 38.4 Controller Mode Operation
      1. 38.4.1 Configuration
      2. 38.4.2 Message Handling
        1. 38.4.2.1  Quick Command
        2. 38.4.2.2  Send Byte
        3. 38.4.2.3  Receive Byte
        4. 38.4.2.4  Write Byte and Write Word
        5. 38.4.2.5  Read Byte and Read Word
        6. 38.4.2.6  Process Call
        7. 38.4.2.7  Block Write
        8. 38.4.2.8  Block Read
        9. 38.4.2.9  Block Write-Block Read Process Call
        10. 38.4.2.10 Alert Response
        11. 38.4.2.11 Extended Command
        12. 38.4.2.12 Group Command
    5. 38.5 Software
      1. 38.5.1 PMBUS Registers to Driverlib Functions
    6. 38.6 PMBUS Registers
      1. 38.6.1 PMBUS Base Address Table
      2. 38.6.2 PMBUS_REGS Registers
  41. 39Universal Asynchronous Receiver/Transmitter (UART)
    1. 39.1 Introduction
      1. 39.1.1 Features
      2. 39.1.2 UART Related Collateral
      3. 39.1.3 Block Diagram
    2. 39.2 Functional Description
      1. 39.2.1 Transmit and Receive Logic
      2. 39.2.2 Baud-Rate Generation
      3. 39.2.3 Data Transmission
      4. 39.2.4 Serial IR (SIR)
      5. 39.2.5 9-Bit UART Mode
      6. 39.2.6 FIFO Operation
      7. 39.2.7 Interrupts
      8. 39.2.8 Loopback Operation
      9. 39.2.9 RTDMA Operation
        1. 39.2.9.1 Receiving Data Using UART with RTDMA
        2. 39.2.9.2 Transmitting Data Using UART with RTDMA
    3. 39.3 Initialization and Configuration
    4. 39.4 Software
      1. 39.4.1 UART Registers to Driverlib Functions
      2. 39.4.2 UART Examples
        1. 39.4.2.1 UART Loopback - SINGLE_CORE
        2. 39.4.2.2 UART Loopback with Interrupt - SINGLE_CORE
        3. 39.4.2.3 UART Loopback with DMA - SINGLE_CORE
        4. 39.4.2.4 UART Echoback - SINGLE_CORE
    5. 39.5 UART Registers
      1. 39.5.1 UART Base Address Table
      2. 39.5.2 UART_REGS Registers
      3. 39.5.3 UART_REGS_WRITE Registers
  42. 40Local Interconnect Network (LIN)
    1. 40.1 LIN Overview
      1. 40.1.1 LIN Mode Features
      2. 40.1.2 SCI Mode Features
      3. 40.1.3 Block Diagram
    2. 40.2 Serial Communications Interface Module
      1. 40.2.1 SCI Communication Formats
        1. 40.2.1.1 SCI Frame Formats
        2. 40.2.1.2 SCI Asynchronous Timing Mode
        3. 40.2.1.3 SCI Baud Rate
          1. 40.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 40.2.1.4 SCI Multiprocessor Communication Modes
          1. 40.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 40.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 40.2.1.5 SCI Multibuffered Mode
      2. 40.2.2 SCI Interrupts
        1. 40.2.2.1 Transmit Interrupt
        2. 40.2.2.2 Receive Interrupt
        3. 40.2.2.3 WakeUp Interrupt
        4. 40.2.2.4 Error Interrupts
      3. 40.2.3 SCI RTDMA Interface
        1. 40.2.3.1 Receive RTDMA Requests
        2. 40.2.3.2 Transmit RTDMA Requests
      4. 40.2.4 SCI Configurations
        1. 40.2.4.1 Receiving Data
          1. 40.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 40.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 40.2.4.2 Transmitting Data
          1. 40.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 40.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 40.2.5 SCI Low-Power Mode
        1. 40.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 40.3 Local Interconnect Network Module
      1. 40.3.1 LIN Communication Formats
        1. 40.3.1.1  LIN Standards
        2. 40.3.1.2  Message Frame
          1. 40.3.1.2.1 Message Header
          2. 40.3.1.2.2 Response
        3. 40.3.1.3  Synchronizer
        4. 40.3.1.4  Baud Rate
          1. 40.3.1.4.1 Fractional Divider
          2. 40.3.1.4.2 Superfractional Divider
            1. 40.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 40.3.1.5  Header Generation
          1. 40.3.1.5.1 Event Triggered Frame Handling
          2. 40.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 40.3.1.6  Extended Frames Handling
        7. 40.3.1.7  Timeout Control
          1. 40.3.1.7.1 No-Response Error (NRE)
          2. 40.3.1.7.2 Bus Idle Detection
          3. 40.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 40.3.1.8  TXRX Error Detector (TED)
          1. 40.3.1.8.1 Bit Errors
          2. 40.3.1.8.2 Physical Bus Errors
          3. 40.3.1.8.3 ID Parity Errors
          4. 40.3.1.8.4 Checksum Errors
        9. 40.3.1.9  Message Filtering and Validation
        10. 40.3.1.10 Receive Buffers
        11. 40.3.1.11 Transmit Buffers
      2. 40.3.2 LIN Interrupts
      3. 40.3.3 Servicing LIN Interrupts
      4. 40.3.4 LIN RTDMA Interface
        1. 40.3.4.1 LIN Receive RTDMA Requests
        2. 40.3.4.2 LIN Transmit RTDMA Requests
      5. 40.3.5 LIN Configurations
        1. 40.3.5.1 Receiving Data
          1. 40.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 40.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 40.3.5.2 Transmitting Data
          1. 40.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 40.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 40.4 Low-Power Mode
      1. 40.4.1 Entering Sleep Mode
      2. 40.4.2 Wakeup
      3. 40.4.3 Wakeup Timeouts
    5. 40.5 Emulation Mode
    6. 40.6 Software
      1. 40.6.1 LIN Registers to Driverlib Functions
      2. 40.6.2 LIN Examples
        1. 40.6.2.1 LIN Internal Loopback with Interrupts - SINGLE_CORE
        2. 40.6.2.2 LIN SCI Mode Internal Loopback with Interrupts - SINGLE_CORE
        3. 40.6.2.3 LIN SCI MODE Internal Loopback with DMA - SINGLE_CORE
        4. 40.6.2.4 LIN Internal Loopback without interrupts (polled mode) - SINGLE_CORE
        5. 40.6.2.5 LIN SCI MODE (Single Buffer) Internal Loopback with DMA - SINGLE_CORE
    7. 40.7 LIN Registers
      1. 40.7.1 LIN Base Address Table
      2. 40.7.2 LIN_REGS Registers
  43. 41Serial Peripheral Interface (SPI)
    1. 41.1 Introduction
      1. 41.1.1 Features
      2. 41.1.2 Block Diagram
    2. 41.2 System-Level Integration
      1. 41.2.1 SPI Module Signals
      2. 41.2.2 Configuring Device Pins
        1. 41.2.2.1 GPIOs Required for High-Speed Mode
      3. 41.2.3 SPI Interrupts
      4. 41.2.4 RTDMA Support
    3. 41.3 SPI Operation
      1. 41.3.1  Introduction to Operation
      2. 41.3.2  Controller Mode
      3. 41.3.3  Peripheral Mode
      4. 41.3.4  Data Format
        1. 41.3.4.1 Transmission of Bit from SPIRXBUF
      5. 41.3.5  Baud Rate Selection
        1. 41.3.5.1 Baud Rate Determination
        2. 41.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
        3. 41.3.5.3 Baud Rate Calculation
      6. 41.3.6  SPI Clocking Schemes
      7. 41.3.7  SPI FIFO Description
      8. 41.3.8  SPI RTDMA Transfers
        1. 41.3.8.1 Transmitting Data Using SPI with RTDMA
        2. 41.3.8.2 Receiving Data Using SPI with RTDMA
      9. 41.3.9  SPI High-Speed Mode
      10. 41.3.10 SPI 3-Wire Mode Description
    4. 41.4 Programming Procedure
      1. 41.4.1 Initialization Upon Reset
      2. 41.4.2 Configuring the SPI
      3. 41.4.3 Configuring the SPI for High-Speed Mode
      4. 41.4.4 Data Transfer Example
      5. 41.4.5 SPI 3-Wire Mode Code Examples
        1. 41.4.5.1 3-Wire Controller Mode Transmit
        2.       1703
          1. 41.4.5.2.1 3-Wire Controller Mode Receive
        3.       1705
          1. 41.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       1707
          1. 41.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 41.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 41.5 Software
      1. 41.5.1 SPI Registers to Driverlib Functions
      2. 41.5.2 SPI Examples
        1. 41.5.2.1 SPI Digital Loopback - SINGLE_CORE
        2. 41.5.2.2 SPI Digital Loopback with FIFO Interrupts - SINGLE_CORE
        3. 41.5.2.3 SPI Digital External Loopback without FIFO Interrupts - SINGLE_CORE
        4. 41.5.2.4 SPI Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        5. 41.5.2.5 SPI Digital Loopback with DMA - SINGLE_CORE
    6. 41.6 SPI Registers
      1. 41.6.1 SPI Base Address Table
      2. 41.6.2 SPI_REGS Registers
  44. 42Single Edge Nibble Transmission (SENT)
    1. 42.1 Introduction
      1. 42.1.1 Features
      2. 42.1.2 SENT Related Collateral
    2. 42.2 Advanced Topologies: MTPG
      1. 42.2.1 MTPG Features
      2. 42.2.2 MTPG Description
      3. 42.2.3 Channel Triggers
      4. 42.2.4 Timeout
    3. 42.3 Protocol Description
      1. 42.3.1 Nibble Frame Format
      2. 42.3.2 CRC
      3. 42.3.3 Short Serial Message Format
      4. 42.3.4 Enhanced Serial Message Format
      5. 42.3.5 Enhanced Serial Message Format CRC
      6. 42.3.6 Receive Modes
    4. 42.4 RTDMA Trigger
    5. 42.5 Interrupts Configuration
    6. 42.6 Glitch Filter
    7. 42.7 Software
      1. 42.7.1 SENT Registers to Driverlib Functions
      2. 42.7.2 SENT Examples
        1. 42.7.2.1 SENT Single Sensor - SINGLE_CORE
    8. 42.8 SENT Registers
      1. 42.8.1 SENT Base Address Table
      2. 42.8.2 SENT_CFG Registers
      3. 42.8.3 SENT_MEM Registers
      4. 42.8.4 SENT_MTPG Registers
  45. 43â–º SECURITY PERIPHERALS
    1.     Technical Reference Manual Overview
  46. 44Security Modules
    1. 44.1 Hardware Security Module (HSM)
      1. 44.1.1 HSM Related Collateral
    2. 44.2 Cryptographic Accelerators
  47. 45Revision History

15.11.2 GPIO_CTRL_REGS Registers

Table 15-11 lists the memory-mapped registers for the GPIO_CTRL_REGS registers. All register offset addresses not listed in Table 15-11 should be considered as reserved locations and the register contents should not be modified.

Table 15-11 GPIO_CTRL_REGS Registers
OffsetAcronymRegister NameProtection
0hGPACTRLGPIO A Qualification Sampling Period Control (GPIO0 to 31)
4hGPAQSEL1GPIO A Qualifier Select 1 Register (GPIO0 to 15)
8hGPAQSEL2GPIO A Qualifier Select 2 Register (GPIO16 to 31)
ChGPAMUX1GPIO A Mux 1 Register (GPIO0 to 15)
10hGPAMUX2GPIO A Mux 2 Register (GPIO16 to 31)
18hGPAPUDGPIO A Pull Up Disable Register (GPIO0 to 31)
20hGPAINVGPIO A Input Polarity Invert Registers (GPIO0 to 31)
24hGPAODRGPIO A Open Drain Output Register (GPIO0 to GPIO31)
40hGPAGMUX1GPIO A Peripheral Group Mux (GPIO0 to 15)
44hGPAGMUX2GPIO A Peripheral Group Mux (GPIO16 to 31)
50hGPACSEL1GPIO A Core Select Register (GPIO0 to 7)
54hGPACSEL2GPIO A Core Select Register (GPIO8 to 15)
58hGPACSEL3GPIO A Core Select Register (GPIO16 to 23)
5ChGPACSEL4GPIO A Core Select Register (GPIO24 to 31)
78hGPALOCKGPIO A Lock Configuration Register (GPIO0 to 31)
7ChGPACRGPIO A Lock Commit Register (GPIO0 to 31)
80hGPBCTRLGPIO B Qualification Sampling Period Control (GPIO32 to 63)
84hGPBQSEL1GPIO B Qualifier Select 1 Register (GPIO32 to 47)
88hGPBQSEL2GPIO B Qualifier Select 2 Register (GPIO48 to 63)
8ChGPBMUX1GPIO B Mux 1 Register (GPIO32 to 47)
90hGPBMUX2GPIO B Mux 2 Register (GPIO48 to 63)
98hGPBPUDGPIO B Pull Up Disable Register (GPIO32 to 63)
A0hGPBINVGPIO B Input Polarity Invert Registers (GPIO32 to 63)
A4hGPBODRGPIO B Open Drain Output Register (GPIO32 to GPIO63)
C0hGPBGMUX1GPIO B Peripheral Group Mux (GPIO32 to 47)
C4hGPBGMUX2GPIO B Peripheral Group Mux (GPIO48 to 63)
D0hGPBCSEL1GPIO B Core Select Register (GPIO32 to 39)
D4hGPBCSEL2GPIO B Core Select Register (GPIO40 to 47)
D8hGPBCSEL3GPIO B Core Select Register (GPIO48 to 55)
DChGPBCSEL4GPIO B Core Select Register (GPIO56 to 63)
F8hGPBLOCKGPIO B Lock Configuration Register (GPIO32 to 63)
FChGPBCRGPIO B Lock Commit Register (GPIO32 to 63)
100hGPCCTRLGPIO C Qualification Sampling Period Control (GPIO64 to 95)
104hGPCQSEL1GPIO C Qualifier Select 1 Register (GPIO64 to 79)
108hGPCQSEL2GPIO C Qualifier Select 2 Register (GPIO80 to 95)
10ChGPCMUX1GPIO C Mux 1 Register (GPIO64 to 79)
110hGPCMUX2GPIO C Mux 2 Register (GPIO80 to 95)
118hGPCPUDGPIO C Pull Up Disable Register (GPIO64 to 95)
120hGPCINVGPIO C Input Polarity Invert Registers (GPIO64 to 95)
124hGPCODRGPIO C Open Drain Output Register (GPIO64 to GPIO95)
140hGPCGMUX1GPIO C Peripheral Group Mux (GPIO64 to 79)
144hGPCGMUX2GPIO C Peripheral Group Mux (GPIO80 to 95)
150hGPCCSEL1GPIO C Core Select Register (GPIO64 to 71)
154hGPCCSEL2GPIO C Core Select Register (GPIO72 to 79)
158hGPCCSEL3GPIO C Core Select Register (GPIO80 to 87)
15ChGPCCSEL4GPIO C Core Select Register (GPIO88 to 95)
178hGPCLOCKGPIO C Lock Configuration Register (GPIO64 to 95)
17ChGPCCRGPIO C Lock Commit Register (GPIO64 to 95)
180hGPDCTRLGPIO D Qualification Sampling Period Control (GPIO96 to 127)
184hGPDQSEL1GPIO D Qualifier Select 1 Register (GPIO96 to 111)
188hGPDQSEL2GPIO D Qualifier Select 2 Register (GPIO112 to 127)
18ChGPDMUX1GPIO D Mux 1 Register (GPIO96 to 111)
190hGPDMUX2GPIO D Mux 2 Register (GPIO112 to 127)
198hGPDPUDGPIO D Pull Up Disable Register (GPIO96 to 127)
1A0hGPDINVGPIO D Input Polarity Invert Registers (GPIO96 to 127)
1A4hGPDODRGPIO D Open Drain Output Register (GPIO96 to GPIO127)
1C0hGPDGMUX1GPIO D Peripheral Group Mux (GPIO96 to 111)
1C4hGPDGMUX2GPIO D Peripheral Group Mux (GPIO112 to 127)
1D0hGPDCSEL1GPIO D Core Select Register (GPIO96 to 103)
1D4hGPDCSEL2GPIO D Core Select Register (GPIO104 to 111)
1D8hGPDCSEL3GPIO D Core Select Register (GPIO112 to 119)
1DChGPDCSEL4GPIO D Core Select Register (GPIO120 to 127)
1F8hGPDLOCKGPIO D Lock Configuration Register (GPIO96 to 127)
1FChGPDCRGPIO D Lock Commit Register (GPIO96 to 127)
280hGPFCTRLGPIO F Qualification Sampling Period Control (GPIO160 to 191)
284hGPFQSEL1GPIO F Qualifier Select 1 Register (GPIO160 to 168)
288hGPFQSEL2GPIO F Qualifier Select 2 Register (GPIO176 to 191)
28ChGPFMUX1GPIO F Mux 1 Register (GPIO160 to 175)
290hGPFMUX2GPIO F Mux 2 Register (GPIO176 to 191)
298hGPFPUDGPIO F Pull Up Disable Register (GPIO160 to 191)
2A0hGPFINVGPIO F Input Polarity Invert Registers (GPIO160 to 191)
2A8hGPFAMSELGPIO F Analog Mode Select register (GPIO160 to GPIO191)
2C0hGPFGMUX1GPIO F Peripheral Group Mux (GPIO160 to 175)
2C4hGPFGMUX2GPIO F Peripheral Group Mux (GPIO176 to 191)
2D0hGPFCSEL1GPIO F Core Select Register (GPIO160 to 167)
2D4hGPFCSEL2GPIO F Core Select Register (GPIO168 to 175)
2D8hGPFCSEL3GPIO F Core Select Register (GPIO176 to 183)
2DChGPFCSEL4GPIO F Core Select Register (GPIO184 to 191)
2F8hGPFLOCKGPIO F Lock Configuration Register (GPIO160 to 191)
2FChGPFCRGPIO F Lock Commit Register (GPIO160 to 191)
300hGPGCTRLGPIO G Qualification Sampling Period Control (GPIO192 to 223)
304hGPGQSEL1GPIO G Qualifier Select 1 Register (GPIO192 to 207)
308hGPGQSEL2GPIO G Qualifier Select 2 Register (GPIO208 to 223)
30ChGPGMUX1GPIO G Mux 1 Register (GPIO192 to 207)
310hGPGMUX2GPIO G Mux 2 Register (GPIO208 to 223)
318hGPGPUDGPIO G Pull Up Disable Register (GPIO192 to 223)
320hGPGINVGPIO G Input Polarity Invert Registers (GPIO192 to 223)
324hGPGODRGPIO G Open Drain Output Register (GPIO192 to 223)
328hGPGAMSELGPIO G Analog Mode Select register (GPIO192 to 223)
340hGPGGMUX1GPIO G Peripheral Group Mux (GPIO192 to 207)
344hGPGGMUX2GPIO G Peripheral Group Mux (GPIO208 to 223)
350hGPGCSEL1GPIO G Core Select Register (GPIO192 to 199)
354hGPGCSEL2GPIO G Core Select Register (GPIO200 to 207)
358hGPGCSEL3GPIO G Core Select Register (GPIO208 to 215)
35ChGPGCSEL4GPIO G Core Select Register (GPIO216 to 223)
378hGPGLOCKGPIO G Lock Configuration Register (GPIO192 to 223)
37ChGPGCRGPIO G Lock Commit Register (GPIO192 to 223)
380hGPHCTRLGPIO H Qualification Sampling Period Control (GPIO224 to 255)
384hGPHQSEL1GPIO H Qualifier Select 1 Register (GPIO224 to 239)
388hGPHQSEL2GPIO H Qualifier Select 2 Register (GPIO240 to 255)
38ChGPHMUX1GPIO H Mux 1 Register (GPIO224 to 239)
390hGPHMUX2GPIO H Mux 2 Register (GPIO240 to 255)
398hGPHPUDGPIO H Pull Up Disable Register (GPIO224 to 255)
3A0hGPHINVGPIO H Input Polarity Invert Registers (GPIO224 to 255)
3A4hGPHODRGPIO H Open Drain Output Register (GPIO224 to GPIO255)
3A8hGPHAMSELGPIO H Analog Mode Select register (GPIO224 to GPIO255)
3C0hGPHGMUX1GPIO H Peripheral Group Mux (GPIO224 to 239)
3C4hGPHGMUX2GPIO H Peripheral Group Mux (GPIO240 to 255)
3D0hGPHCSEL1GPIO H Core Select Register (GPIO224 to 231)
3D4hGPHCSEL2GPIO H Core Select Register (GPIO232 to 239)
3D8hGPHCSEL3GPIO H Core Select Register (GPIO240 to 247)
3DChGPHCSEL4GPIO H Core Select Register (GPIO248 to 255)
3F8hGPHLOCKGPIO H Lock Configuration Register (GPIO224 to 255)
3FChGPHCRGPIO H Lock Commit Register (GPIO224 to 255)

Complex bit access types are encoded to fit into small table cells. Table 15-12 shows the codes that are used for access types in this section.

Table 15-12 GPIO_CTRL_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
WSonceW
Sonce		Write
Set once
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

15.11.2.1 GPACTRL Register (Offset = 0h) [Reset = 00000000h]

GPACTRL is shown in Figure 15-4 and described in Table 15-13.

Return to the Summary Table.

GPIO A Qualification Sampling Period Control (GPIO0 to 31)

Figure 15-4 GPACTRL Register
313029282726252423222120191817161514131211109876543210
QUALPRD3QUALPRD2QUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-13 GPACTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24QUALPRD3R/W0hQualification sampling period for GPIO24 to GPIO31:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

23-16QUALPRD2R/W0hQualification sampling period for GPIO16 to GPIO23:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15-8QUALPRD1R/W0hQualification sampling period for GPIO8 to GPIO15:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

7-0QUALPRD0R/W0hQualification sampling period for GPIO0 to GPIO7:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15.11.2.2 GPAQSEL1 Register (Offset = 4h) [Reset = 00000000h]

GPAQSEL1 is shown in Figure 15-5 and described in Table 15-14.

Return to the Summary Table.

GPIO A Qualifier Select 1 Register (GPIO0 to 15)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 15-5 GPAQSEL1 Register
31302928272625242322212019181716
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-14 GPAQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO15R/W0hSelect input qualification type for GPIO15:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO14R/W0hSelect input qualification type for GPIO14:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO13R/W0hSelect input qualification type for GPIO13:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO12R/W0hSelect input qualification type for GPIO12:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO11R/W0hSelect input qualification type for GPIO11:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO10R/W0hSelect input qualification type for GPIO10:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO9R/W0hSelect input qualification type for GPIO9:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO8R/W0hSelect input qualification type for GPIO8:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO7R/W0hSelect input qualification type for GPIO7:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO6R/W0hSelect input qualification type for GPIO6:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO5R/W0hSelect input qualification type for GPIO5:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO4R/W0hSelect input qualification type for GPIO4:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO3R/W0hSelect input qualification type for GPIO3:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO2R/W0hSelect input qualification type for GPIO2:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO1R/W0hSelect input qualification type for GPIO1:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO0R/W0hSelect input qualification type for GPIO0:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15.11.2.3 GPAQSEL2 Register (Offset = 8h) [Reset = 00000000h]

GPAQSEL2 is shown in Figure 15-6 and described in Table 15-15.

Return to the Summary Table.

GPIO A Qualifier Select 2 Register (GPIO16 to 31)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 15-6 GPAQSEL2 Register
31302928272625242322212019181716
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-15 GPAQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO31R/W0hSelect input qualification type for GPIO31:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO30R/W0hSelect input qualification type for GPIO30:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO29R/W0hSelect input qualification type for GPIO29:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO28R/W0hSelect input qualification type for GPIO28:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO27R/W0hSelect input qualification type for GPIO27:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO26R/W0hSelect input qualification type for GPIO26:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO25R/W0hSelect input qualification type for GPIO25:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO24R/W0hSelect input qualification type for GPIO24:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO23R/W0hSelect input qualification type for GPIO23:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO22R/W0hSelect input qualification type for GPIO22:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO21R/W0hSelect input qualification type for GPIO21:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO20R/W0hSelect input qualification type for GPIO20:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO19R/W0hSelect input qualification type for GPIO19:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO18R/W0hSelect input qualification type for GPIO18:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO17R/W0hSelect input qualification type for GPIO17:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO16R/W0hSelect input qualification type for GPIO16:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15.11.2.4 GPAMUX1 Register (Offset = Ch) [Reset = 00000000h]

GPAMUX1 is shown in Figure 15-7 and described in Table 15-16.

Return to the Summary Table.

GPIO A Mux 1 Register (GPIO0 to 15)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 15-7 GPAMUX1 Register
31302928272625242322212019181716
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-16 GPAMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO15R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO14R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO13R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO12R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO11R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO10R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO9R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO8R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO7R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO6R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO5R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO4R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO3R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO2R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO1R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO0R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.5 GPAMUX2 Register (Offset = 10h) [Reset = 00000000h]

GPAMUX2 is shown in Figure 15-8 and described in Table 15-17.

Return to the Summary Table.

GPIO A Mux 2 Register (GPIO16 to 31)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 15-8 GPAMUX2 Register
31302928272625242322212019181716
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-17 GPAMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO31R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO30R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO29R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO28R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO27R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO26R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO25R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO24R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO23R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO22R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO21R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO20R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO19R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO18R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO17R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO16R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.6 GPAPUD Register (Offset = 18h) [Reset = FFFFFFFFh]

GPAPUD is shown in Figure 15-9 and described in Table 15-18.

Return to the Summary Table.

GPIO A Pull Up Disable Register (GPIO0 to 31)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 15-9 GPAPUD Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 15-18 GPAPUD Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

30GPIO30R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

29GPIO29R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

28GPIO28R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

27GPIO27R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

26GPIO26R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

25GPIO25R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

24GPIO24R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

23GPIO23R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

22GPIO22R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

21GPIO21R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

20GPIO20R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

19GPIO19R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

18GPIO18R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

17GPIO17R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

16GPIO16R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15GPIO15R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14GPIO14R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

13GPIO13R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

12GPIO12R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

11GPIO11R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

10GPIO10R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

9GPIO9R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

8GPIO8R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

7GPIO7R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

6GPIO6R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

5GPIO5R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

4GPIO4R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

3GPIO3R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

2GPIO2R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

1GPIO1R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

0GPIO0R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15.11.2.7 GPAINV Register (Offset = 20h) [Reset = 00000000h]

GPAINV is shown in Figure 15-10 and described in Table 15-19.

Return to the Summary Table.

GPIO A Input Polarity Invert Registers (GPIO0 to 31)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 15-10 GPAINV Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-19 GPAINV Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hInput inversion control for this pin

Reset type: SYSRSn

30GPIO30R/W0hInput inversion control for this pin

Reset type: SYSRSn

29GPIO29R/W0hInput inversion control for this pin

Reset type: SYSRSn

28GPIO28R/W0hInput inversion control for this pin

Reset type: SYSRSn

27GPIO27R/W0hInput inversion control for this pin

Reset type: SYSRSn

26GPIO26R/W0hInput inversion control for this pin

Reset type: SYSRSn

25GPIO25R/W0hInput inversion control for this pin

Reset type: SYSRSn

24GPIO24R/W0hInput inversion control for this pin

Reset type: SYSRSn

23GPIO23R/W0hInput inversion control for this pin

Reset type: SYSRSn

22GPIO22R/W0hInput inversion control for this pin

Reset type: SYSRSn

21GPIO21R/W0hInput inversion control for this pin

Reset type: SYSRSn

20GPIO20R/W0hInput inversion control for this pin

Reset type: SYSRSn

19GPIO19R/W0hInput inversion control for this pin

Reset type: SYSRSn

18GPIO18R/W0hInput inversion control for this pin

Reset type: SYSRSn

17GPIO17R/W0hInput inversion control for this pin

Reset type: SYSRSn

16GPIO16R/W0hInput inversion control for this pin

Reset type: SYSRSn

15GPIO15R/W0hInput inversion control for this pin

Reset type: SYSRSn

14GPIO14R/W0hInput inversion control for this pin

Reset type: SYSRSn

13GPIO13R/W0hInput inversion control for this pin

Reset type: SYSRSn

12GPIO12R/W0hInput inversion control for this pin

Reset type: SYSRSn

11GPIO11R/W0hInput inversion control for this pin

Reset type: SYSRSn

10GPIO10R/W0hInput inversion control for this pin

Reset type: SYSRSn

9GPIO9R/W0hInput inversion control for this pin

Reset type: SYSRSn

8GPIO8R/W0hInput inversion control for this pin

Reset type: SYSRSn

7GPIO7R/W0hInput inversion control for this pin

Reset type: SYSRSn

6GPIO6R/W0hInput inversion control for this pin

Reset type: SYSRSn

5GPIO5R/W0hInput inversion control for this pin

Reset type: SYSRSn

4GPIO4R/W0hInput inversion control for this pin

Reset type: SYSRSn

3GPIO3R/W0hInput inversion control for this pin

Reset type: SYSRSn

2GPIO2R/W0hInput inversion control for this pin

Reset type: SYSRSn

1GPIO1R/W0hInput inversion control for this pin

Reset type: SYSRSn

0GPIO0R/W0hInput inversion control for this pin

Reset type: SYSRSn

15.11.2.8 GPAODR Register (Offset = 24h) [Reset = 00000000h]

GPAODR is shown in Figure 15-11 and described in Table 15-20.

Return to the Summary Table.

GPIO A Open Drain Output Register (GPIO0 to GPIO31)

Selects between normal and open-drain output for the GPIO pin.

0: Normal Output
1: Open Drain Output

Reading the register returns the current value of the register setting.

Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.

Figure 15-11 GPAODR Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-20 GPAODR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

30GPIO30R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

29GPIO29R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

28GPIO28R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

27GPIO27R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

26GPIO26R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

25GPIO25R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

24GPIO24R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

23GPIO23R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

22GPIO22R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

21GPIO21R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

20GPIO20R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

19GPIO19R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

18GPIO18R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

17GPIO17R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

16GPIO16R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

15GPIO15R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

14GPIO14R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

13GPIO13R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

12GPIO12R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

11GPIO11R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

10GPIO10R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

9GPIO9R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

8GPIO8R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

7GPIO7R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

6GPIO6R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

5GPIO5R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

4GPIO4R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

3GPIO3R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

2GPIO2R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

1GPIO1R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

0GPIO0R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

15.11.2.9 GPAGMUX1 Register (Offset = 40h) [Reset = 00000000h]

GPAGMUX1 is shown in Figure 15-12 and described in Table 15-21.

Return to the Summary Table.

GPIO A Peripheral Group Mux (GPIO0 to 15)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 15-12 GPAGMUX1 Register
31302928272625242322212019181716
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-21 GPAGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO15R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO14R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO13R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO12R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO11R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO10R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO9R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO8R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO7R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO6R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO5R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO4R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO3R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO2R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO1R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO0R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.10 GPAGMUX2 Register (Offset = 44h) [Reset = 00000000h]

GPAGMUX2 is shown in Figure 15-13 and described in Table 15-22.

Return to the Summary Table.

GPIO A Peripheral Group Mux (GPIO16 to 31)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 15-13 GPAGMUX2 Register
31302928272625242322212019181716
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-22 GPAGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO31R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO30R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO29R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO28R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO27R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO26R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO25R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO24R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO23R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO22R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO21R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO20R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO19R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO18R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO17R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO16R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.11 GPACSEL1 Register (Offset = 50h) [Reset = 00000000h]

GPACSEL1 is shown in Figure 15-14 and described in Table 15-23.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-14 GPACSEL1 Register
31302928272625242322212019181716
GPIO7GPIO6GPIO5GPIO4
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-23 GPACSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO7R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO6R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO5R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO4R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO3R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO2R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO1R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO0R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.12 GPACSEL2 Register (Offset = 54h) [Reset = 00000000h]

GPACSEL2 is shown in Figure 15-15 and described in Table 15-24.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-15 GPACSEL2 Register
31302928272625242322212019181716
GPIO15GPIO14GPIO13GPIO12
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-24 GPACSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO15R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO14R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO13R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO12R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO11R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO10R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO9R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO8R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.13 GPACSEL3 Register (Offset = 58h) [Reset = 00000000h]

GPACSEL3 is shown in Figure 15-16 and described in Table 15-25.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-16 GPACSEL3 Register
31302928272625242322212019181716
GPIO23GPIO22GPIO21GPIO20
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-25 GPACSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO23R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO22R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO21R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO20R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO19R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO18R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO17R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO16R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.14 GPACSEL4 Register (Offset = 5Ch) [Reset = 00000000h]

GPACSEL4 is shown in Figure 15-17 and described in Table 15-26.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-17 GPACSEL4 Register
31302928272625242322212019181716
GPIO31GPIO30GPIO29GPIO28
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-26 GPACSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO31R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO30R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO29R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO28R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO27R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO26R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO25R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO24R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.15 GPALOCK Register (Offset = 78h) [Reset = 00000000h]

GPALOCK is shown in Figure 15-18 and described in Table 15-27.

Return to the Summary Table.

GPIO A Lock Configuration Register (GPIO0 to 31)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 15-18 GPALOCK Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-27 GPALOCK Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

30GPIO30R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

29GPIO29R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

28GPIO28R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

27GPIO27R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

26GPIO26R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

25GPIO25R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

24GPIO24R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

23GPIO23R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

22GPIO22R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

21GPIO21R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

20GPIO20R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

19GPIO19R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

18GPIO18R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

17GPIO17R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

16GPIO16R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15GPIO15R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14GPIO14R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

13GPIO13R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

12GPIO12R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

11GPIO11R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

10GPIO10R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

9GPIO9R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

8GPIO8R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

7GPIO7R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

6GPIO6R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

5GPIO5R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

4GPIO4R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

3GPIO3R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

2GPIO2R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

1GPIO1R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

0GPIO0R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15.11.2.16 GPACR Register (Offset = 7Ch) [Reset = 00000000h]

GPACR is shown in Figure 15-19 and described in Table 15-28.

Return to the Summary Table.

GPIO A Lock Commit Register (GPIO0 to 31)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 15-19 GPACR Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 15-28 GPACR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

30GPIO30R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

29GPIO29R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

28GPIO28R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

27GPIO27R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

26GPIO26R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

25GPIO25R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

24GPIO24R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

23GPIO23R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

22GPIO22R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

21GPIO21R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

20GPIO20R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

19GPIO19R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

18GPIO18R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

17GPIO17R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

16GPIO16R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15GPIO15R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14GPIO14R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

13GPIO13R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

12GPIO12R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

11GPIO11R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

10GPIO10R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

9GPIO9R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

8GPIO8R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

7GPIO7R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

6GPIO6R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

5GPIO5R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

4GPIO4R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

3GPIO3R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

2GPIO2R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

1GPIO1R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

0GPIO0R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15.11.2.17 GPBCTRL Register (Offset = 80h) [Reset = 00000000h]

GPBCTRL is shown in Figure 15-20 and described in Table 15-29.

Return to the Summary Table.

GPIO B Qualification Sampling Period Control (GPIO32 to 63)

Figure 15-20 GPBCTRL Register
313029282726252423222120191817161514131211109876543210
QUALPRD3QUALPRD2QUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-29 GPBCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24QUALPRD3R/W0hQualification sampling period for GPIO56 to GPIO63:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

23-16QUALPRD2R/W0hQualification sampling period for GPIO48 to GPIO55:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15-8QUALPRD1R/W0hQualification sampling period for GPIO40 to GPIO47:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

7-0QUALPRD0R/W0hQualification sampling period for GPIO32 to GPIO39:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15.11.2.18 GPBQSEL1 Register (Offset = 84h) [Reset = 00000000h]

GPBQSEL1 is shown in Figure 15-21 and described in Table 15-30.

Return to the Summary Table.

GPIO B Qualifier Select 1 Register (GPIO32 to 47)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 15-21 GPBQSEL1 Register
31302928272625242322212019181716
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-30 GPBQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO47R/W0hSelect input qualification type for GPIO47:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO46R/W0hSelect input qualification type for GPIO46:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO45R/W0hSelect input qualification type for GPIO45:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO44R/W0hSelect input qualification type for GPIO44:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO43R/W0hSelect input qualification type for GPIO43:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO42R/W0hSelect input qualification type for GPIO42:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO41R/W0hSelect input qualification type for GPIO41:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO40R/W0hSelect input qualification type for GPIO40:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO39R/W0hSelect input qualification type for GPIO39:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO38R/W0hSelect input qualification type for GPIO38:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO37R/W0hSelect input qualification type for GPIO37:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO36R/W0hSelect input qualification type for GPIO36:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO35R/W0hSelect input qualification type for GPIO35:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO34R/W0hSelect input qualification type for GPIO34:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO33R/W0hSelect input qualification type for GPIO33:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO32R/W0hSelect input qualification type for GPIO32:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15.11.2.19 GPBQSEL2 Register (Offset = 88h) [Reset = 00000000h]

GPBQSEL2 is shown in Figure 15-22 and described in Table 15-31.

Return to the Summary Table.

GPIO B Qualifier Select 2 Register (GPIO48 to 63)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 15-22 GPBQSEL2 Register
31302928272625242322212019181716
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-31 GPBQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO63R/W0hSelect input qualification type for GPIO63:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO62R/W0hSelect input qualification type for GPIO62:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO61R/W0hSelect input qualification type for GPIO61:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO60R/W0hSelect input qualification type for GPIO60:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO59R/W0hSelect input qualification type for GPIO59:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO58R/W0hSelect input qualification type for GPIO58:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO57R/W0hSelect input qualification type for GPIO57:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO56R/W0hSelect input qualification type for GPIO56:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO55R/W0hSelect input qualification type for GPIO55:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO54R/W0hSelect input qualification type for GPIO54:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO53R/W0hSelect input qualification type for GPIO53:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO52R/W0hSelect input qualification type for GPIO52:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO51R/W0hSelect input qualification type for GPIO51:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO50R/W0hSelect input qualification type for GPIO50:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO49R/W0hSelect input qualification type for GPIO49:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO48R/W0hSelect input qualification type for GPIO48:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15.11.2.20 GPBMUX1 Register (Offset = 8Ch) [Reset = 00000000h]

GPBMUX1 is shown in Figure 15-23 and described in Table 15-32.

Return to the Summary Table.

GPIO B Mux 1 Register (GPIO32 to 47)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 15-23 GPBMUX1 Register
31302928272625242322212019181716
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-32 GPBMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO47R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO46R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO45R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO44R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO43R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO42R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO41R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO40R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO39R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO38R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO37R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO36R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO35R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO34R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO33R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO32R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.21 GPBMUX2 Register (Offset = 90h) [Reset = 00000000h]

GPBMUX2 is shown in Figure 15-24 and described in Table 15-33.

Return to the Summary Table.

GPIO B Mux 2 Register (GPIO48 to 63)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 15-24 GPBMUX2 Register
31302928272625242322212019181716
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-33 GPBMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO63R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO62R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO61R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO60R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO59R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO58R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO57R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO56R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO55R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO54R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO53R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO52R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO51R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO50R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO49R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO48R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.22 GPBPUD Register (Offset = 98h) [Reset = FFFFFFFFh]

GPBPUD is shown in Figure 15-25 and described in Table 15-34.

Return to the Summary Table.

GPIO B Pull Up Disable Register (GPIO32 to 63)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 15-25 GPBPUD Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 15-34 GPBPUD Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

30GPIO62R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

29GPIO61R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

28GPIO60R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

27GPIO59R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

26GPIO58R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

25GPIO57R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

24GPIO56R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

23GPIO55R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

22GPIO54R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

21GPIO53R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

20GPIO52R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

19GPIO51R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

18GPIO50R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

17GPIO49R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

16GPIO48R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15GPIO47R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14GPIO46R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

13GPIO45R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

12GPIO44R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

11GPIO43R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

10GPIO42R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

9GPIO41R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

8GPIO40R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

7GPIO39R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

6GPIO38R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

5GPIO37R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

4GPIO36R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

3GPIO35R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

2GPIO34R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

1GPIO33R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

0GPIO32R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15.11.2.23 GPBINV Register (Offset = A0h) [Reset = 00000000h]

GPBINV is shown in Figure 15-26 and described in Table 15-35.

Return to the Summary Table.

GPIO B Input Polarity Invert Registers (GPIO32 to 63)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 15-26 GPBINV Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-35 GPBINV Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/W0hInput inversion control for this pin

Reset type: SYSRSn

30GPIO62R/W0hInput inversion control for this pin

Reset type: SYSRSn

29GPIO61R/W0hInput inversion control for this pin

Reset type: SYSRSn

28GPIO60R/W0hInput inversion control for this pin

Reset type: SYSRSn

27GPIO59R/W0hInput inversion control for this pin

Reset type: SYSRSn

26GPIO58R/W0hInput inversion control for this pin

Reset type: SYSRSn

25GPIO57R/W0hInput inversion control for this pin

Reset type: SYSRSn

24GPIO56R/W0hInput inversion control for this pin

Reset type: SYSRSn

23GPIO55R/W0hInput inversion control for this pin

Reset type: SYSRSn

22GPIO54R/W0hInput inversion control for this pin

Reset type: SYSRSn

21GPIO53R/W0hInput inversion control for this pin

Reset type: SYSRSn

20GPIO52R/W0hInput inversion control for this pin

Reset type: SYSRSn

19GPIO51R/W0hInput inversion control for this pin

Reset type: SYSRSn

18GPIO50R/W0hInput inversion control for this pin

Reset type: SYSRSn

17GPIO49R/W0hInput inversion control for this pin

Reset type: SYSRSn

16GPIO48R/W0hInput inversion control for this pin

Reset type: SYSRSn

15GPIO47R/W0hInput inversion control for this pin

Reset type: SYSRSn

14GPIO46R/W0hInput inversion control for this pin

Reset type: SYSRSn

13GPIO45R/W0hInput inversion control for this pin

Reset type: SYSRSn

12GPIO44R/W0hInput inversion control for this pin

Reset type: SYSRSn

11GPIO43R/W0hInput inversion control for this pin

Reset type: SYSRSn

10GPIO42R/W0hInput inversion control for this pin

Reset type: SYSRSn

9GPIO41R/W0hInput inversion control for this pin

Reset type: SYSRSn

8GPIO40R/W0hInput inversion control for this pin

Reset type: SYSRSn

7GPIO39R/W0hInput inversion control for this pin

Reset type: SYSRSn

6GPIO38R/W0hInput inversion control for this pin

Reset type: SYSRSn

5GPIO37R/W0hInput inversion control for this pin

Reset type: SYSRSn

4GPIO36R/W0hInput inversion control for this pin

Reset type: SYSRSn

3GPIO35R/W0hInput inversion control for this pin

Reset type: SYSRSn

2GPIO34R/W0hInput inversion control for this pin

Reset type: SYSRSn

1GPIO33R/W0hInput inversion control for this pin

Reset type: SYSRSn

0GPIO32R/W0hInput inversion control for this pin

Reset type: SYSRSn

15.11.2.24 GPBODR Register (Offset = A4h) [Reset = 00000000h]

GPBODR is shown in Figure 15-27 and described in Table 15-36.

Return to the Summary Table.

GPIO B Open Drain Output Register (GPIO32 to GPIO63)

Selects between normal and open-drain output for the GPIO pin.

0: Normal Output
1: Open Drain Output

Reading the register returns the current value of the register setting.

Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.

Figure 15-27 GPBODR Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-36 GPBODR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

30GPIO62R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

29GPIO61R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

28GPIO60R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

27GPIO59R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

26GPIO58R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

25GPIO57R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

24GPIO56R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

23GPIO55R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

22GPIO54R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

21GPIO53R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

20GPIO52R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

19GPIO51R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

18GPIO50R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

17GPIO49R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

16GPIO48R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

15GPIO47R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

14GPIO46R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

13GPIO45R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

12GPIO44R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

11GPIO43R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

10GPIO42R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

9GPIO41R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

8GPIO40R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

7GPIO39R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

6GPIO38R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

5GPIO37R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

4GPIO36R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

3GPIO35R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

2GPIO34R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

1GPIO33R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

0GPIO32R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

15.11.2.25 GPBGMUX1 Register (Offset = C0h) [Reset = 00000000h]

GPBGMUX1 is shown in Figure 15-28 and described in Table 15-37.

Return to the Summary Table.

GPIO B Peripheral Group Mux (GPIO32 to 47)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 15-28 GPBGMUX1 Register
31302928272625242322212019181716
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-37 GPBGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO47R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO46R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO45R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO44R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO43R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO42R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO41R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO40R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO39R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO38R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO37R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO36R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO35R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO34R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO33R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO32R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.26 GPBGMUX2 Register (Offset = C4h) [Reset = 00000000h]

GPBGMUX2 is shown in Figure 15-29 and described in Table 15-38.

Return to the Summary Table.

GPIO B Peripheral Group Mux (GPIO48 to 63)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 15-29 GPBGMUX2 Register
31302928272625242322212019181716
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-38 GPBGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO63R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO62R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO61R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO60R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO59R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO58R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO57R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO56R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO55R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO54R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO53R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO52R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO51R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO50R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO49R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO48R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.27 GPBCSEL1 Register (Offset = D0h) [Reset = 00000000h]

GPBCSEL1 is shown in Figure 15-30 and described in Table 15-39.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-30 GPBCSEL1 Register
31302928272625242322212019181716
GPIO39GPIO38GPIO37GPIO36
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-39 GPBCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO39R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO38R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO37R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO36R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO35R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO34R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO33R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO32R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.28 GPBCSEL2 Register (Offset = D4h) [Reset = 00000000h]

GPBCSEL2 is shown in Figure 15-31 and described in Table 15-40.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-31 GPBCSEL2 Register
31302928272625242322212019181716
GPIO47GPIO46GPIO45GPIO44
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-40 GPBCSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO47R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO46R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO45R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO44R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO43R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO42R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO41R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO40R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.29 GPBCSEL3 Register (Offset = D8h) [Reset = 00000000h]

GPBCSEL3 is shown in Figure 15-32 and described in Table 15-41.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-32 GPBCSEL3 Register
31302928272625242322212019181716
GPIO55GPIO54GPIO53GPIO52
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-41 GPBCSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO55R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO54R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO53R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO52R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO51R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO50R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO49R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO48R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.30 GPBCSEL4 Register (Offset = DCh) [Reset = 00000000h]

GPBCSEL4 is shown in Figure 15-33 and described in Table 15-42.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-33 GPBCSEL4 Register
31302928272625242322212019181716
GPIO63GPIO62GPIO61GPIO60
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-42 GPBCSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO63R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO62R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO61R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO60R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO59R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO58R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO57R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO56R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.31 GPBLOCK Register (Offset = F8h) [Reset = 00000000h]

GPBLOCK is shown in Figure 15-34 and described in Table 15-43.

Return to the Summary Table.

GPIO B Lock Configuration Register (GPIO32 to 63)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 15-34 GPBLOCK Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-43 GPBLOCK Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

30GPIO62R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

29GPIO61R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

28GPIO60R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

27GPIO59R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

26GPIO58R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

25GPIO57R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

24GPIO56R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

23GPIO55R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

22GPIO54R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

21GPIO53R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

20GPIO52R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

19GPIO51R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

18GPIO50R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

17GPIO49R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

16GPIO48R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15GPIO47R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14GPIO46R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

13GPIO45R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

12GPIO44R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

11GPIO43R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

10GPIO42R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

9GPIO41R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

8GPIO40R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

7GPIO39R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

6GPIO38R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

5GPIO37R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

4GPIO36R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

3GPIO35R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

2GPIO34R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

1GPIO33R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

0GPIO32R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15.11.2.32 GPBCR Register (Offset = FCh) [Reset = 00000000h]

GPBCR is shown in Figure 15-35 and described in Table 15-44.

Return to the Summary Table.

GPIO B Lock Commit Register (GPIO32 to 63)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 15-35 GPBCR Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 15-44 GPBCR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

30GPIO62R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

29GPIO61R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

28GPIO60R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

27GPIO59R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

26GPIO58R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

25GPIO57R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

24GPIO56R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

23GPIO55R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

22GPIO54R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

21GPIO53R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

20GPIO52R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

19GPIO51R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

18GPIO50R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

17GPIO49R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

16GPIO48R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15GPIO47R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14GPIO46R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

13GPIO45R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

12GPIO44R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

11GPIO43R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

10GPIO42R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

9GPIO41R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

8GPIO40R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

7GPIO39R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

6GPIO38R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

5GPIO37R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

4GPIO36R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

3GPIO35R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

2GPIO34R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

1GPIO33R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

0GPIO32R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15.11.2.33 GPCCTRL Register (Offset = 100h) [Reset = 00000000h]

GPCCTRL is shown in Figure 15-36 and described in Table 15-45.

Return to the Summary Table.

GPIO C Qualification Sampling Period Control (GPIO64 to 95)

Figure 15-36 GPCCTRL Register
313029282726252423222120191817161514131211109876543210
QUALPRD3QUALPRD2QUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-45 GPCCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24QUALPRD3R/W0hQualification sampling period for GPIO88 to GPIO95:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

23-16QUALPRD2R/W0hQualification sampling period for GPIO80 to GPIO87:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15-8QUALPRD1R/W0hQualification sampling period for GPIO72 to GPIO79:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

7-0QUALPRD0R/W0hQualification sampling period for GPIO64 to GPIO71:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15.11.2.34 GPCQSEL1 Register (Offset = 104h) [Reset = 00000000h]

GPCQSEL1 is shown in Figure 15-37 and described in Table 15-46.

Return to the Summary Table.

GPIO C Qualifier Select 1 Register (GPIO64 to 79)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 15-37 GPCQSEL1 Register
31302928272625242322212019181716
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-46 GPCQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO79R/W0hSelect input qualification type for GPIO79:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO78R/W0hSelect input qualification type for GPIO78:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO77R/W0hSelect input qualification type for GPIO77:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO76R/W0hSelect input qualification type for GPIO76:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO75R/W0hSelect input qualification type for GPIO75:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO74R/W0hSelect input qualification type for GPIO74:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO73R/W0hSelect input qualification type for GPIO73:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO72R/W0hSelect input qualification type for GPIO72:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO71R/W0hSelect input qualification type for GPIO71:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO70R/W0hSelect input qualification type for GPIO70:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO69R/W0hSelect input qualification type for GPIO69:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO68R/W0hSelect input qualification type for GPIO68:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO67R/W0hSelect input qualification type for GPIO67:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO66R/W0hSelect input qualification type for GPIO66:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO65R/W0hSelect input qualification type for GPIO65:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO64R/W0hSelect input qualification type for GPIO64:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15.11.2.35 GPCQSEL2 Register (Offset = 108h) [Reset = 00000000h]

GPCQSEL2 is shown in Figure 15-38 and described in Table 15-47.

Return to the Summary Table.

GPIO C Qualifier Select 2 Register (GPIO80 to 95)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 15-38 GPCQSEL2 Register
31302928272625242322212019181716
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-47 GPCQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO95R/W0hSelect input qualification type for GPIO95:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO94R/W0hSelect input qualification type for GPIO94:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO93R/W0hSelect input qualification type for GPIO93:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO92R/W0hSelect input qualification type for GPIO92:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO91R/W0hSelect input qualification type for GPIO91:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO90R/W0hSelect input qualification type for GPIO90:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO89R/W0hSelect input qualification type for GPIO89:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO88R/W0hSelect input qualification type for GPIO88:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO87R/W0hSelect input qualification type for GPIO87:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO86R/W0hSelect input qualification type for GPIO86:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO85R/W0hSelect input qualification type for GPIO85:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO84R/W0hSelect input qualification type for GPIO84:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO83R/W0hSelect input qualification type for GPIO83:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO82R/W0hSelect input qualification type for GPIO82:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO81R/W0hSelect input qualification type for GPIO81:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO80R/W0hSelect input qualification type for GPIO80:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15.11.2.36 GPCMUX1 Register (Offset = 10Ch) [Reset = 00000000h]

GPCMUX1 is shown in Figure 15-39 and described in Table 15-48.

Return to the Summary Table.

GPIO C Mux 1 Register (GPIO64 to 79)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 15-39 GPCMUX1 Register
31302928272625242322212019181716
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-48 GPCMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO79R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO78R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO77R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO76R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO75R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO74R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO73R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO72R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO71R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO70R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO69R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO68R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO67R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO66R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO65R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO64R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.37 GPCMUX2 Register (Offset = 110h) [Reset = 00000000h]

GPCMUX2 is shown in Figure 15-40 and described in Table 15-49.

Return to the Summary Table.

GPIO C Mux 2 Register (GPIO80 to 95)
Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 15-40 GPCMUX2 Register
31302928272625242322212019181716
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-49 GPCMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO95R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO94R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO93R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO92R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO91R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO90R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO89R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO88R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO87R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO86R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO85R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO84R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO83R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO82R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO81R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO80R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.38 GPCPUD Register (Offset = 118h) [Reset = FFFFFFFFh]

GPCPUD is shown in Figure 15-41 and described in Table 15-50.

Return to the Summary Table.

GPIO C Pull Up Disable Register (GPIO64 to 95)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 15-41 GPCPUD Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 15-50 GPCPUD Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

30GPIO94R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

29GPIO93R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

28GPIO92R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

27GPIO91R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

26GPIO90R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

25GPIO89R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

24GPIO88R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

23GPIO87R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

22GPIO86R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

21GPIO85R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

20GPIO84R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

19GPIO83R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

18GPIO82R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

17GPIO81R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

16GPIO80R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15GPIO79R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14GPIO78R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

13GPIO77R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

12GPIO76R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

11GPIO75R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

10GPIO74R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

9GPIO73R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

8GPIO72R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

7GPIO71R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

6GPIO70R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

5GPIO69R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

4GPIO68R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

3GPIO67R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

2GPIO66R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

1GPIO65R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

0GPIO64R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15.11.2.39 GPCINV Register (Offset = 120h) [Reset = 00000000h]

GPCINV is shown in Figure 15-42 and described in Table 15-51.

Return to the Summary Table.

GPIO C Input Polarity Invert Registers (GPIO64 to 95)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 15-42 GPCINV Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-51 GPCINV Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/W0hInput inversion control for this pin

Reset type: SYSRSn

30GPIO94R/W0hInput inversion control for this pin

Reset type: SYSRSn

29GPIO93R/W0hInput inversion control for this pin

Reset type: SYSRSn

28GPIO92R/W0hInput inversion control for this pin

Reset type: SYSRSn

27GPIO91R/W0hInput inversion control for this pin

Reset type: SYSRSn

26GPIO90R/W0hInput inversion control for this pin

Reset type: SYSRSn

25GPIO89R/W0hInput inversion control for this pin

Reset type: SYSRSn

24GPIO88R/W0hInput inversion control for this pin

Reset type: SYSRSn

23GPIO87R/W0hInput inversion control for this pin

Reset type: SYSRSn

22GPIO86R/W0hInput inversion control for this pin

Reset type: SYSRSn

21GPIO85R/W0hInput inversion control for this pin

Reset type: SYSRSn

20GPIO84R/W0hInput inversion control for this pin

Reset type: SYSRSn

19GPIO83R/W0hInput inversion control for this pin

Reset type: SYSRSn

18GPIO82R/W0hInput inversion control for this pin

Reset type: SYSRSn

17GPIO81R/W0hInput inversion control for this pin

Reset type: SYSRSn

16GPIO80R/W0hInput inversion control for this pin

Reset type: SYSRSn

15GPIO79R/W0hInput inversion control for this pin

Reset type: SYSRSn

14GPIO78R/W0hInput inversion control for this pin

Reset type: SYSRSn

13GPIO77R/W0hInput inversion control for this pin

Reset type: SYSRSn

12GPIO76R/W0hInput inversion control for this pin

Reset type: SYSRSn

11GPIO75R/W0hInput inversion control for this pin

Reset type: SYSRSn

10GPIO74R/W0hInput inversion control for this pin

Reset type: SYSRSn

9GPIO73R/W0hInput inversion control for this pin

Reset type: SYSRSn

8GPIO72R/W0hInput inversion control for this pin

Reset type: SYSRSn

7GPIO71R/W0hInput inversion control for this pin

Reset type: SYSRSn

6GPIO70R/W0hInput inversion control for this pin

Reset type: SYSRSn

5GPIO69R/W0hInput inversion control for this pin

Reset type: SYSRSn

4GPIO68R/W0hInput inversion control for this pin

Reset type: SYSRSn

3GPIO67R/W0hInput inversion control for this pin

Reset type: SYSRSn

2GPIO66R/W0hInput inversion control for this pin

Reset type: SYSRSn

1GPIO65R/W0hInput inversion control for this pin

Reset type: SYSRSn

0GPIO64R/W0hInput inversion control for this pin

Reset type: SYSRSn

15.11.2.40 GPCODR Register (Offset = 124h) [Reset = 00000000h]

GPCODR is shown in Figure 15-43 and described in Table 15-52.

Return to the Summary Table.

GPIO C Open Drain Output Register (GPIO64 to GPIO95)

Selects between normal and open-drain output for the GPIO pin.

0: Normal Output
1: Open Drain Output

Reading the register returns the current value of the register setting.

Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.

Figure 15-43 GPCODR Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-52 GPCODR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

30GPIO94R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

29GPIO93R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

28GPIO92R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

27GPIO91R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

26GPIO90R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

25GPIO89R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

24GPIO88R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

23GPIO87R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

22GPIO86R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

21GPIO85R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

20GPIO84R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

19GPIO83R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

18GPIO82R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

17GPIO81R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

16GPIO80R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

15GPIO79R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

14GPIO78R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

13GPIO77R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

12GPIO76R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

11GPIO75R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

10GPIO74R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

9GPIO73R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

8GPIO72R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

7GPIO71R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

6GPIO70R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

5GPIO69R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

4GPIO68R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

3GPIO67R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

2GPIO66R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

1GPIO65R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

0GPIO64R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

15.11.2.41 GPCGMUX1 Register (Offset = 140h) [Reset = 00000000h]

GPCGMUX1 is shown in Figure 15-44 and described in Table 15-53.

Return to the Summary Table.

GPIO C Peripheral Group Mux (GPIO64 to 79)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 15-44 GPCGMUX1 Register
31302928272625242322212019181716
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-53 GPCGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO79R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO78R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO77R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO76R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO75R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO74R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO73R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO72R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO71R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO70R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO69R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO68R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO67R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO66R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO65R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO64R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.42 GPCGMUX2 Register (Offset = 144h) [Reset = 00000000h]

GPCGMUX2 is shown in Figure 15-45 and described in Table 15-54.

Return to the Summary Table.

GPIO C Peripheral Group Mux (GPIO80 to 95)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 15-45 GPCGMUX2 Register
31302928272625242322212019181716
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-54 GPCGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO95R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO94R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO93R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO92R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO91R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO90R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO89R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO88R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO87R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO86R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO85R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO84R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO83R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO82R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO81R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO80R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.43 GPCCSEL1 Register (Offset = 150h) [Reset = 00000000h]

GPCCSEL1 is shown in Figure 15-46 and described in Table 15-55.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-46 GPCCSEL1 Register
31302928272625242322212019181716
GPIO71GPIO70GPIO69GPIO68
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-55 GPCCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO71R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO70R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO69R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO68R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO67R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO66R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO65R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO64R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.44 GPCCSEL2 Register (Offset = 154h) [Reset = 00000000h]

GPCCSEL2 is shown in Figure 15-47 and described in Table 15-56.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-47 GPCCSEL2 Register
31302928272625242322212019181716
GPIO79GPIO78GPIO77GPIO76
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-56 GPCCSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO79R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO78R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO77R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO76R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO75R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO74R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO73R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO72R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.45 GPCCSEL3 Register (Offset = 158h) [Reset = 00000000h]

GPCCSEL3 is shown in Figure 15-48 and described in Table 15-57.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-48 GPCCSEL3 Register
31302928272625242322212019181716
GPIO87GPIO86GPIO85GPIO84
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-57 GPCCSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO87R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO86R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO85R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO84R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO83R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO82R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO81R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO80R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.46 GPCCSEL4 Register (Offset = 15Ch) [Reset = 00000000h]

GPCCSEL4 is shown in Figure 15-49 and described in Table 15-58.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-49 GPCCSEL4 Register
31302928272625242322212019181716
GPIO95GPIO94GPIO93GPIO92
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-58 GPCCSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO95R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO94R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO93R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO92R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO91R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO90R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO89R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO88R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.47 GPCLOCK Register (Offset = 178h) [Reset = 00000000h]

GPCLOCK is shown in Figure 15-50 and described in Table 15-59.

Return to the Summary Table.

GPIO C Lock Configuration Register (GPIO64 to 95)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 15-50 GPCLOCK Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-59 GPCLOCK Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

30GPIO94R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

29GPIO93R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

28GPIO92R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

27GPIO91R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

26GPIO90R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

25GPIO89R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

24GPIO88R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

23GPIO87R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

22GPIO86R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

21GPIO85R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

20GPIO84R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

19GPIO83R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

18GPIO82R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

17GPIO81R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

16GPIO80R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15GPIO79R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14GPIO78R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

13GPIO77R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

12GPIO76R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

11GPIO75R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

10GPIO74R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

9GPIO73R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

8GPIO72R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

7GPIO71R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

6GPIO70R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

5GPIO69R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

4GPIO68R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

3GPIO67R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

2GPIO66R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

1GPIO65R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

0GPIO64R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15.11.2.48 GPCCR Register (Offset = 17Ch) [Reset = 00000000h]

GPCCR is shown in Figure 15-51 and described in Table 15-60.

Return to the Summary Table.

GPIO C Lock Commit Register (GPIO64 to 95)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 15-51 GPCCR Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 15-60 GPCCR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

30GPIO94R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

29GPIO93R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

28GPIO92R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

27GPIO91R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

26GPIO90R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

25GPIO89R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

24GPIO88R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

23GPIO87R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

22GPIO86R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

21GPIO85R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

20GPIO84R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

19GPIO83R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

18GPIO82R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

17GPIO81R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

16GPIO80R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15GPIO79R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14GPIO78R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

13GPIO77R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

12GPIO76R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

11GPIO75R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

10GPIO74R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

9GPIO73R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

8GPIO72R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

7GPIO71R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

6GPIO70R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

5GPIO69R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

4GPIO68R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

3GPIO67R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

2GPIO66R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

1GPIO65R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

0GPIO64R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15.11.2.49 GPDCTRL Register (Offset = 180h) [Reset = 00000000h]

GPDCTRL is shown in Figure 15-52 and described in Table 15-61.

Return to the Summary Table.

GPIO D Qualification Sampling Period Control (GPIO96 to 127)

Figure 15-52 GPDCTRL Register
313029282726252423222120191817161514131211109876543210
QUALPRD3RESERVEDQUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-61 GPDCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24QUALPRD3R/W0hQualification sampling period for GPIO120 to GPIO127:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

23-16RESERVEDR/W0hReserved
15-8QUALPRD1R/W0hQualification sampling period for GPIO104 to GPIO111:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

7-0QUALPRD0R/W0hQualification sampling period for GPIO96 to GPIO103:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15.11.2.50 GPDQSEL1 Register (Offset = 184h) [Reset = 00000000h]

GPDQSEL1 is shown in Figure 15-53 and described in Table 15-62.

Return to the Summary Table.

GPIO D Qualifier Select 1 Register (GPIO96 to 111)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 15-53 GPDQSEL1 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDGPIO105RESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO103RESERVEDGPIO101GPIO100
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-62 GPDQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18GPIO105R/W0hSelect input qualification type for GPIO105:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16RESERVEDR/W0hReserved
15-14GPIO103R/W0hSelect input qualification type for GPIO103:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12RESERVEDR/W0hReserved
11-10GPIO101R/W0hSelect input qualification type for GPIO101:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO100R/W0hSelect input qualification type for GPIO100:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO99R/W0hSelect input qualification type for GPIO99:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO98R/W0hSelect input qualification type for GPIO98:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO97R/W0hSelect input qualification type for GPIO97:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO96R/W0hSelect input qualification type for GPIO96:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15.11.2.51 GPDQSEL2 Register (Offset = 188h) [Reset = 00000000h]

GPDQSEL2 is shown in Figure 15-54 and described in Table 15-63.

Return to the Summary Table.

GPIO D Qualifier Select 2 Register (GPIO112 to 127)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 15-54 GPDQSEL2 Register
3130292827262524
GPIO127RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-63 GPDQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO127R/W0hSelect input qualification type for GPIO127:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4RESERVEDR/W0hReserved
3-2RESERVEDR/W0hReserved
1-0RESERVEDR/W0hReserved

15.11.2.52 GPDMUX1 Register (Offset = 18Ch) [Reset = 00000000h]

GPDMUX1 is shown in Figure 15-55 and described in Table 15-64.

Return to the Summary Table.

GPIO D Mux 1 Register (GPIO96 to 111)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 15-55 GPDMUX1 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDGPIO105RESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO103RESERVEDGPIO101GPIO100
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-64 GPDMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18GPIO105R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16RESERVEDR/W0hReserved
15-14GPIO103R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12RESERVEDR/W0hReserved
11-10GPIO101R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO100R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO99R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO98R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO97R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO96R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.53 GPDMUX2 Register (Offset = 190h) [Reset = 00000000h]

GPDMUX2 is shown in Figure 15-56 and described in Table 15-65.

Return to the Summary Table.

GPIO D Mux 2 Register (GPIO112 to 127)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 15-56 GPDMUX2 Register
3130292827262524
GPIO127RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-65 GPDMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO127R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4RESERVEDR/W0hReserved
3-2RESERVEDR/W0hReserved
1-0RESERVEDR/W0hReserved

15.11.2.54 GPDPUD Register (Offset = 198h) [Reset = FFFFFFFFh]

GPDPUD is shown in Figure 15-57 and described in Table 15-66.

Return to the Summary Table.

GPIO D Pull Up Disable Register (GPIO96 to 127)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 15-57 GPDPUD Register
3130292827262524
GPIO127RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO105RESERVED
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO103RESERVEDGPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 15-66 GPDPUD Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

30RESERVEDR/W1hReserved
29RESERVEDR/W1hReserved
28RESERVEDR/W1hReserved
27RESERVEDR/W1hReserved
26RESERVEDR/W1hReserved
25RESERVEDR/W1hReserved
24RESERVEDR/W1hReserved
23RESERVEDR/W1hReserved
22RESERVEDR/W1hReserved
21RESERVEDR/W1hReserved
20RESERVEDR/W1hReserved
19RESERVEDR/W1hReserved
18RESERVEDR/W1hReserved
17RESERVEDR/W1hReserved
16RESERVEDR/W1hReserved
15RESERVEDR/W1hReserved
14RESERVEDR/W1hReserved
13RESERVEDR/W1hReserved
12RESERVEDR/W1hReserved
11RESERVEDR/W1hReserved
10RESERVEDR/W1hReserved
9GPIO105R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

8RESERVEDR/W1hReserved
7GPIO103R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

6RESERVEDR/W1hReserved
5GPIO101R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

4GPIO100R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

3GPIO99R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

2GPIO98R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

1GPIO97R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

0GPIO96R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15.11.2.55 GPDINV Register (Offset = 1A0h) [Reset = 00000000h]

GPDINV is shown in Figure 15-58 and described in Table 15-67.

Return to the Summary Table.

GPIO D Input Polarity Invert Registers (GPIO96 to 127)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 15-58 GPDINV Register
3130292827262524
GPIO127RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO105RESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO103RESERVEDGPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-67 GPDINV Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/W0hInput inversion control for this pin

Reset type: SYSRSn

30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9GPIO105R/W0hInput inversion control for this pin

Reset type: SYSRSn

8RESERVEDR/W0hReserved
7GPIO103R/W0hInput inversion control for this pin

Reset type: SYSRSn

6RESERVEDR/W0hReserved
5GPIO101R/W0hInput inversion control for this pin

Reset type: SYSRSn

4GPIO100R/W0hInput inversion control for this pin

Reset type: SYSRSn

3GPIO99R/W0hInput inversion control for this pin

Reset type: SYSRSn

2GPIO98R/W0hInput inversion control for this pin

Reset type: SYSRSn

1GPIO97R/W0hInput inversion control for this pin

Reset type: SYSRSn

0GPIO96R/W0hInput inversion control for this pin

Reset type: SYSRSn

15.11.2.56 GPDODR Register (Offset = 1A4h) [Reset = 00000000h]

GPDODR is shown in Figure 15-59 and described in Table 15-68.

Return to the Summary Table.

GPIO D Open Drain Output Register (GPIO96 to GPIO127)

Selects between normal and open-drain output for the GPIO pin.

0: Normal Output
1: Open Drain Output

Reading the register returns the current value of the register setting.

Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.

Figure 15-59 GPDODR Register
3130292827262524
GPIO127RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO105RESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO103RESERVEDGPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-68 GPDODR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9GPIO105R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

8RESERVEDR/W0hReserved
7GPIO103R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

6RESERVEDR/W0hReserved
5GPIO101R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

4GPIO100R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

3GPIO99R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

2GPIO98R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

1GPIO97R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

0GPIO96R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

15.11.2.57 GPDGMUX1 Register (Offset = 1C0h) [Reset = 00000000h]

GPDGMUX1 is shown in Figure 15-60 and described in Table 15-69.

Return to the Summary Table.

GPIO D Peripheral Group Mux (GPIO96 to 111)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 15-60 GPDGMUX1 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDGPIO105RESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO103RESERVEDGPIO101GPIO100
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-69 GPDGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18GPIO105R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16RESERVEDR/W0hReserved
15-14GPIO103R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12RESERVEDR/W0hReserved
11-10GPIO101R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO100R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO99R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO98R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO97R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO96R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.58 GPDGMUX2 Register (Offset = 1C4h) [Reset = 00000000h]

GPDGMUX2 is shown in Figure 15-61 and described in Table 15-70.

Return to the Summary Table.

GPIO D Peripheral Group Mux (GPIO112 to 127)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 15-61 GPDGMUX2 Register
3130292827262524
GPIO127RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-70 GPDGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO127R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4RESERVEDR/W0hReserved
3-2RESERVEDR/W0hReserved
1-0RESERVEDR/W0hReserved

15.11.2.59 GPDCSEL1 Register (Offset = 1D0h) [Reset = 00000000h]

GPDCSEL1 is shown in Figure 15-62 and described in Table 15-71.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-62 GPDCSEL1 Register
31302928272625242322212019181716
GPIO103RESERVEDGPIO101GPIO100
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-71 GPDCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO103R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24RESERVEDR/W0hReserved
23-20GPIO101R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO100R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO99R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO98R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO97R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO96R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.60 GPDCSEL2 Register (Offset = 1D4h) [Reset = 00000000h]

GPDCSEL2 is shown in Figure 15-63 and described in Table 15-72.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-63 GPDCSEL2 Register
31302928272625242322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
RESERVEDRESERVEDGPIO105RESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-72 GPDCSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0hReserved
27-24RESERVEDR/W0hReserved
23-20RESERVEDR/W0hReserved
19-16RESERVEDR/W0hReserved
15-12RESERVEDR/W0hReserved
11-8RESERVEDR/W0hReserved
7-4GPIO105R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0RESERVEDR/W0hReserved

15.11.2.61 GPDCSEL3 Register (Offset = 1D8h) [Reset = 00000000h]

GPDCSEL3 is shown in Figure 15-64 and described in Table 15-73.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-64 GPDCSEL3 Register
31302928272625242322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-73 GPDCSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0hReserved
27-24RESERVEDR/W0hReserved
23-20RESERVEDR/W0hReserved
19-16RESERVEDR/W0hReserved
15-12RESERVEDR/W0hReserved
11-8RESERVEDR/W0hReserved
7-4RESERVEDR/W0hReserved
3-0RESERVEDR/W0hReserved

15.11.2.62 GPDCSEL4 Register (Offset = 1DCh) [Reset = 00000000h]

GPDCSEL4 is shown in Figure 15-65 and described in Table 15-74.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-65 GPDCSEL4 Register
31302928272625242322212019181716
GPIO127RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-74 GPDCSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO127R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24RESERVEDR/W0hReserved
23-20RESERVEDR/W0hReserved
19-16RESERVEDR/W0hReserved
15-12RESERVEDR/W0hReserved
11-8RESERVEDR/W0hReserved
7-4RESERVEDR/W0hReserved
3-0RESERVEDR/W0hReserved

15.11.2.63 GPDLOCK Register (Offset = 1F8h) [Reset = 00000000h]

GPDLOCK is shown in Figure 15-66 and described in Table 15-75.

Return to the Summary Table.

GPIO D Lock Configuration Register (GPIO96 to 127)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 15-66 GPDLOCK Register
3130292827262524
GPIO127RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO105RESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO103RESERVEDGPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-75 GPDLOCK Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9GPIO105R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

8RESERVEDR/W0hReserved
7GPIO103R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

6RESERVEDR/W0hReserved
5GPIO101R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

4GPIO100R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

3GPIO99R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

2GPIO98R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

1GPIO97R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

0GPIO96R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15.11.2.64 GPDCR Register (Offset = 1FCh) [Reset = 00000000h]

GPDCR is shown in Figure 15-67 and described in Table 15-76.

Return to the Summary Table.

GPIO D Lock Commit Register (GPIO96 to 127)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 15-67 GPDCR Register
3130292827262524
GPIO127RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO105RESERVED
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
GPIO103RESERVEDGPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 15-76 GPDCR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

30RESERVEDR/WSonce0hReserved
29RESERVEDR/WSonce0hReserved
28RESERVEDR/WSonce0hReserved
27RESERVEDR/WSonce0hReserved
26RESERVEDR/WSonce0hReserved
25RESERVEDR/WSonce0hReserved
24RESERVEDR/WSonce0hReserved
23RESERVEDR/WSonce0hReserved
22RESERVEDR/WSonce0hReserved
21RESERVEDR/WSonce0hReserved
20RESERVEDR/WSonce0hReserved
19RESERVEDR/WSonce0hReserved
18RESERVEDR/WSonce0hReserved
17RESERVEDR/WSonce0hReserved
16RESERVEDR/WSonce0hReserved
15RESERVEDR/WSonce0hReserved
14RESERVEDR/WSonce0hReserved
13RESERVEDR/WSonce0hReserved
12RESERVEDR/WSonce0hReserved
11RESERVEDR/WSonce0hReserved
10RESERVEDR/WSonce0hReserved
9GPIO105R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

8RESERVEDR/WSonce0hReserved
7GPIO103R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

6RESERVEDR/WSonce0hReserved
5GPIO101R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

4GPIO100R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

3GPIO99R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

2GPIO98R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

1GPIO97R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

0GPIO96R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15.11.2.65 GPFCTRL Register (Offset = 280h) [Reset = 00000000h]

GPFCTRL is shown in Figure 15-68 and described in Table 15-77.

Return to the Summary Table.

GPIO F Qualification Sampling Period Control (GPIO160 to 191)

Figure 15-68 GPFCTRL Register
313029282726252423222120191817161514131211109876543210
QUALPRD3QUALPRD2QUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-77 GPFCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24QUALPRD3R/W0hQualification sampling period for GPIO184 to GPIO191:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

23-16QUALPRD2R/W0hQualification sampling period for GPIO176 to GPIO183:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15-8QUALPRD1R/W0hQualification sampling period for GPIO168:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

7-0QUALPRD0R/W0hQualification sampling period for GPIO160 to GPIO167:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15.11.2.66 GPFQSEL1 Register (Offset = 284h) [Reset = 00000000h]

GPFQSEL1 is shown in Figure 15-69 and described in Table 15-78.

Return to the Summary Table.

GPIO F Qualifier Select 1 Register (GPIO160 to 168)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 15-69 GPFQSEL1 Register
3130292827262524
GPIO175GPIO174GPIO173GPIO172
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO171GPIO170GPIO169GPIO168
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO167GPIO166GPIO165GPIO164
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-78 GPFQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO175R/W0hSelect input qualification type for GPIO175:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO174R/W0hSelect input qualification type for GPIO174:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO173R/W0hSelect input qualification type for GPIO173:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO172R/W0hSelect input qualification type for GPIO172:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO171R/W0hSelect input qualification type for GPIO171:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO170R/W0hSelect input qualification type for GPIO170:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO169R/W0hSelect input qualification type for GPIO169:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO168R/W0hSelect input qualification type for GPIO168:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO167R/W0hSelect input qualification type for GPIO167:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO166R/W0hSelect input qualification type for GPIO166:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO165R/W0hSelect input qualification type for GPIO165:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO164R/W0hSelect input qualification type for GPIO164:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO163R/W0hSelect input qualification type for GPIO163:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO162R/W0hSelect input qualification type for GPIO162:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO161R/W0hSelect input qualification type for GPIO161:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO160R/W0hSelect input qualification type for GPIO160:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15.11.2.67 GPFQSEL2 Register (Offset = 288h) [Reset = 00000000h]

GPFQSEL2 is shown in Figure 15-70 and described in Table 15-79.

Return to the Summary Table.

GPIO F Qualifier Select 2 Register (GPIO176 to 191)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 15-70 GPFQSEL2 Register
3130292827262524
GPIO191GPIO190GPIO189GPIO188
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO187GPIO186GPIO185GPIO184
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO183GPIO182GPIO181GPIO180
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO179GPIO178GPIO177GPIO176
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-79 GPFQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO191R/W0hSelect input qualification type for GPIO191:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO190R/W0hSelect input qualification type for GPIO190:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO189R/W0hSelect input qualification type for GPIO189:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO188R/W0hSelect input qualification type for GPIO188:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO187R/W0hSelect input qualification type for GPIO187:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO186R/W0hSelect input qualification type for GPIO186:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO185R/W0hSelect input qualification type for GPIO185:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO184R/W0hSelect input qualification type for GPIO184:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO183R/W0hSelect input qualification type for GPIO183:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO182R/W0hSelect input qualification type for GPIO182:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO181R/W0hSelect input qualification type for GPIO181:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO180R/W0hSelect input qualification type for GPIO180:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO179R/W0hSelect input qualification type for GPIO179:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO178R/W0hSelect input qualification type for GPIO178:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO177R/W0hSelect input qualification type for GPIO177:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO176R/W0hSelect input qualification type for GPIO176:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15.11.2.68 GPFMUX1 Register (Offset = 28Ch) [Reset = 00000000h]

GPFMUX1 is shown in Figure 15-71 and described in Table 15-80.

Return to the Summary Table.

GPIO F Mux 1 Register (GPIO160 to 175)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 15-71 GPFMUX1 Register
3130292827262524
GPIO175GPIO174GPIO173GPIO172
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO171GPIO170GPIO169GPIO168
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO167GPIO166GPIO165GPIO164
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-80 GPFMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO175R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO174R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO173R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO172R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO171R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO170R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO169R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO168R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO167R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO166R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO165R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO164R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO163R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO162R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO161R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO160R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.69 GPFMUX2 Register (Offset = 290h) [Reset = 00000000h]

GPFMUX2 is shown in Figure 15-72 and described in Table 15-81.

Return to the Summary Table.

GPIO F Mux 2 Register (GPIO176 to 191)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 15-72 GPFMUX2 Register
3130292827262524
GPIO191GPIO190GPIO189GPIO188
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO187GPIO186GPIO185GPIO184
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO183GPIO182GPIO181GPIO180
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO179GPIO178GPIO177GPIO176
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-81 GPFMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO191R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO190R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO189R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO188R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO187R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO186R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO185R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO184R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO183R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO182R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO181R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO180R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO179R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO178R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO177R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO176R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.70 GPFPUD Register (Offset = 298h) [Reset = FFFFFFFFh]

GPFPUD is shown in Figure 15-73 and described in Table 15-82.

Return to the Summary Table.

GPIO F Pull Up Disable Register (GPIO160 to 191)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 15-73 GPFPUD Register
3130292827262524
GPIO191GPIO190GPIO189GPIO188GPIO187GPIO186GPIO185GPIO184
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
GPIO183GPIO182GPIO181GPIO180GPIO179GPIO178GPIO177GPIO176
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO175GPIO174GPIO173GPIO172GPIO171GPIO170GPIO169GPIO168
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 15-82 GPFPUD Register Field Descriptions
BitFieldTypeResetDescription
31GPIO191R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

30GPIO190R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

29GPIO189R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

28GPIO188R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

27GPIO187R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

26GPIO186R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

25GPIO185R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

24GPIO184R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

23GPIO183R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

22GPIO182R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

21GPIO181R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

20GPIO180R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

19GPIO179R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

18GPIO178R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

17GPIO177R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

16GPIO176R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15GPIO175R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14GPIO174R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

13GPIO173R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

12GPIO172R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

11GPIO171R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

10GPIO170R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

9GPIO169R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

8GPIO168R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

7GPIO167R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

6GPIO166R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

5GPIO165R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

4GPIO164R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

3GPIO163R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

2GPIO162R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

1GPIO161R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

0GPIO160R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15.11.2.71 GPFINV Register (Offset = 2A0h) [Reset = 00000000h]

GPFINV is shown in Figure 15-74 and described in Table 15-83.

Return to the Summary Table.

GPIO F Input Polarity Invert Registers (GPIO160 to 191)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 15-74 GPFINV Register
3130292827262524
GPIO191GPIO190GPIO189GPIO188GPIO187GPIO186GPIO185GPIO184
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO183GPIO182GPIO181GPIO180GPIO179GPIO178GPIO177GPIO176
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO175GPIO174GPIO173GPIO172GPIO171GPIO170GPIO169GPIO168
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-83 GPFINV Register Field Descriptions
BitFieldTypeResetDescription
31GPIO191R/W0hInput inversion control for this pin

Reset type: SYSRSn

30GPIO190R/W0hInput inversion control for this pin

Reset type: SYSRSn

29GPIO189R/W0hInput inversion control for this pin

Reset type: SYSRSn

28GPIO188R/W0hInput inversion control for this pin

Reset type: SYSRSn

27GPIO187R/W0hInput inversion control for this pin

Reset type: SYSRSn

26GPIO186R/W0hInput inversion control for this pin

Reset type: SYSRSn

25GPIO185R/W0hInput inversion control for this pin

Reset type: SYSRSn

24GPIO184R/W0hInput inversion control for this pin

Reset type: SYSRSn

23GPIO183R/W0hInput inversion control for this pin

Reset type: SYSRSn

22GPIO182R/W0hInput inversion control for this pin

Reset type: SYSRSn

21GPIO181R/W0hInput inversion control for this pin

Reset type: SYSRSn

20GPIO180R/W0hInput inversion control for this pin

Reset type: SYSRSn

19GPIO179R/W0hInput inversion control for this pin

Reset type: SYSRSn

18GPIO178R/W0hInput inversion control for this pin

Reset type: SYSRSn

17GPIO177R/W0hInput inversion control for this pin

Reset type: SYSRSn

16GPIO176R/W0hInput inversion control for this pin

Reset type: SYSRSn

15GPIO175R/W0hInput inversion control for this pin

Reset type: SYSRSn

14GPIO174R/W0hInput inversion control for this pin

Reset type: SYSRSn

13GPIO173R/W0hInput inversion control for this pin

Reset type: SYSRSn

12GPIO172R/W0hInput inversion control for this pin

Reset type: SYSRSn

11GPIO171R/W0hInput inversion control for this pin

Reset type: SYSRSn

10GPIO170R/W0hInput inversion control for this pin

Reset type: SYSRSn

9GPIO169R/W0hInput inversion control for this pin

Reset type: SYSRSn

8GPIO168R/W0hInput inversion control for this pin

Reset type: SYSRSn

7GPIO167R/W0hInput inversion control for this pin

Reset type: SYSRSn

6GPIO166R/W0hInput inversion control for this pin

Reset type: SYSRSn

5GPIO165R/W0hInput inversion control for this pin

Reset type: SYSRSn

4GPIO164R/W0hInput inversion control for this pin

Reset type: SYSRSn

3GPIO163R/W0hInput inversion control for this pin

Reset type: SYSRSn

2GPIO162R/W0hInput inversion control for this pin

Reset type: SYSRSn

1GPIO161R/W0hInput inversion control for this pin

Reset type: SYSRSn

0GPIO160R/W0hInput inversion control for this pin

Reset type: SYSRSn

15.11.2.72 GPFAMSEL Register (Offset = 2A8h) [Reset = FFFFFFFFh]

GPFAMSEL is shown in Figure 15-75 and described in Table 15-84.

Return to the Summary Table.

GPIO F Analog Mode Select register (GPIO160 to GPIO 191)

Selects between digital and analog functionality for GPIO pins.

0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, t

Figure 15-75 GPFAMSEL Register
3130292827262524
GPIO191GPIO190GPIO189GPIO188GPIO187GPIO186GPIO185GPIO184
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
GPIO183GPIO182GPIO181GPIO180GPIO179GPIO178GPIO177GPIO176
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO175GPIO174GPIO173GPIO172GPIO171GPIO170GPIO169GPIO168
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 15-84 GPFAMSEL Register Field Descriptions
BitFieldTypeResetDescription
31GPIO191R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

30GPIO190R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

29GPIO189R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

28GPIO188R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

27GPIO187R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

26GPIO186R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

25GPIO185R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

24GPIO184R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

23GPIO183R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

22GPIO182R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

21GPIO181R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

20GPIO180R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

19GPIO179R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

18GPIO178R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

17GPIO177R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

16GPIO176R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

15GPIO175R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

14GPIO174R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

13GPIO173R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

12GPIO172R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

11GPIO171R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

10GPIO170R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

9GPIO169R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

8GPIO168R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

7GPIO167R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

6GPIO166R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

5GPIO165R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

4GPIO164R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

3GPIO163R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

2GPIO162R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

1GPIO161R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

0GPIO160R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

15.11.2.73 GPFGMUX1 Register (Offset = 2C0h) [Reset = 00000000h]

GPFGMUX1 is shown in Figure 15-76 and described in Table 15-85.

Return to the Summary Table.

GPIO F Peripheral Group Mux (GPIO160 to 175)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 15-76 GPFGMUX1 Register
3130292827262524
GPIO175GPIO174GPIO173GPIO172
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO171GPIO170GPIO169GPIO168
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO167GPIO166GPIO165GPIO164
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-85 GPFGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO175R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO174R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO173R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO172R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO171R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO170R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO169R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO168R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO167R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO166R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO165R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO164R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO163R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO162R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO161R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO160R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.74 GPFGMUX2 Register (Offset = 2C4h) [Reset = 00000000h]

GPFGMUX2 is shown in Figure 15-77 and described in Table 15-86.

Return to the Summary Table.

GPIO F Peripheral Group Mux (GPIO176 to 191)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 15-77 GPFGMUX2 Register
3130292827262524
GPIO191GPIO190GPIO189GPIO188
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO187GPIO186GPIO185GPIO184
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO183GPIO182GPIO181GPIO180
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO179GPIO178GPIO177GPIO176
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-86 GPFGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO191R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO190R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO189R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO188R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO187R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO186R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO185R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO184R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO183R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO182R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO181R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO180R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO179R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO178R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO177R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO176R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.75 GPFCSEL1 Register (Offset = 2D0h) [Reset = 00000000h]

GPFCSEL1 is shown in Figure 15-78 and described in Table 15-87.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-78 GPFCSEL1 Register
31302928272625242322212019181716
GPIO167GPIO166GPIO165GPIO164
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-87 GPFCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO167R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO166R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO165R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO164R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO163R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO162R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO161R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO160R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.76 GPFCSEL2 Register (Offset = 2D4h) [Reset = 00000000h]

GPFCSEL2 is shown in Figure 15-79 and described in Table 15-88.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-79 GPFCSEL2 Register
31302928272625242322212019181716
GPIO175GPIO174GPIO173GPIO172
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO171GPIO170GPIO169GPIO168
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-88 GPFCSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO175R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO174R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO173R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO172R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO171R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO170R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO169R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO168R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.77 GPFCSEL3 Register (Offset = 2D8h) [Reset = 00000000h]

GPFCSEL3 is shown in Figure 15-80 and described in Table 15-89.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-80 GPFCSEL3 Register
31302928272625242322212019181716
GPIO183GPIO182GPIO181GPIO180
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO179GPIO178GPIO177GPIO176
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-89 GPFCSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO183R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO182R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO181R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO180R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO179R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO178R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO177R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO176R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.78 GPFCSEL4 Register (Offset = 2DCh) [Reset = 00000000h]

GPFCSEL4 is shown in Figure 15-81 and described in Table 15-90.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-81 GPFCSEL4 Register
31302928272625242322212019181716
GPIO191GPIO190GPIO189GPIO188
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO187GPIO186GPIO185GPIO184
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-90 GPFCSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO191R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO190R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO189R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO188R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO187R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO186R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO185R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO184R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.79 GPFLOCK Register (Offset = 2F8h) [Reset = 00000000h]

GPFLOCK is shown in Figure 15-82 and described in Table 15-91.

Return to the Summary Table.

GPIO F Lock Configuration Register (GPIO160 to 191)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 15-82 GPFLOCK Register
3130292827262524
GPIO191GPIO190GPIO189GPIO188GPIO187GPIO186GPIO185GPIO184
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO183GPIO182GPIO181GPIO180GPIO179GPIO178GPIO177GPIO176
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO175GPIO174GPIO173GPIO172GPIO171GPIO170GPIO169GPIO168
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-91 GPFLOCK Register Field Descriptions
BitFieldTypeResetDescription
31GPIO191R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

30GPIO190R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

29GPIO189R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

28GPIO188R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

27GPIO187R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

26GPIO186R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

25GPIO185R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

24GPIO184R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

23GPIO183R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

22GPIO182R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

21GPIO181R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

20GPIO180R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

19GPIO179R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

18GPIO178R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

17GPIO177R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

16GPIO176R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15GPIO175R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14GPIO174R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

13GPIO173R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

12GPIO172R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

11GPIO171R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

10GPIO170R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

9GPIO169R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

8GPIO168R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

7GPIO167R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

6GPIO166R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

5GPIO165R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

4GPIO164R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

3GPIO163R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

2GPIO162R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

1GPIO161R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

0GPIO160R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15.11.2.80 GPFCR Register (Offset = 2FCh) [Reset = 00000000h]

GPFCR is shown in Figure 15-83 and described in Table 15-92.

Return to the Summary Table.

GPIO F Lock Commit Register (GPIO160 to 191)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 15-83 GPFCR Register
3130292827262524
GPIO191GPIO190GPIO189GPIO188GPIO187GPIO186GPIO185GPIO184
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
GPIO183GPIO182GPIO181GPIO180GPIO179GPIO178GPIO177GPIO176
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
GPIO175GPIO174GPIO173GPIO172GPIO171GPIO170GPIO169GPIO168
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 15-92 GPFCR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO191R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

30GPIO190R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

29GPIO189R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

28GPIO188R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

27GPIO187R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

26GPIO186R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

25GPIO185R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

24GPIO184R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

23GPIO183R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

22GPIO182R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

21GPIO181R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

20GPIO180R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

19GPIO179R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

18GPIO178R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

17GPIO177R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

16GPIO176R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15GPIO175R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14GPIO174R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

13GPIO173R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

12GPIO172R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

11GPIO171R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

10GPIO170R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

9GPIO169R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

8GPIO168R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

7GPIO167R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

6GPIO166R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

5GPIO165R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

4GPIO164R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

3GPIO163R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

2GPIO162R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

1GPIO161R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

0GPIO160R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15.11.2.81 GPGCTRL Register (Offset = 300h) [Reset = 00000000h]

GPGCTRL is shown in Figure 15-84 and described in Table 15-93.

Return to the Summary Table.

GPIO G Qualification Sampling Period Control (GPIO192 to 223)

Figure 15-84 GPGCTRL Register
313029282726252423222120191817161514131211109876543210
QUALPRD3QUALPRD2QUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-93 GPGCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24QUALPRD3R/W0hQualification sampling period for GPIO216 to GPIO223:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

23-16QUALPRD2R/W0hQualification sampling period for GPIO208 to GPIO215:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15-8QUALPRD1R/W0hQualification sampling period for GPIO200 to GPIO207:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

7-0QUALPRD0R/W0hQualification sampling period for GPIO192 to GPIO199:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15.11.2.82 GPGQSEL1 Register (Offset = 304h) [Reset = 00000000h]

GPGQSEL1 is shown in Figure 15-85 and described in Table 15-94.

Return to the Summary Table.

GPIO G Qualifier Select 1 Register (GPIO192 to 207)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 15-85 GPGQSEL1 Register
3130292827262524
GPIO207GPIO206GPIO205GPIO204
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO199GPIO198GPIO197GPIO196
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO195GPIO194GPIO193GPIO192
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-94 GPGQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO207R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO206R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO205R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO204R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO203R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO202R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO201R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO200R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO199R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO198R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO197R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO196R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO195R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO194R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO193R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO192R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15.11.2.83 GPGQSEL2 Register (Offset = 308h) [Reset = F0000000h]

GPGQSEL2 is shown in Figure 15-86 and described in Table 15-95.

Return to the Summary Table.

GPIO G Qualifier Select 2 Register (GPIO208 to 223)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 15-86 GPGQSEL2 Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220
R/W-3hR/W-3hR/W-0hR/W-0h
2322212019181716
GPIO219RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDGPIO213GPIO212
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-95 GPGQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO223R/W3hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO222R/W3hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO221R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO220R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO219R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12RESERVEDR/W0hReserved
11-10GPIO213R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO212R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO211R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO210R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO209R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO208R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15.11.2.84 GPGMUX1 Register (Offset = 30Ch) [Reset = 00000000h]

GPGMUX1 is shown in Figure 15-87 and described in Table 15-96.

Return to the Summary Table.

GPIO G Mux 1 Register (GPIO192 to 207)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 15-87 GPGMUX1 Register
3130292827262524
GPIO207GPIO206GPIO205GPIO204
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO199GPIO198GPIO197GPIO196
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO195GPIO194GPIO193GPIO192
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-96 GPGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO207R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO206R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO205R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO204R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO203R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO202R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO201R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO200R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO199R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO198R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO197R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO196R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO195R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO194R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO193R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO192R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.85 GPGMUX2 Register (Offset = 310h) [Reset = 50000000h]

GPGMUX2 is shown in Figure 15-88 and described in Table 15-97.

Return to the Summary Table.

GPIO G Mux 2 Register (GPIO208 to 223)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 15-88 GPGMUX2 Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220
R/W-1hR/W-1hR/W-0hR/W-0h
2322212019181716
GPIO219RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDGPIO213GPIO212
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-97 GPGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO223R/W1hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO222R/W1hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO221R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO220R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO219R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12RESERVEDR/W0hReserved
11-10GPIO213R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO212R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO211R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO210R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO209R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO208R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.86 GPGPUD Register (Offset = 318h) [Reset = FFFFFFFFh]

GPGPUD is shown in Figure 15-89 and described in Table 15-98.

Return to the Summary Table.

GPIO G Pull Up Disable Register (GPIO192 to 223)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 15-89 GPGPUD Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220GPIO219RESERVEDRESERVEDRESERVED
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
RESERVEDRESERVEDGPIO213GPIO212GPIO211GPIO210GPIO209GPIO208
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO207GPIO206GPIO205GPIO204GPIO203GPIO202GPIO201GPIO200
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO199GPIO198GPIO197GPIO196GPIO195GPIO194GPIO193GPIO192
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 15-98 GPGPUD Register Field Descriptions
BitFieldTypeResetDescription
31GPIO223R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

30GPIO222R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

29GPIO221R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

28GPIO220R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

27GPIO219R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

26RESERVEDR/W1hReserved
25RESERVEDR/W1hReserved
24RESERVEDR/W1hReserved
23RESERVEDR/W1hReserved
22RESERVEDR/W1hReserved
21GPIO213R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

20GPIO212R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

19GPIO211R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

18GPIO210R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

17GPIO209R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

16GPIO208R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15GPIO207R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14GPIO206R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

13GPIO205R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

12GPIO204R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

11GPIO203R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

10GPIO202R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

9GPIO201R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

8GPIO200R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

7GPIO199R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

6GPIO198R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

5GPIO197R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

4GPIO196R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

3GPIO195R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

2GPIO194R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

1GPIO193R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

0GPIO192R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15.11.2.87 GPGINV Register (Offset = 320h) [Reset = 00000000h]

GPGINV is shown in Figure 15-90 and described in Table 15-99.

Return to the Summary Table.

GPIO G Input Polarity Invert Registers (GPIO192 to 223)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 15-90 GPGINV Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220GPIO219RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDGPIO213GPIO212GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO207GPIO206GPIO205GPIO204GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO199GPIO198GPIO197GPIO196GPIO195GPIO194GPIO193GPIO192
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-99 GPGINV Register Field Descriptions
BitFieldTypeResetDescription
31GPIO223R/W0hInput inversion control for this pin

Reset type: SYSRSn

30GPIO222R/W0hInput inversion control for this pin

Reset type: SYSRSn

29GPIO221R/W0hInput inversion control for this pin

Reset type: SYSRSn

28GPIO220R/W0hInput inversion control for this pin

Reset type: SYSRSn

27GPIO219R/W0hInput inversion control for this pin

Reset type: SYSRSn

26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21GPIO213R/W0hInput inversion control for this pin

Reset type: SYSRSn

20GPIO212R/W0hInput inversion control for this pin

Reset type: SYSRSn

19GPIO211R/W0hInput inversion control for this pin

Reset type: SYSRSn

18GPIO210R/W0hInput inversion control for this pin

Reset type: SYSRSn

17GPIO209R/W0hInput inversion control for this pin

Reset type: SYSRSn

16GPIO208R/W0hInput inversion control for this pin

Reset type: SYSRSn

15GPIO207R/W0hInput inversion control for this pin

Reset type: SYSRSn

14GPIO206R/W0hInput inversion control for this pin

Reset type: SYSRSn

13GPIO205R/W0hInput inversion control for this pin

Reset type: SYSRSn

12GPIO204R/W0hInput inversion control for this pin

Reset type: SYSRSn

11GPIO203R/W0hInput inversion control for this pin

Reset type: SYSRSn

10GPIO202R/W0hInput inversion control for this pin

Reset type: SYSRSn

9GPIO201R/W0hInput inversion control for this pin

Reset type: SYSRSn

8GPIO200R/W0hInput inversion control for this pin

Reset type: SYSRSn

7GPIO199R/W0hInput inversion control for this pin

Reset type: SYSRSn

6GPIO198R/W0hInput inversion control for this pin

Reset type: SYSRSn

5GPIO197R/W0hInput inversion control for this pin

Reset type: SYSRSn

4GPIO196R/W0hInput inversion control for this pin

Reset type: SYSRSn

3GPIO195R/W0hInput inversion control for this pin

Reset type: SYSRSn

2GPIO194R/W0hInput inversion control for this pin

Reset type: SYSRSn

1GPIO193R/W0hInput inversion control for this pin

Reset type: SYSRSn

0GPIO192R/W0hInput inversion control for this pin

Reset type: SYSRSn

15.11.2.88 GPGODR Register (Offset = 324h) [Reset = 00000000h]

GPGODR is shown in Figure 15-91 and described in Table 15-100.

Return to the Summary Table.

GPIO G Open Drain Output Register (GPIO92 to 223)

Selects between normal and open-drain output for the GPIO pin.

0: Normal Output
1: Open Drain Output

Reading the register returns the current value of the register setting.

Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.

Figure 15-91 GPGODR Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220GPIO219RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-100 GPGODR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO223R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

30GPIO222R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

29GPIO221R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

28GPIO220R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

27GPIO219R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8RESERVEDR/W0hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

15.11.2.89 GPGAMSEL Register (Offset = 328h) [Reset = 003FFFFFh]

GPGAMSEL is shown in Figure 15-92 and described in Table 15-101.

Return to the Summary Table.

GPIO G Analog Mode Select register (GPIO192 to 223)

Selects between digital and analog functionality for GPIO pins.

0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, t

Figure 15-92 GPGAMSEL Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDGPIO213GPIO212GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO207GPIO206GPIO205GPIO204GPIO203GPIO202GPIO201GPIO200
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO199GPIO198GPIO197GPIO196GPIO195GPIO194GPIO193GPIO192
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 15-101 GPGAMSEL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21GPIO213R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

20GPIO212R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

19GPIO211R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

18GPIO210R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

17GPIO209R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

16GPIO208R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

15GPIO207R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

14GPIO206R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

13GPIO205R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

12GPIO204R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

11GPIO203R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

10GPIO202R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

9GPIO201R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

8GPIO200R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

7GPIO199R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

6GPIO198R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

5GPIO197R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

4GPIO196R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

3GPIO195R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

2GPIO194R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

1GPIO193R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

0GPIO192R/W1hAnalog Mode select for this pin

Reset type: SYSRSn

15.11.2.90 GPGGMUX1 Register (Offset = 340h) [Reset = 00000000h]

GPGGMUX1 is shown in Figure 15-93 and described in Table 15-102.

Return to the Summary Table.

GPIO G Peripheral Group Mux (GPIO192 to 207)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 15-93 GPGGMUX1 Register
3130292827262524
GPIO207GPIO206GPIO205GPIO204
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO199GPIO198GPIO197GPIO196
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO195GPIO194GPIO193GPIO192
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-102 GPGGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO207R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO206R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO205R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO204R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO203R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO202R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO201R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO200R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO199R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO198R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO197R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO196R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO195R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO194R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO193R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO192R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.91 GPGGMUX2 Register (Offset = 344h) [Reset = 00000000h]

GPGGMUX2 is shown in Figure 15-94 and described in Table 15-103.

Return to the Summary Table.

GPIO G Peripheral Group Mux (GPIO208 to 223)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 15-94 GPGGMUX2 Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO219RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDGPIO213GPIO212
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-103 GPGGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO223R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO222R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO221R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO220R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO219R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12RESERVEDR/W0hReserved
11-10GPIO213R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO212R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO211R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO210R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO209R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO208R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.92 GPGCSEL1 Register (Offset = 350h) [Reset = 00000000h]

GPGCSEL1 is shown in Figure 15-95 and described in Table 15-104.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-95 GPGCSEL1 Register
31302928272625242322212019181716
GPIO199GPIO198GPIO197GPIO196
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO195GPIO194GPIO193GPIO192
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-104 GPGCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO199R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO198R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO197R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO196R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO195R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO194R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO193R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO192R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.93 GPGCSEL2 Register (Offset = 354h) [Reset = 00000000h]

GPGCSEL2 is shown in Figure 15-96 and described in Table 15-105.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-96 GPGCSEL2 Register
31302928272625242322212019181716
GPIO207GPIO206GPIO205GPIO204
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-105 GPGCSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO207R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO206R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO205R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO204R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO203R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO202R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO201R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO200R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.94 GPGCSEL3 Register (Offset = 358h) [Reset = 00000000h]

GPGCSEL3 is shown in Figure 15-97 and described in Table 15-106.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-97 GPGCSEL3 Register
31302928272625242322212019181716
RESERVEDRESERVEDGPIO213GPIO212
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-106 GPGCSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0hReserved
27-24RESERVEDR/W0hReserved
23-20GPIO213R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO212R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO211R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO210R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO209R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO208R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.95 GPGCSEL4 Register (Offset = 35Ch) [Reset = 00000000h]

GPGCSEL4 is shown in Figure 15-98 and described in Table 15-107.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-98 GPGCSEL4 Register
31302928272625242322212019181716
GPIO223GPIO222GPIO221GPIO220
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO219RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-107 GPGCSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO223R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO222R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO221R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO220R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO219R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8RESERVEDR/W0hReserved
7-4RESERVEDR/W0hReserved
3-0RESERVEDR/W0hReserved

15.11.2.96 GPGLOCK Register (Offset = 378h) [Reset = 00000000h]

GPGLOCK is shown in Figure 15-99 and described in Table 15-108.

Return to the Summary Table.

GPIO G Lock Configuration Register (GPIO192 to 223)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 15-99 GPGLOCK Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220GPIO219RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDGPIO213GPIO212GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO207GPIO206GPIO205GPIO204GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO199GPIO198GPIO197GPIO196GPIO195GPIO194GPIO193GPIO192
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-108 GPGLOCK Register Field Descriptions
BitFieldTypeResetDescription
31GPIO223R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

30GPIO222R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

29GPIO221R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

28GPIO220R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

27GPIO219R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21GPIO213R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

20GPIO212R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

19GPIO211R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

18GPIO210R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

17GPIO209R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

16GPIO208R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15GPIO207R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14GPIO206R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

13GPIO205R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

12GPIO204R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

11GPIO203R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

10GPIO202R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

9GPIO201R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

8GPIO200R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

7GPIO199R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

6GPIO198R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

5GPIO197R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

4GPIO196R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

3GPIO195R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

2GPIO194R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

1GPIO193R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

0GPIO192R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15.11.2.97 GPGCR Register (Offset = 37Ch) [Reset = 00000000h]

GPGCR is shown in Figure 15-100 and described in Table 15-109.

Return to the Summary Table.

GPIO G Lock Commit Register (GPIO192 to 223)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 15-100 GPGCR Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220GPIO219RESERVEDRESERVEDRESERVED
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
RESERVEDRESERVEDGPIO213GPIO212GPIO211GPIO210GPIO209GPIO208
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
GPIO207GPIO206GPIO205GPIO204GPIO203GPIO202GPIO201GPIO200
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
GPIO199GPIO198GPIO197GPIO196GPIO195GPIO194GPIO193GPIO192
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 15-109 GPGCR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO223R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

30GPIO222R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

29GPIO221R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

28GPIO220R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

27GPIO219R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

26RESERVEDR/WSonce0hReserved
25RESERVEDR/WSonce0hReserved
24RESERVEDR/WSonce0hReserved
23RESERVEDR/WSonce0hReserved
22RESERVEDR/WSonce0hReserved
21GPIO213R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

20GPIO212R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

19GPIO211R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

18GPIO210R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

17GPIO209R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

16GPIO208R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15GPIO207R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14GPIO206R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

13GPIO205R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

12GPIO204R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

11GPIO203R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

10GPIO202R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

9GPIO201R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

8GPIO200R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

7GPIO199R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

6GPIO198R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

5GPIO197R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

4GPIO196R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

3GPIO195R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

2GPIO194R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

1GPIO193R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

0GPIO192R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15.11.2.98 GPHCTRL Register (Offset = 380h) [Reset = 00000000h]

GPHCTRL is shown in Figure 15-101 and described in Table 15-110.

Return to the Summary Table.

GPIO H Qualification Sampling Period Control (GPIO224 to 255)

Figure 15-101 GPHCTRL Register
313029282726252423222120191817161514131211109876543210
QUALPRD3QUALPRD2QUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-110 GPHCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24QUALPRD3R/W0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/513

Reset type: SYSRSn

23-16QUALPRD2R/W0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/512

Reset type: SYSRSn

15-8QUALPRD1R/W0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/511

Reset type: SYSRSn

7-0QUALPRD0R/W0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15.11.2.99 GPHQSEL1 Register (Offset = 384h) [Reset = 00000000h]

GPHQSEL1 is shown in Figure 15-102 and described in Table 15-111.

Return to the Summary Table.

GPIO H Qualifier Select 1 Register (GPIO224 to 239)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 15-102 GPHQSEL1 Register
3130292827262524
GPIO239GPIO238GPIO237GPIO236
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO231GPIO230GPIO229GPIO228
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-111 GPHQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO239R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO238R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO237R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO236R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO235R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO234R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO233R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO232R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO231R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO230R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO229R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO228R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO227R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO226R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO225R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO224R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15.11.2.100 GPHQSEL2 Register (Offset = 388h) [Reset = 00000000h]

GPHQSEL2 is shown in Figure 15-103 and described in Table 15-112.

Return to the Summary Table.

GPIO H Qualifier Select 2 Register (GPIO240 to 255)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 15-103 GPHQSEL2 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDGPIO249GPIO248
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO247GPIO246GPIO245GPIO244
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO243GPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-112 GPHQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18GPIO249R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO248R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO247R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO246R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO245R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO244R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO243R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO242R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO241R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO240R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15.11.2.101 GPHMUX1 Register (Offset = 38Ch) [Reset = 00000000h]

GPHMUX1 is shown in Figure 15-104 and described in Table 15-113.

Return to the Summary Table.

GPIO H Mux 1 Register (GPIO224 to 239)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 15-104 GPHMUX1 Register
3130292827262524
GPIO239GPIO238GPIO237GPIO236
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO231GPIO230GPIO229GPIO228
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-113 GPHMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO239R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO238R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO237R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO236R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO235R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO234R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO233R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO232R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO231R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO230R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO229R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO228R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO227R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO226R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO225R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO224R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.102 GPHMUX2 Register (Offset = 390h) [Reset = 00000000h]

GPHMUX2 is shown in Figure 15-105 and described in Table 15-114.

Return to the Summary Table.

GPIO H Mux 2 Register (GPIO240 to 255)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 15-105 GPHMUX2 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDGPIO249GPIO248
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO247GPIO246GPIO245GPIO244
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO243GPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-114 GPHMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18GPIO249R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO248R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO247R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO246R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO245R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO244R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO243R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO242R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO241R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO240R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.103 GPHPUD Register (Offset = 398h) [Reset = FFFFFFFFh]

GPHPUD is shown in Figure 15-106 and described in Table 15-115.

Return to the Summary Table.

GPIO H Pull Up Disable Register (GPIO224 to 255)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 15-106 GPHPUD Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO249GPIO248
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
GPIO247GPIO246GPIO245GPIO244GPIO243GPIO242GPIO241GPIO240
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO239GPIO238GPIO237GPIO236GPIO235GPIO234GPIO233GPIO232
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO231GPIO230GPIO229GPIO228GPIO227GPIO226GPIO225GPIO224
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 15-115 GPHPUD Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W1hReserved
30RESERVEDR/W1hReserved
29RESERVEDR/W1hReserved
28RESERVEDR/W1hReserved
27RESERVEDR/W1hReserved
26RESERVEDR/W1hReserved
25GPIO249R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

24GPIO248R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

23GPIO247R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

22GPIO246R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

21GPIO245R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

20GPIO244R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

19GPIO243R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

18GPIO242R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

17GPIO241R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

16GPIO240R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

15GPIO239R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

14GPIO238R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

13GPIO237R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

12GPIO236R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

11GPIO235R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

10GPIO234R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

9GPIO233R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

8GPIO232R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

7GPIO231R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

6GPIO230R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

5GPIO229R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

4GPIO228R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

3GPIO227R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

2GPIO226R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

1GPIO225R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

0GPIO224R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

15.11.2.104 GPHINV Register (Offset = 3A0h) [Reset = 00000000h]

GPHINV is shown in Figure 15-107 and described in Table 15-116.

Return to the Summary Table.

GPIO H Input Polarity Invert Registers (GPIO224 to 255)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 15-107 GPHINV Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO249GPIO248
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO247GPIO246GPIO245GPIO244GPIO243GPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO239GPIO238GPIO237GPIO236GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO231GPIO230GPIO229GPIO228GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-116 GPHINV Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25GPIO249R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

24GPIO248R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

23GPIO247R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

22GPIO246R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

21GPIO245R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

20GPIO244R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

19GPIO243R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

18GPIO242R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

17GPIO241R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

16GPIO240R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

15GPIO239R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

14GPIO238R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

13GPIO237R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

12GPIO236R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

11GPIO235R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

10GPIO234R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

9GPIO233R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

8GPIO232R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

7GPIO231R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

6GPIO230R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

5GPIO229R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

4GPIO228R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

3GPIO227R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

2GPIO226R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

1GPIO225R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

0GPIO224R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

15.11.2.105 GPHODR Register (Offset = 3A4h) [Reset = 00000000h]

GPHODR is shown in Figure 15-108 and described in Table 15-117.

Return to the Summary Table.

GPIO H Open Drain Output Register (GPIO224 to GPIO255)

Selects between normal and open-drain output for the GPIO pin.

0: Normal Output
1: Open Drain Output

Reading the register returns the current value of the register setting.

Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.

Figure 15-108 GPHODR Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO249GPIO248
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO247GPIO246GPIO245GPIO244GPIO243GPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO239GPIO238GPIO237GPIO236GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO231GPIO230GPIO229GPIO228GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-117 GPHODR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25GPIO249R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

24GPIO248R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

23GPIO247R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

22GPIO246R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

21GPIO245R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

20GPIO244R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

19GPIO243R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

18GPIO242R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

17GPIO241R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

16GPIO240R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

15GPIO239R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

14GPIO238R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

13GPIO237R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

12GPIO236R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

11GPIO235R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

10GPIO234R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

9GPIO233R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

8GPIO232R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

7GPIO231R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

6GPIO230R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

5GPIO229R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

4GPIO228R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

3GPIO227R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

2GPIO226R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

1GPIO225R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

0GPIO224R/W0hOutpout Open-Drain control for this pin

Reset type: SYSRSn

15.11.2.106 GPHAMSEL Register (Offset = 3A8h) [Reset = 03FFFFFFh]

GPHAMSEL is shown in Figure 15-109 and described in Table 15-118.

Return to the Summary Table.

GPIO H Analog Mode Select register (GPIO224 to GPIO255)

Selects between digital and analog functionality for GPIO pins.

0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, t

Figure 15-109 GPHAMSEL Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO249GPIO248
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-1h
2322212019181716
GPIO247GPIO246GPIO245GPIO244GPIO243GPIO242GPIO241GPIO240
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO239GPIO238GPIO237GPIO236GPIO235GPIO234GPIO233GPIO232
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO231GPIO230GPIO229GPIO228GPIO227GPIO226GPIO225GPIO224
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 15-118 GPHAMSEL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25GPIO249R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

24GPIO248R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

23GPIO247R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

22GPIO246R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

21GPIO245R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

20GPIO244R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

19GPIO243R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

18GPIO242R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

17GPIO241R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

16GPIO240R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

15GPIO239R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

14GPIO238R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

13GPIO237R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

12GPIO236R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

11GPIO235R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

10GPIO234R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

9GPIO233R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

8GPIO232R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

7GPIO231R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

6GPIO230R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

5GPIO229R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

4GPIO228R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

3GPIO227R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

2GPIO226R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

1GPIO225R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

0GPIO224R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

15.11.2.107 GPHGMUX1 Register (Offset = 3C0h) [Reset = 00000000h]

GPHGMUX1 is shown in Figure 15-110 and described in Table 15-119.

Return to the Summary Table.

GPIO H Peripheral Group Mux (GPIO224 to 239)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 15-110 GPHGMUX1 Register
3130292827262524
GPIO239GPIO238GPIO237GPIO236
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO231GPIO230GPIO229GPIO228
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-119 GPHGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO239R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO238R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO237R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO236R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO235R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO234R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO233R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO232R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO231R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO230R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO229R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO228R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO227R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO226R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO225R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO224R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.108 GPHGMUX2 Register (Offset = 3C4h) [Reset = 00000000h]

GPHGMUX2 is shown in Figure 15-111 and described in Table 15-120.

Return to the Summary Table.

GPIO H Peripheral Group Mux (GPIO240 to 255)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 15-111 GPHGMUX2 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDGPIO249GPIO248
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO247GPIO246GPIO245GPIO244
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO243GPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-120 GPHGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18GPIO249R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO248R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO247R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO246R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO245R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO244R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO243R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO242R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO241R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO240R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15.11.2.109 GPHCSEL1 Register (Offset = 3D0h) [Reset = 00000000h]

GPHCSEL1 is shown in Figure 15-112 and described in Table 15-121.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-112 GPHCSEL1 Register
31302928272625242322212019181716
GPIO231GPIO230GPIO229GPIO228
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-121 GPHCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO231R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO230R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO229R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO228R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO227R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO226R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO225R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO224R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.110 GPHCSEL2 Register (Offset = 3D4h) [Reset = 00000000h]

GPHCSEL2 is shown in Figure 15-113 and described in Table 15-122.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-113 GPHCSEL2 Register
31302928272625242322212019181716
GPIO239GPIO238GPIO237GPIO236
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-122 GPHCSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO239R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO238R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO237R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO236R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO235R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO234R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO233R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO232R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.111 GPHCSEL3 Register (Offset = 3D8h) [Reset = 00000000h]

GPHCSEL3 is shown in Figure 15-114 and described in Table 15-123.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-114 GPHCSEL3 Register
31302928272625242322212019181716
GPIO247GPIO246GPIO245GPIO244
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO243GPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-123 GPHCSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO247R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO246R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO245R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO244R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO243R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO242R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO241R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO240R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.112 GPHCSEL4 Register (Offset = 3DCh) [Reset = 00000000h]

GPHCSEL4 is shown in Figure 15-115 and described in Table 15-124.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE/DIR registers control this GPIO pin

0000: CPU1 selected
0001: CPU2 selected
0010: CPU3 selected
0011: CPU4 selected (Reserved)
0100: CPU5 selected (Reserved)
0101: CPU6 selected (Reserved)
1xxx: (Reserved)

Figure 15-115 GPHCSEL4 Register
31302928272625242322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
RESERVEDRESERVEDGPIO249GPIO248
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-124 GPHCSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0hReserved
27-24RESERVEDR/W0hReserved
23-20RESERVEDR/W0hReserved
19-16RESERVEDR/W0hReserved
15-12RESERVEDR/W0hReserved
11-8RESERVEDR/W0hReserved
7-4GPIO249R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO248R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15.11.2.113 GPHLOCK Register (Offset = 3F8h) [Reset = 00000000h]

GPHLOCK is shown in Figure 15-116 and described in Table 15-125.

Return to the Summary Table.

GPIO H Lock Configuration Register (GPIO224 to 255)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 15-116 GPHLOCK Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO249GPIO248
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO247GPIO246GPIO245GPIO244GPIO243GPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO239GPIO238GPIO237GPIO236GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO231GPIO230GPIO229GPIO228GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-125 GPHLOCK Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25GPIO249R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

24GPIO248R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

23GPIO247R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

22GPIO246R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

21GPIO245R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

20GPIO244R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

19GPIO243R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

18GPIO242R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

17GPIO241R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

16GPIO240R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15GPIO239R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14GPIO238R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

13GPIO237R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

12GPIO236R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

11GPIO235R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

10GPIO234R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

9GPIO233R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

8GPIO232R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

7GPIO231R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

6GPIO230R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

5GPIO229R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

4GPIO228R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

3GPIO227R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

2GPIO226R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

1GPIO225R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

0GPIO224R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15.11.2.114 GPHCR Register (Offset = 3FCh) [Reset = 00000000h]

GPHCR is shown in Figure 15-117 and described in Table 15-126.

Return to the Summary Table.

GPIO H Lock Commit Register (GPIO224 to 255)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 15-117 GPHCR Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO249GPIO248
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
GPIO247GPIO246GPIO245GPIO244GPIO243GPIO242GPIO241GPIO240
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
GPIO239GPIO238GPIO237GPIO236GPIO235GPIO234GPIO233GPIO232
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
GPIO231GPIO230GPIO229GPIO228GPIO227GPIO226GPIO225GPIO224
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 15-126 GPHCR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/WSonce0hReserved
30RESERVEDR/WSonce0hReserved
29RESERVEDR/WSonce0hReserved
28RESERVEDR/WSonce0hReserved
27RESERVEDR/WSonce0hReserved
26RESERVEDR/WSonce0hReserved
25GPIO249R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

24GPIO248R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

23GPIO247R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

22GPIO246R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

21GPIO245R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

20GPIO244R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

19GPIO243R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

18GPIO242R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

17GPIO241R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

16GPIO240R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

15GPIO239R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

14GPIO238R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

13GPIO237R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

12GPIO236R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

11GPIO235R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

10GPIO234R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

9GPIO233R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

8GPIO232R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

7GPIO231R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

6GPIO230R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

5GPIO229R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

4GPIO228R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

3GPIO227R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

2GPIO226R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

1GPIO225R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

0GPIO224R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn