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F29P329SM-Q1

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C29x 200MHz、Lockstep、符合功能安全、2MB 的車用 C2000 64 位元 MCU

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F29P329SM-Q1

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產品規格表 立即訂購

產品詳細資料

TI functional safety category Functional Safety-Compliant Operating temperature range (°C) to Rating Automotive
TI functional safety category Functional Safety-Compliant Operating temperature range (°C) to Rating Automotive
HTQFP (PZS) 100 196 mm² 14 x 14

Real-time Processing

  • Three C29x 64-bit CPUs (CPU1, CPU2, CPU3) running at 200MHz
    • 2x signal chain performance versus C28x with improved pipeline
    • Split lock and lockstep operating modes
  • C29x CPU architecture
    • Byte addressability
    • High-performance real-time control with low latency
    • High-performance DSP and general-purpose processing capabilities
    • VLIW CPU executes 1 to 8 instructions in parallel
    • Fully protected pipeline
    • 8/16/32/64-bit single-cycle memory operations, up to two 64-bit memory reads and one 64-bit memory write in a single-cycle
    • IEEE 32-bit and 64-bit floating operations
    • 32-bit and 64-bit trigonometric operations
    • HW interrupt prioritization and nesting
    • 11-cycle real-time interrupt response
    • Atomic operations with memory protection
    • Multi safe island code execution managed in hardware

Memory

  • 4MB of CPU-mappable flash (ECC-protected) capable of supporting Firmware Over the Air (FOTA) with A/B swap and LFU
  • 256KB of Data-only Flash (ECC-protected)
  • 452KB of RAM (ECC-protected)
  • Dedicated 512KB Flash and 40KB RAM memories for HSM (ECC-protected)
  • Built in ECC logic for system-wide safety

Safety Peripherals

  • CPU1 and CPU2 lockstep
    • CPU1 and CPU2 splitlock mode is also available (for applications not needing functional safety or using methods like Reciprocal Comparison with multiple CPUs)
  • Logic Power-On Self-Test (LPOST)
  • Memory Power-On Self-Test (MPOST)
  • Error Signaling Module (ESM)
  • Dual-clock Comparator (DCC)
  • Waveform Analyzer and Diagnostics (WADI)
  • Context-sensitive Memory and Peripheral Protection with SSU
  • Safety Interconnect (SIC)
  • Functional Safety-Compliant targeted
    • Developed for functional safety applications
    • Documentation to aid ISO 26262 and IEC 61508 system design will be available upon production release
    • Systematic capability up to ASIL D and SIL 3 targeted
    • Hardware capability up to ASIL D and SIL 3 targeted
  • Safety-related certification
    • ISO 26262 certification up to ASIL D and IEC 61508 SIL 3 by TÜV SÜD planned

Security

  • Hardware Security Module (HSM)
    • Independently running Arm Cortex-M4 based security controller subsystem at 100MHz
    • 512KB of flash (ECC-protected)
    • 36KB of RAM (ECC-protected)
    • Secure key storage
    • Secure BOOT
    • Secure Debug
    • Dedicated 8-channel Real-Time Direct Memory Access (RTDMA) controller
    • EVITA-full support
    • FOTA with A/B swap
    • Hardware cryptographic accelerators
      • Asymmetric cryptography - RSA, ECC, SM2
      • Symmetric cryptography - AES, SM4
      • Hash operations - SHA2, HMAC, SM3
      • True Random Number Generator
  • Safety and Security Unit (SSU)
    • Advanced Real-Time Safety and Security
      • 64 Memory Access Protection Ranges per CPU
      • Up to 15 user LINKs and 7 stack pointers per CPU for hardware code isolation
      • Power-on Self-test (POST) capability
      • FOTA and LFU support with rollback control

Analog Subsystem

  • Five Analog-to-Digital Converters (ADCs)
    • Two 16-bit ADCs, 1.19MSPS each
    • Three 12-bit ADCs, 3.92MSPS each
    • Up to 80 single-ended or 16 differential inputs
    • 40 redundant input channels for flexibility
    • Separate sample-and-hold (S/H) on each ADC for simultaneous sampling
    • Hardware post-processing of conversions
    • Hardware oversampling (up to 128x) and undersampling modes, with accumulation, averaging and outlier rejection
    • Programmable delay from SOC trigger to start of conversion
    • Ten ADC Safety Checkers for comparison of conversion results across multiple ADC modules
  • 12 windowed comparators with 12-bit Digital-to-Analog Converter (DAC) references
    • Connection options for internal temperature sensor and ADC reference
  • Two 12-bit buffered DAC outputs

Control Peripherals

  • 36 Pulse Width Modulator (PWM) channels, all with high-resolution capability (HRPWM)
    • Minimum Dead-Band Logic (MINDB)
    • Illegal Combo Logic (ICL) for standard and high resolution
    • Diode Emulation (DE) support
    • Multilevel shadowing on XCMP
  • Six Enhanced Capture (eCAP) modules
    • High-resolution Capture (HRCAP) available on two of the six eCAP modules
    • Two new monitor units for edge, pulse width and period that can be coupled with ePWM strobes and trip events
    • Increased 256 multiplexed capture inputs
    • New ADC SOC generation capability
  • Six Enhanced Quadrature Encoder Pulse (eQEP) modules
  • 16 Sigma-Delta Filter Module (SDFM) input channels, 2 independent filters per channel
  • Embedded Pattern Generator (EPG)
  • Configurable Logic Block (CLB)
    • Six tiles
    • Augments existing peripheral capability
    • Supports position manager solutions

Communications Peripherals

  • EtherCAT SubordinateDevice (or SubDevice) Controller (ESC)
  • Fast Serial Interface (FSI) with four transmitters and four receivers
  • Five high-speed (up to 50MHz) SPI ports (pin-bootable)
  • Six High-Speed Universal Asynchronous Receiver/Transmitters (UARTs) (pin-bootable)
  • Two I2C interfaces (pin-bootable)
  • Two Local Interconnect Network (LIN) (supports SCI)
  • Power-Management Bus (PMBus) interface (supports I2C)
  • Six Single Edge Nibble Transmission interface (SENT)
  • Six Controller Area Networks with Flexible Data Rate (CAN FD/MCAN) (pin-bootable)

Systems Peripherals

  • External Memory Interface (EMIF) with ASRAM and SDRAM support
  • Two 10-channel Real-Time Direct Memory Access (RTDMA) controllers with MPU
  • Up to 190 usable signal pins
    • 136 General-Purpose Input/Output (GPIO) pins
    • 80 analog pins (26 AGPIOs included in GPIOs)
    • 5V fail-safe and tolerant capability on 6 GPIOs for PMBUS/I2C/SENT support
  • Peripheral Interrupt Priority and Expansion (PIPE)
  • Low-power mode (LPM) support
  • Embedded Real-time Analysis and Diagnostic (ERAD)

Clock and System Control

  • On-chip crystal oscillator
  • Windowed watchdog timer module
  • Missing clock detection circuitry
  • 1.25V core, 3.3V I/O design
    • Internal VREG for 1.25V generation
    • Brownout reset (BOR) circuit

Package Options:

  • Lead-free, green packaging
  • 256-ball New Fine Pitch Ball Grid Array (nFBGA) [ZEX suffix], 13mm x 13mm/0.8mm pitch
  • 176-pin Thermally Enhanced Thin Quad Flatpack (HTQFP) [PTS suffix], 22mm x 22mm/0.4mm pitch
  • 144-pin HTQFP [RFS suffix],18mm x 18mm/0.4mm pitch
  • 100-pin HTQFP [PZS suffix],14mm x 14mm/0.4mm pitch

Recommended TPS653860-Q1 and TPS650366-Q1 Power Management ICs (PMIC)

  • Companion PMICs specially designed to meet device power supply requirements
  • Flexible mapping and factory programmed configurations to support different use cases
  • Functional safety compliant PMICs to support external voltage monitoring and watchdog timer MCU safety requirements

Temperature

  • Ambient (TA): –40°C to 125°C

Real-time Processing

  • Three C29x 64-bit CPUs (CPU1, CPU2, CPU3) running at 200MHz
    • 2x signal chain performance versus C28x with improved pipeline
    • Split lock and lockstep operating modes
  • C29x CPU architecture
    • Byte addressability
    • High-performance real-time control with low latency
    • High-performance DSP and general-purpose processing capabilities
    • VLIW CPU executes 1 to 8 instructions in parallel
    • Fully protected pipeline
    • 8/16/32/64-bit single-cycle memory operations, up to two 64-bit memory reads and one 64-bit memory write in a single-cycle
    • IEEE 32-bit and 64-bit floating operations
    • 32-bit and 64-bit trigonometric operations
    • HW interrupt prioritization and nesting
    • 11-cycle real-time interrupt response
    • Atomic operations with memory protection
    • Multi safe island code execution managed in hardware

Memory

  • 4MB of CPU-mappable flash (ECC-protected) capable of supporting Firmware Over the Air (FOTA) with A/B swap and LFU
  • 256KB of Data-only Flash (ECC-protected)
  • 452KB of RAM (ECC-protected)
  • Dedicated 512KB Flash and 40KB RAM memories for HSM (ECC-protected)
  • Built in ECC logic for system-wide safety

Safety Peripherals

  • CPU1 and CPU2 lockstep
    • CPU1 and CPU2 splitlock mode is also available (for applications not needing functional safety or using methods like Reciprocal Comparison with multiple CPUs)
  • Logic Power-On Self-Test (LPOST)
  • Memory Power-On Self-Test (MPOST)
  • Error Signaling Module (ESM)
  • Dual-clock Comparator (DCC)
  • Waveform Analyzer and Diagnostics (WADI)
  • Context-sensitive Memory and Peripheral Protection with SSU
  • Safety Interconnect (SIC)
  • Functional Safety-Compliant targeted
    • Developed for functional safety applications
    • Documentation to aid ISO 26262 and IEC 61508 system design will be available upon production release
    • Systematic capability up to ASIL D and SIL 3 targeted
    • Hardware capability up to ASIL D and SIL 3 targeted
  • Safety-related certification
    • ISO 26262 certification up to ASIL D and IEC 61508 SIL 3 by TÜV SÜD planned

Security

  • Hardware Security Module (HSM)
    • Independently running Arm Cortex-M4 based security controller subsystem at 100MHz
    • 512KB of flash (ECC-protected)
    • 36KB of RAM (ECC-protected)
    • Secure key storage
    • Secure BOOT
    • Secure Debug
    • Dedicated 8-channel Real-Time Direct Memory Access (RTDMA) controller
    • EVITA-full support
    • FOTA with A/B swap
    • Hardware cryptographic accelerators
      • Asymmetric cryptography - RSA, ECC, SM2
      • Symmetric cryptography - AES, SM4
      • Hash operations - SHA2, HMAC, SM3
      • True Random Number Generator
  • Safety and Security Unit (SSU)
    • Advanced Real-Time Safety and Security
      • 64 Memory Access Protection Ranges per CPU
      • Up to 15 user LINKs and 7 stack pointers per CPU for hardware code isolation
      • Power-on Self-test (POST) capability
      • FOTA and LFU support with rollback control

Analog Subsystem

  • Five Analog-to-Digital Converters (ADCs)
    • Two 16-bit ADCs, 1.19MSPS each
    • Three 12-bit ADCs, 3.92MSPS each
    • Up to 80 single-ended or 16 differential inputs
    • 40 redundant input channels for flexibility
    • Separate sample-and-hold (S/H) on each ADC for simultaneous sampling
    • Hardware post-processing of conversions
    • Hardware oversampling (up to 128x) and undersampling modes, with accumulation, averaging and outlier rejection
    • Programmable delay from SOC trigger to start of conversion
    • Ten ADC Safety Checkers for comparison of conversion results across multiple ADC modules
  • 12 windowed comparators with 12-bit Digital-to-Analog Converter (DAC) references
    • Connection options for internal temperature sensor and ADC reference
  • Two 12-bit buffered DAC outputs

Control Peripherals

  • 36 Pulse Width Modulator (PWM) channels, all with high-resolution capability (HRPWM)
    • Minimum Dead-Band Logic (MINDB)
    • Illegal Combo Logic (ICL) for standard and high resolution
    • Diode Emulation (DE) support
    • Multilevel shadowing on XCMP
  • Six Enhanced Capture (eCAP) modules
    • High-resolution Capture (HRCAP) available on two of the six eCAP modules
    • Two new monitor units for edge, pulse width and period that can be coupled with ePWM strobes and trip events
    • Increased 256 multiplexed capture inputs
    • New ADC SOC generation capability
  • Six Enhanced Quadrature Encoder Pulse (eQEP) modules
  • 16 Sigma-Delta Filter Module (SDFM) input channels, 2 independent filters per channel
  • Embedded Pattern Generator (EPG)
  • Configurable Logic Block (CLB)
    • Six tiles
    • Augments existing peripheral capability
    • Supports position manager solutions

Communications Peripherals

  • EtherCAT SubordinateDevice (or SubDevice) Controller (ESC)
  • Fast Serial Interface (FSI) with four transmitters and four receivers
  • Five high-speed (up to 50MHz) SPI ports (pin-bootable)
  • Six High-Speed Universal Asynchronous Receiver/Transmitters (UARTs) (pin-bootable)
  • Two I2C interfaces (pin-bootable)
  • Two Local Interconnect Network (LIN) (supports SCI)
  • Power-Management Bus (PMBus) interface (supports I2C)
  • Six Single Edge Nibble Transmission interface (SENT)
  • Six Controller Area Networks with Flexible Data Rate (CAN FD/MCAN) (pin-bootable)

Systems Peripherals

  • External Memory Interface (EMIF) with ASRAM and SDRAM support
  • Two 10-channel Real-Time Direct Memory Access (RTDMA) controllers with MPU
  • Up to 190 usable signal pins
    • 136 General-Purpose Input/Output (GPIO) pins
    • 80 analog pins (26 AGPIOs included in GPIOs)
    • 5V fail-safe and tolerant capability on 6 GPIOs for PMBUS/I2C/SENT support
  • Peripheral Interrupt Priority and Expansion (PIPE)
  • Low-power mode (LPM) support
  • Embedded Real-time Analysis and Diagnostic (ERAD)

Clock and System Control

  • On-chip crystal oscillator
  • Windowed watchdog timer module
  • Missing clock detection circuitry
  • 1.25V core, 3.3V I/O design
    • Internal VREG for 1.25V generation
    • Brownout reset (BOR) circuit

Package Options:

  • Lead-free, green packaging
  • 256-ball New Fine Pitch Ball Grid Array (nFBGA) [ZEX suffix], 13mm x 13mm/0.8mm pitch
  • 176-pin Thermally Enhanced Thin Quad Flatpack (HTQFP) [PTS suffix], 22mm x 22mm/0.4mm pitch
  • 144-pin HTQFP [RFS suffix],18mm x 18mm/0.4mm pitch
  • 100-pin HTQFP [PZS suffix],14mm x 14mm/0.4mm pitch

Recommended TPS653860-Q1 and TPS650366-Q1 Power Management ICs (PMIC)

  • Companion PMICs specially designed to meet device power supply requirements
  • Flexible mapping and factory programmed configurations to support different use cases
  • Functional safety compliant PMICs to support external voltage monitoring and watchdog timer MCU safety requirements

Temperature

  • Ambient (TA): –40°C to 125°C

The Functional Block Diagram shows the CPU system and associated peripherals.

The Functional Block Diagram shows the CPU system and associated peripherals.
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重要文件 類型 標題 格式選項 日期
* Data sheet F29H85x, F29P58x, and F29P32x Real-Time Microcontrollers datasheet (Rev. C) PDF | HTML 2025年 12月 10日
* Errata F29H85x, F29P58x, and F29P32x Real-Time MCUs Silicon Errata (Rev. C) PDF | HTML 2026年 3月 4日
Application note Functional Safety Concept in On-Board Charger System PDF | HTML 2026年 1月 7日
User guide F29H85x and F29P58x Real-Time Microcontrollers Technical Reference Manual (Rev. A) PDF | HTML 2025年 12月 23日
Application note Live Firmware Update on F29x MCUs PDF | HTML 2025年 12月 4日
User guide C29 Software Optimization Guide (Rev. B) PDF | HTML 2025年 11月 17日
White paper Integrating EVCC, DCDC, and Host Architecture: TI Automotive MCUs for Next-Generation EV Charging (Rev. A) PDF | HTML 2025年 11月 13日
Product overview Automotive Functional Safety for C2000™ Real-Time Microcontrollers (Rev. F) 2025年 10月 9日
Application note Implementing Run-Time Safety and Security With the C29x Safety and Security Unit (Rev. A) PDF | HTML 2025年 10月 3日
Application note F29x Error Handling and Debug Guide PDF | HTML 2025年 9月 11日
Application note Second Sourcing Solution for 0.4 mm Pitch and 0.5 mm Pitch QFP Packages 2025年 8月 19日
Application note EEPROM Emulation for Generation 3 C2000 Real-Time Controllers (Rev. B) PDF | HTML 2025年 8月 13日
Application note MCU Control Center Tool Developer's Guide PDF | HTML 2025年 8月 4日
Application note MCU Signal Sight Tool Developer's Guide PDF | HTML 2025年 8月 1日
User guide C2000 Real-Time Control Peripheral Reference Guide (Rev. U) PDF | HTML 2025年 7月 11日
User guide F29H85x Flash API User's Guide (Rev. A) PDF | HTML 2025年 7月 1日
Application note C2000-IDE Assist Tool Migration Feature Guide PDF | HTML 2025年 4月 23日
Product overview Industrial Functional Safety for C2000™ Real-Time Microcontrollers (Rev. F) 2025年 4月 23日
User guide C29x CPU Reference Guide (Rev. A) PDF | HTML 2025年 3月 28日
Application brief C2000 F29H85x and F29P58x Real-Time Microcontrollers PDF | HTML 2025年 2月 18日
Application note C2000 IDE Assist Tool Features Guide (Rev. A) PDF | HTML 2025年 1月 29日
Application note EEPROM Emulation Driver Guide for C29x PDF | HTML 2025年 1月 9日
Application note DLT Developer's Guide With Tooling PDF | HTML 2024年 12月 23日
Application note Serial Flash Programming of F29H85x™ PDF | HTML 2024年 12月 23日
User guide Migration Between TMS320F28P65x and TMS320F29H85x PDF | HTML 2024年 11月 15日
White paper Enabling Cybersecurity for High Performance Real-Time Control Systems with C2000™ F29x Microcontrollers PDF | HTML 2024年 11月 8日
Application brief Optimize EPS System with C2000 F29 MCU PDF | HTML 2024年 11月 8日
User guide Application Software Migration to the C29 CPU User's Guide PDF | HTML 2024年 10月 24日
White paper The C29 CPU – Unrivaled Real-Time Performance with Optimized Architecture on C2000 MCUs PDF | HTML 2024年 10月 14日
Application brief Discrete Power Design for C2000™ PDF | HTML 2024年 8月 15日
Application note Development Tool Versions for C2000™ Support (Rev. A) PDF | HTML 2024年 6月 26日
Product overview Implementing IEC 60730 / UL 1998 Compliance for C2000 Real-Time Microcontrollers (Rev. A) PDF | HTML 2024年 6月 25日
Application note Obtain UL/IEC 60730-1/60335-1 Class B Certification Based on C2000™ MCU Diagnostic Library in Appliances PDF | HTML 2024年 5月 30日
Application note Power Supply and Monitoring Solution for C2000 MCU Automotive Applications PDF | HTML 2024年 4月 17日
Application note CAN Flash Programming of C2000™ Microcontrollers (Rev. A) PDF | HTML 2024年 4月 15日
Application note Clock Edge Delay Compensation With Isolated Modulators Digital Interface to MCUs (Rev. A) PDF | HTML 2024年 1月 12日
White paper Achieving High Efficiency and Enabling Integration in EV Powertrain Subsystems (Rev. A) PDF | HTML 2023年 7月 17日
Application note CRC Engines in C2000 Devices (Rev. A) PDF | HTML 2023年 5月 1日
Application note ADC Input Circuit Evaluation for C2000 MCUs (using TINA-TI simulation tool) (Rev. A) PDF | HTML 2023年 3月 24日
Application note ADC Input Circuit Evaluation for C2000 Real-Time MCUs (using PSPICE-FOR-TI) PDF | HTML 2023年 3月 24日
Application note Charge-Sharing Driving Circuits for C2000 ADCs (using PSPICE-FOR-TI) (Rev. A) PDF | HTML 2023年 3月 24日
Application note Charge-Sharing Driving Circuits for C2000 ADCs (using TINA-TI simulation tool) (Rev. A) PDF | HTML 2023年 3月 24日
Application note Methods for Mitigating ADC Memory Cross-Talk (Rev. A) PDF | HTML 2023年 3月 24日
Application note Using SMI of C2000 EtherCAT Slave Controller for Ethernet PHY Configuration PDF | HTML 2023年 2月 27日
Application note C2000 ePWM Developer’s Guide (Rev. A) PDF | HTML 2023年 2月 24日
Application note How to Implement Custom Serial Interfaces Using Configurable Logic Block (CLB) PDF | HTML 2023年 2月 3日
Application note C2000 SysConfig Linker Command Tool PDF | HTML 2023年 1月 26日
Application note Using the Fast Serial Interface (FSI) With Multiple Devices in an Application (Rev. E) PDF | HTML 2023年 1月 25日
Application note Diagnosing Delta-Sigma Modulator Bitstream Using C2000™ Configurable Logic Block PDF | HTML 2022年 12月 19日
User guide Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) (Rev. C) PDF | HTML 2022年 6月 29日
Application note Implement three-phase interleaved LLC on C2000 Type-4 PWM PDF | HTML 2022年 3月 30日
Application note The Essential Guide for Developing With C2000 Real-Time Microcontrollers (Rev. F) PDF | HTML 2022年 3月 3日
Application note Real-Time Benchmarks Showcasing C2000™ Control MCU's Optimized Signal Chain (Rev. A) PDF | HTML 2021年 12月 15日
Application note Achieve Delayed Protection for Three-Level Inverter With Type 4 EPWM PDF | HTML 2021年 10月 29日
Application note C2000 SysConfig PDF | HTML 2021年 10月 20日
Application note Getting Started with the MCAN (CAN FD) Module PDF | HTML 2021年 10月 20日
Application note Achieve Delayed Protection for Three-Level Inverter With CLB PDF | HTML 2021年 6月 28日
Application note Programming Examples for the DCAN Module (Rev. A) PDF | HTML 2021年 5月 20日
Application note Leverage New Type ePWM Features for Multiple Phase Control PDF | HTML 2021年 5月 11日
Application note CRM/ZVS PFC Implementation Based on C2000 Type-4 PWM Module PDF | HTML 2021年 2月 18日
More literature Maximize density, power, and reliability with TI GaN and C2000™ real-time MCUs 2020年 12月 15日
Application note C2000™ Unique Device Number (Rev. B) PDF | HTML 2020年 9月 17日
Application note Secure BOOT On C2000 Device 2020年 7月 21日
Application note How to Migrate Custom Logic From an FPGA/CPLD to C2000 Microcontrollers (Rev. A) 2020年 6月 15日
Application note EtherCAT Based Connected Servo Drive using Fast Current Loop on PMSM (Rev. B) PDF | HTML 2020年 2月 19日
White paper Distributed Power Control Architecture w/ C2000 MCUs Over Fast Serial Interface PDF | HTML 2020年 2月 14日
E-book E-book: An engineer’s guide to industrial robot designs 2020年 2月 12日
Application note Configurable Error Generator for Controller Area Network PDF | HTML 2019年 12月 19日
Application note Leveraging High Resolution Capture (HRCAP) for Single Wire Data Transfer PDF | HTML 2019年 8月 28日
Application note Fast Integer Division – A Differentiated Offering From C2000 Product Family PDF | HTML 2019年 6月 14日
Application note Calculating Useful Lifetimes of Embedded Processors (Rev. B) PDF | HTML 2019年 5月 7日
Application note Embedded Real-Time Analysis and Response for Control Applications PDF | HTML 2019年 3月 29日
Application note Designing With The C2000 Configurable Logic Block 2019年 2月 5日
Application note MSL Ratings and Reflow Profiles (Rev. A) 2018年 12月 13日
Application note Fast Serial Interface (FSI) Skew Compensation 2018年 11月 8日
White paper Maximizing power for Level 3 EV charging stations 2018年 6月 12日
Application note Calculating FIT for a Mission Profile 2015年 3月 24日

設計與開發

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開發板

F29H85X-SOM-EVM — F29H85x controlSOM 評估模組

若要評估 F29H85X-SOM-EVM，需要單獨購買 XDS110ISO-EVM 偵錯探針。

可選擇性單獨購買 HSEC180ADAPEVM 和 TMDSHSECDOCK，以便與 controlCARD 型平台向後相容。

F29H85X-SOM-EVM 是一款適合 TI C2000™ F29H85x 和 F29P58x 裝置 MCU 系列的評估和開發電路板。此系統模組設計非常適合初始評估和原型設計。

使用指南: PDF | HTML
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開發板

HSEC180ADAPEVM — HSEC180 轉接器電路板，適用於系統模組 (SOM) 型平台

此評估模組是用於 TI C2000™ 系統模組平台的 180 針腳高速邊緣卡 (HSEC) 轉接器，允許 SOM 型平台與 C2000 HSEC 型 EVM 向下相容。HSEC180ADAPEVM 可將來自 SOM 電路板的 180 針腳連接至 HSEC 針腳，以便與舊版 C2000 HSEC 擴充底座 (如 TMDSHSECDOCK) 一起使用。HSEC180ADAPEVM 還具有兩個 DP83826 10/100Mbps 工業乙太網路 PHY，用於評估 C2000 微控制器 SOM 平台上的 EtherCAT® 功能。

使用指南: PDF | HTML
TI.com 無法提供
軟體開發套件 (SDK)

F29H85X-MCAL-SDK — Microcontroller Abstraction Layer (MCAL) and Complex Device Drivers (CDD) for F29H85x

The F29x SDKs support the C29x cpu based family of real time MCUs. Together, these SDKs provide comprehensive software packages for the development of high-performance real-time control applications. The SDKs enable easy integration of host functionality together with the control, safety and (...)

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F29H85X-TIFS-SDK — F29H85x foundational security software

The F29x SDKs support the C29x cpu based family of real time MCUs. Together, these SDKs provide comprehensive software packages for the development of high-performance real-time control applications. The SDKs enable easy integration of host functionality together with the control, safety and (...)

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IDE、配置、編譯器或偵錯程式

EDGE-AI-STUDIO-MCU — Edge AI Studio for Microcontrollers

Edge AI Studio is part of the CCStudio™ development tool ecosystem.  Edge AI Studio is a collection of graphical and command line tools designed to accelerate edge AI development on TI processors, microcontrollers, connectivity devices and radar sensors.  It supports both AI-accelerated (...)

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線上培訓

C29X-ACADEMY — C29X-ACADEMY

The C29x Academy is a great resource for developers to learn about C29-based C2000 real-time microcontrollers. The Academy delivers informational training modules as well as hands-on lab exercises that span a variety of topics.
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軟體程式設計工具

UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash is a software tool for programming on-chip flash on TI microcontrollers and wireless connectivity devices and on-board flash for TI processors. UniFlash provides both graphical and command-line interfaces.

UniFlash can be run from the cloud on the TI Developer Zone or downloaded and used (...)

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模擬型號

F29H859TU-Q1 BSDL Model

SPRM872.ZIP (14 KB) - BSDL Model
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設計工具

F29-SCHEMATIC-DESIGN-TOOL — Hardware schematic checklist for F29-based designs.

Hardware schematic checklist for F29-based designs.
支援產品和硬體

支援產品和硬體
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
HTQFP (PZS) 100 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

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