首頁 微控制器 (MCU) 與處理器 微處理器和 DSP 音訊與雷達 DSP SoC
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微控制器 (MCU) 與處理器
微處理器和 DSP
音訊與雷達 DSP SoC

DRA726

現行

適用於車載資訊娛樂系統與儀錶板且具有圖形與 DSP 的 1.5 GHz Arm Cortex-A15

立即訂購
產品規格表
使用指南

DRA726

現行
立即訂購

產品詳細資料

CPU 1 Arm Cortex-A15 Frequency (MHz) 1500 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 1 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 2 PCIe Gen 2 Hardware accelerators Audio tracking logic, Image video accelerator, Viterbi decoder Features Multimedia Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
CPU 1 Arm Cortex-A15 Frequency (MHz) 1500 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 1 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 2 PCIe Gen 2 Hardware accelerators Audio tracking logic, Image video accelerator, Viterbi decoder Features Multimedia Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCBGA (ABC) 760 529 mm² (23 mm × 23 mm)
  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video inputs and video outputs
    • 2D and 3D graphics
  • Arm® Cortex®-A15 microprocessor subsystem
  • C66x floating-point VLIW DSP cores
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512KB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • DDR3/DDR3L External Memory Interface (EMIF) module
    • Supports up to DDR3-1333 (667 MHz)
    • Up to 2GB across single chip select
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Single-core PowerVR™ SGX544 3D GPU
  • One Video Input Port (VIP) module
    • Support for up to four multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-Port Gigabit Ethernet switch
    • Up to two external ports
  • Sixteen 32-bit general-purpose timers
  • 32-bit MPU watchdog timer
  • Six high speed Inter-Integrated Circuit (I2C™) ports
  • HDQ/1-Wire® interface
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad Serial Peripheral Interface (QSPI)
  • Media Local Bus subsystem (MLBSS)
  • Real-Time Clock subsystem (RTCSS)
  • SATA interface
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • High Speed USB 2.0 dual-role device
  • High Speed USB 2.0 on-the-go
  • Four MultiMedia Card/Secure Digital®/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
  • PCI-Express® (PCIe®) revision 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B Protocol
  • MIPI® Camera Serial Interface 2 (CSI-2)
  • Up to 215 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG lock
    • Secure keys
    • Secure ROM and Boot
    • Customer programmable keys (Silicon Revision 2.1)
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)
  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video inputs and video outputs
    • 2D and 3D graphics
  • Arm® Cortex®-A15 microprocessor subsystem
  • C66x floating-point VLIW DSP cores
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512KB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • DDR3/DDR3L External Memory Interface (EMIF) module
    • Supports up to DDR3-1333 (667 MHz)
    • Up to 2GB across single chip select
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Single-core PowerVR™ SGX544 3D GPU
  • One Video Input Port (VIP) module
    • Support for up to four multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-Port Gigabit Ethernet switch
    • Up to two external ports
  • Sixteen 32-bit general-purpose timers
  • 32-bit MPU watchdog timer
  • Six high speed Inter-Integrated Circuit (I2C™) ports
  • HDQ/1-Wire® interface
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad Serial Peripheral Interface (QSPI)
  • Media Local Bus subsystem (MLBSS)
  • Real-Time Clock subsystem (RTCSS)
  • SATA interface
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • High Speed USB 2.0 dual-role device
  • High Speed USB 2.0 on-the-go
  • Four MultiMedia Card/Secure Digital®/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
  • PCI-Express® (PCIe®) revision 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B Protocol
  • MIPI® Camera Serial Interface 2 (CSI-2)
  • Up to 215 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG lock
    • Secure keys
    • Secure ROM and Boot
    • Customer programmable keys (Silicon Revision 2.1)
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)

DRA72x ("Jacinto™ 6 Eco") infotainment applications processors are developed on the same architecture as Jacinto 6 devices to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

DRA72x devices offer upward scalability to DRA74x devices, while being pin-compatible across the family, allowing Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 and Jacinto 6 Eco devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution.

Programmability is provided by a single-core Arm® Cortex®-A15 RISC CPU with Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm® processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm®, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment is available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA72x Jacinto 6 Eco processor family is qualified according to the AEC-Q100 standard.

DRA72x ("Jacinto™ 6 Eco") infotainment applications processors are developed on the same architecture as Jacinto 6 devices to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

DRA72x devices offer upward scalability to DRA74x devices, while being pin-compatible across the family, allowing Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 and Jacinto 6 Eco devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution.

Programmability is provided by a single-core Arm® Cortex®-A15 RISC CPU with Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm® processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm®, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment is available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA72x Jacinto 6 Eco processor family is qualified according to the AEC-Q100 standard.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 DRA72x Infotainment Applications Processor Silicon Revision 2.0 and 2.1 datasheet (Rev. H) PDF | HTML 2019/7/24
* 使用指南 DRA71x and DRA72x Technical Reference Manual (Rev. D) 2019/5/21
* 勘誤表 DRA72x and DRA71x SoC for Automotive Infortainment Silicon Errata (Rev. F) PDF | HTML 2024/9/8
應用說明 Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 2021/5/5
應用說明 IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 2020/8/24
白皮書 Jump Start Upgrading Your Digital Cluster Design with Jacinto 6 Platform (Rev. A) 2020/8/17
應用說明 AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 2020/1/6
應用說明 Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 2019/6/11
應用說明 Achieving Early CAN Response on DRA7xx Devices 2018/11/28
應用說明 DRA74x_75x/DRA72x Performance (Rev. A) 2018/10/31
應用說明 Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 2018/9/14
應用說明 The Implementation of YUV422 Output for SRV 2018/8/2
應用說明 MMC DLL Tuning (Rev. B) 2018/7/31
應用說明 Integrating AUTOSAR on TI SoC: Fundamentals 2018/6/18
應用說明 ECC/EDC on TDAxx (Rev. B) 2018/6/13
應用說明 Tools and Techniques to Root Case Failures in Video Capture Subsystem 2018/6/12
應用說明 Sharing VPE Between VISIONSDK and PSDKLA 2018/5/4
應用說明 Android Boot Optimization on DRA7xx Devices (Rev. A) 2018/2/13
技術文章 Jacinto™ DRA automotive processors drive digital cockpit solutions PDF | HTML 2018/1/12
應用說明 Flashing Utility - mflash 2018/1/9
應用說明 Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 2017/11/30
應用說明 Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) 2017/11/27
應用說明 Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 2017/11/7
應用說明 A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 2017/11/3
應用說明 Robust Rear-View Camera (RVC) App Report 2017/9/13
應用說明 Optimization of GPU-Based Surround View on TI’s TDA2x SoC 2017/9/12
應用說明 Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 2017/8/14
應用說明 Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 2017/7/12
白皮書 Revolutionize the automotive cockpit 2017/6/2
應用說明 Linux Boot Time Optimizations on DRA7xx Devices 2017/3/31
應用說明 Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 2017/2/17
應用說明 Early Splash Screen on DRA7x Devices 2017/1/31
應用說明 Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 2016/12/15
使用指南 DM369 Camera Starter Kit (CSK) User's Guide 2016/12/15
EVM User's guide DRA72x EVM CPU Board User's Guide 2016/12/7
應用說明 Gstreamer Migration Guidelines 2016/4/26
使用指南 Jacinto6 Android Video Encoder Software Design Specification User's Guide 2016/4/21
使用指南 Jacinto6 Android Video Decoder Software Design Specification User's Guide 2016/4/21
應用說明 Flashing Binaries to DRA7xx Factory Boards Using DFU 2016/4/14
應用說明 Tools and Techniques for Audio Debugging 2016/4/13
應用說明 Debugging Tools and Techniques With IPC3.x 2016/3/30
技術文章 Infotainment for the Masses – Volkswagen MIB II Standard powered by TI PDF | HTML 2016/2/17
應用說明 Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 2016/1/15
技術文章 Securing the Scene PDF | HTML 2015/12/16
應用說明 Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 2014/8/13
白皮書 Today’s high-end infotainment soon becoming mainstream 2014/6/2

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

軟體開發套件 (SDK)

PROCESSOR-SDK-ANDROID-AUTOMOTIVE-DRA7X

處理器 SDK Linux Automotive

處理器 SDK Linux Automotive 是 TI 的 Jacinto™ DRAx 資訊娛樂系統 SoC 系列的基礎軟體開發平台。軟體架構可讓使用者開發功能豐富的車載資訊娛樂系統解決方案，例如新一代汽車適用之可重新配置的數位儀表總成、整合式駕駛艙、車內資訊娛樂系統、無線數據通訊、後座娛樂等。SDK 是以通用處理器 SDK 平台為基礎。

焦點
  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) 工具鏈
  • Yocto Project™ OE Core 相容檔案系統
(...)
支援產品和硬體
軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X — PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X

處理器 SDK Linux Automotive

處理器 SDK Linux Automotive 是 TI 的 Jacinto™ DRAx 資訊娛樂系統 SoC 系列的基礎軟體開發平台。軟體架構可讓使用者開發功能豐富的車載資訊娛樂系統解決方案，例如新一代汽車適用之可重新配置的數位儀表總成、整合式駕駛艙、車內資訊娛樂系統、無線數據通訊、後座娛樂等。SDK 是以通用處理器 SDK 平台為基礎。

焦點
  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) 工具鏈
  • Yocto Project™ OE Core 相容檔案系統
(...)
支援產品和硬體
軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-AUTOMOTIVE-DRA7X

處理器 SDK Linux Automotive

處理器 SDK Linux Automotive 是 TI 的 Jacinto™ DRAx 資訊娛樂系統 SoC 系列的基礎軟體開發平台。軟體架構可讓使用者開發功能豐富的車載資訊娛樂系統解決方案，例如新一代汽車適用之可重新配置的數位儀表總成、整合式駕駛艙、車內資訊娛樂系統、無線數據通訊、後座娛樂等。SDK 是以通用處理器 SDK 平台為基礎。

焦點
  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) 工具鏈
  • Yocto Project™ OE Core 相容檔案系統
(...)
支援產品和硬體
IDE、配置、編譯器或偵錯程式

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

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作業系統 (OS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
支援產品和硬體
支援軟體

VCTR-3P-MICROSAR — 適用於微控制器和高性能電腦 (HPC) 的 Vector MICROSAR AUTOSAR 軟體

MICROSAR 與 DaVinci 產品系列透過適用於微控制器與 HPC 的精密嵌入式軟體和強大開發工具，簡化 ECU 開發。有了先進的基礎架構軟體，您即可為 ECU 建立最佳基礎，並利用相關工具簡化所有相關開發作業。MICROSAR 嵌入式軟體是根據 AUTOSAR 經典和適應性等相關標準所開發。軟體也適合符合最高 ASIL D 之 ISO 26262 標準的安全相關應用。此外，智慧網路安全功能可保護控制單元免受未經授權的存取和竄改。Vector 涵蓋所有汽車與其他工業應用的使用案例。對於配備高性能電腦的軟體定義車輛 (SDV)，其可提供現代車輛作業系統，以做為開放式模組化軟體生態系統。

從：Vector Informatik GmbH
支援產品和硬體
模擬型號

DRA72x BSDL

SPRM684.ZIP (13 KB) - BSDL 模型
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模擬型號

DRA72x IBIS

SPRM683.ZIP (12619 KB) - IBIS 模型
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模擬型號

DRA72x Thermal Model

SPRM681.ZIP (1 KB) - 熱模型
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計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (ABC) 760 Ultra Librarian
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