15 Revision History
Changes from March 3, 2022 to April 30, 2026 (from Revision A (March 2022) to Revision B (April 2026))
- Introduction: Removed under-construction noticeGo
- Introduction: Expanded WKUP domain definitionGo
- Introduction: Updated to MMA2F in block diagramGo
- Introduction: Added Single and Dual core options to C7x introductory description. Updated MMA name. Removed DRU data compressionGo
- Update number of rings supported.Go
- Removed authentication from the OSPI supported features, renamed On-The-Fly Authentication (OTFA) references with On-The-Fly Encryption (OTFE).Go
- I2C FIFO size is not programmable, fixed size of 32 Bytes.Go
- Change 4-bit wide data bus from one to two controllers.Go
- Introduction: Added note about other name for SPIGo
- Remove SuperSpeed as it is not supported.Go
- I2C FIFO size is not programmable, fixed size of 32
Bytes.Go
- Introduction: Updated Device Identification for new part numbers Go
- Memory Map: Removed under-construction noticeGo
- Memory Map: Updated note about C7x Memory View to include details on MMU mappingGo
- Memory Map: Update summary to use consistent region name formatting Go
- Interconnect: Removed under-construction noticeGo
- Added Interrupts section with GICSS, GPIOMUX_INTROUTER, CMP_EVENT_INTROUTERGo
- Integration: Removed under-construction noticeGo
- Integration: Updated CTRL_MMR0 to MAIN_CTRL_MMR0Go
- Correct numbering of Terperature Sensors.Go
- Added PGD Hardware Requests to Module Integration.Go
- Add AUDIO_EXT_REFCLK0 and AUDIO_EXT_REFCLK1 to MCASP Clocks.Go
- Add Multi-drop and 9-bit mode to unsupported features.Go
- Remove 'Baud rates above 3.6864Mbaud'. Add '12Mbps not supported for MCU and WKUP domains.'Go
- Integration: removed unused instances from UART Unsupported Features
Go
- Integration: Added unsupported OSPI features listGo
- Integration: Added HyperBus information to FSS tables Go
- Add High Speed DDR to Unsupported features.Go
- Remove High Speed DDR from 8-bit MMC0Go
- Integration: removed unused instances from MCAN Unsupported Features
Go
- Update
RTC Unsupported FeaturesGo
- Added
"Two digital voltage domains" in section RTC
Unsupported Features Go
- Add Input/MUX and DCCCLKSRCx Value Columns.Go
- Integration: removed unused instances from ESM Unsupported Features
Go
- Initialization: Removed under-construction noticeGo
- Changed Public ROM Code executable from initial power up to after a cold or warm reset.Go
- Boot: Updated to more generic DEVSTAT register format nameGo
- Boot: Removed non-applicable items from B7Go
- Boot: Removed non-applicable items from B13Go
- Remove "_" from PADCONFIGx Register name.Go
- Boot: Added xSPI Bootloader OperationGo
- Boot: Added QSPI Bootloader Operation subsectionGo
- Remove "_" from PADCONFIGx Register name.Go
- Remove "_" from PADCONFIGx Register name.Go
- Initialization: Added reference to new tablesGo
- Initialization: Added tables that explain PLL Configurations values Go
- Remove "_" from PADCONFIGx Register name.Go
- Device Configuration: Removed under-construction noticeGo
- Device Configuration: Updated titles and reference to chapter titles Go
- Update delay from ns to us for entries 54-63.Go
- Device Configuration: Updating CTRL_MMR and PSC names to latest instance namesGo
- VTM: Removed unused domain and added a sentence about VTM registers in VTM Summaries Go
- Reset and Naming Alignment (WARMRESET->WARMRST) (DMSC->DMSC-L) (MMR0->MMR)Go
- MCU/MAIN domain nomenclature standardizationGo
- Device Reset Sources Table: Updated SW_MCU_WARMRSTz corresponding
register name in Register column from MMR to
MCU_CTRL_MMR_CFG0_RST_CTRLGo
- CTRLMMR Register Link UpdatesGo
- Reset Overview: Added register name of register
(MCU_CTRL_MMR_CFG0_RST_CTRL) that bit field SW_MCU_WARMRST[11:8] is contained
inGo
- Change MCU_HFOSC0 to HFOSC0Go
- Clocks: Replaced Top-Level Clock Diagram with high resolution versionGo
- Added AUDIO_EXT_REFCLK[1:0] with description.Go
- Device Configuration: Update register chapter name to latest name - CTRL_MMR RegistersGo
- Changed MCU_HFOSC0 to HFOSC0.Go
- Rename MCU_CLK_12M_RC to CLK_12M_RC for consistency.Go
- Update WKUP_CLKOUT0 Mux Diagram to remove divider. Go
- Update register bit name to CLKOUT_CTRL_WKUP_CLKOUT_SEL.Go
- Device Configuration: Update chapter name referencesGo
- Rename
MCU_RC_OSC_12M to CLK_12M_RC for
consistency.Go
- Change MCU_HFOSC0 to HFOSC0.Go
- Change
MCU_HFOSC0 to HFOSC0.Go
- Rename
MCU_RC_OSC_12M to CLK_12M_RC for
consistency.Go
- Change MCU_HFOSC0* to HFOSC0*Go
- Rename MCU_CLK_12M_RC and MCU_RC_OSC_12M to CLK-12M_RC for
consistency.Go
- PLL: Made a note of reserved PLL HSDIVs Go
- Device Configuration: update PLL CLKSEL Register names and numbersGo
- Update figure so that FOUTPOSTDIV is routed to HSDIV[5-9] and FOUTP
is routed to HSDIV[0-4]Go
- Update register
names.Go
- Update PLL Domains for SSMOD.Go
- Change MCU_HFOSC0 to HFOSC0.Go
- Added brown out note.Go
- Add PLL Integer calibration enabled recommendation.Go
- Change MCU_HFOSC0 to HFOSC0.Go
- Processors and Accelerators: Removed under-construction noticeGo
- Added Unsupported Features section.Go
- [R5FSS] Added Remote L2 Cache (RL2) sectionGo
- [R5FSS] Added Fast Local Copy (FLC) sectionGo
- Updated R5FSS Master Interfaces section.Go
- Added Note to CPU Output Compare Block section.Go
- Updated Note in VIM Lockstep Mode section.Go
- DSP: Updated MMA version name to MMA2FGo
- IPC: Removed under-construction noticeGo
- Secure Proxy moved to Interprocessor Communications
Chapter.Go
- Memory Controllers: Removed under-construction noticeGo
- Interrupts: Removed under-construction noticeGo
- Removed TimeSync SupportGo
- Interrupts: Update CTRL_MMR0 to MAIN_CTRL_MMR0Go
- Interrupts: Update CTRL_MMR0 to MAIN_CTRL_MMR0Go
- Add RX State Mapping TableGo
- Add TX State Mapping TableGo
- Add BCDMA Mapping TableGo
- Update Transfer Request Packet Descriptor Layout.Go
- DMSS: Update allocation tables to include applicable domainsGo
- DMSS: Removed incompleted sentences and add details on section descriptionsGo
- Update number of rings supported.Go
- SPI: Removed duplicate feature topics in PDMA OverviewGo
- PDMA: Updated number of simultaneous Rx and Tx channels supported , from 3 to 2Go
- Peripherals: Removed under-construction noticeGo
- ASRC: Added tables for RXSYNC and TXSYNCGo
- Rename PRU_ICSSG to PRUSS.Go
- Added Unsupported Features section.Go
- Added ATL Ports section.Go
- MLBSS: Removed registers not applicable to the deviceGo
- Create note to see Module Integration section about which GPIO pins
are supported.Go
- Add clarification of
GPIO interrupt generation.Go
- Genericize I2C statements.Go
- I2C: Genericize I2C Module imageGo
- I2C: Updated note under I2C Block Diagram to clarify the i variablesGo
- I2C: Updated note in I2C Clocking to clarify the i variablesGo
- I2C: Updated subsection reference to parent of the subsection Go
- Registers names updated within SPI chapter.Go
- MCSPI: Removed note referencing non-applicable registersGo
- MCSPI: MCSPI Interface Signals in Controller Mode updated to a more generic imageGo
- MCSPI: Update MCSPI Channels to show as CH(i) instead of CHi.Go
- SPI: Basic MCSPI Pins for Peripheral Mode table and diagrams updated to be nire generic Go
- Add addition information to Polarity and Phase regarding data
transfer.Go
- Rename PRU_ICSSG to PRUSSGo
- SPI: Update Global Initialization of Surrounding Modues to mention not all modules are applicable Go
- Added RX, TX, CTS and RTS signals to main domain. Go
- UART: changed description in System Using RS-485 Communication to better align with UART instance used in section's imageGo
- Signal names added to UART I/O Signals TableGo
- UART: Changed IrDA Mode Interface Signals image and paragraph to be more genericGo
- UART: Made CIR Mode Interface Signals diagram and paragraph more genericGo
- Updated the UART Baud Rate Settings table for baud rate up to
12Mbps.Go
- Update DLL and DLH Hex values associated with 160MHz and 192MHz
Source Clock.Go
- Register name updates within CPSW3G
Chapter.Go
- CPSW: Update interface mode registers to more generic name. Go
- CPSW: Updated RMII clocking register to more generic nameGo
- CPSW: Updated CPSW CPTS CLKSEL to generic bit nameGo
- CPSW: Change to generic CPTS_CLKSEL nameGo
- Update Event FIFO depth from 10 to 32.Go
- Add PORT2 to TX INFO Word 3 Format, SRD_ID fieldGo
- Add Port 2 to RX INFO Word 2, TO_PORT field.Go
- CPSW: updated to generic names for ENET1_CTRL and ENET2_CTRLGo
- FSS: Move the FSS Introduction to be after the section's table of contents. Re-organized the OSPI bullet points into separate bullet points for clarity. Moved a table that outlines mode of operations and allowed interfaces to the intro sectionGo
- FSS: Removed a duplicate allocation table and allocation paragraph for FSS0Go
- FSS: Updated FSS Environment to mention other FSS0 namesGo
- FSS: Updated FSS I/O Signals to point to a subsection that covers the OSPI signals as a whole instead of a specific table. Go
- FSS: Cleaned up references to other chaptersGo
- FSS: Updated Boot Size Configuration to point to CTRL_MMR RegistersGo
- FSS1: Removed duplicate overview paragraphs and duplicate sections on unsupported features. Updated diagram to remove reference to unused domains and ospi. Go
- FSS1: Removed references to unused OSPI1Go
- FSS: Updated FSS1 Typical Application images and tables to use more generic instance namesGo
- FSS: Removed FSS Allowed Interface Combinations to improve clarity of chapter as whole. Condensed list to reduce duplicate information. Removed Modes of Operation subsection because information got moved to a different a subsection. Made Block diagram more generic and clear.Go
- Update register names in OSPI Chapter.Go
- OSPI: Added new subsections to the chapter - OSPI PHY Modiule, PHY Pipeline Mode, Read Data Capturing by the PHY ModuleGo
- FSS/OSPI: Added new sections about OSPI to help explain OSPI items from FSS diagramsGo
- Maximum bytes
supported by STIG is 16.Go
- FSS and HyperBus: Added new subsections about HyperBus to provide more details for FSSGo
- FSS: Added sections to provide in-depth details about HyperBusGo
- Added HyperBus Not Supported
Features section.Go
- HyperBus: Adding HyperRAM and HyperFlash Programming guideGo
- MMCSD Chapter modified to be more generic. Specifics included in module
Integration section.Go
- Fixed typo of SDIO version from 4.0 to 3.0.Go
- Add 3.3V to Legacy MMC, High Speed SDR and High Speed DDR MMC
Support.Go
- IO Signals made generic for different device types.Go
- Remove 33 Ω resistor requirement from MMCi_CLK.Go
- MMCSD IO Multiplexer figure added.Go
- EPWM I/O Signals Figure and Table updated to be generic for all
devices.Go
- EPW: Updated instance counts and register names for Time-Base ClocksGo
- Fix statement regarding Case 1 and Case 4.Go
- ADC: Updated Overview to be more generic Go
- Added Unsupported Features section.Go
- Updated ADC I/O Signals table.Go
- ADC: Replaced registers with more generic names Go
- Added AFE Functional Block DiagramGo
- Updated AFE Functional Block DiagramGo
- Update register names in GTC Chapter.Go
- GTC: Updated CLKSEL register name Go
- Added steps to Clear GTC Counter.Go
- Update register names in chapter.Go
- Change 32768 MHz to 32768Hz.Go
- Change 32768 MHz to 32768Hz.Go
- Update register names in chapter.Go
- Timers: Updated paragraph to clarify instance counts. Updated register reference to register name instead of register regionGo
- Add "sourced from the LFOSC" to the bullet: Generated a 1ms
tick.Go
- Hard code registers.Go
- Add note that 32-kHz clock is sourced from the
LFOSC.Go
- Hard code registers. Add Module Integration reference for
unsupported features.Go
- Hard code registers.Go
- Hard code registers.Go
- Hard code registersGo
- Hard Code registersGo
- Hard code registersGo
- Hard code registersGo
- Hard code registersGo
- Hard code registersGo
- Hard code registersyesGo
- Hard code registers.Go
- Register names updated within Chapter.Go
- DCC: Update note and image to be genericGo
- Hard
code registersGo
- Updated block diagram to be generic and include all domains. See
datasheet for specifics.Go
- Fix broken links to footnotes.Go
- Debug: Removed under-construction noticeGo
- Registers: Fixed various links in the subsections. Updated RTI instances in Timer subsectionGo
- Registers: Removed under-construction notice and updated registers name to clearer formatGo
- Registers: Changed a chapter titleGo
- PDMA Registers: Added note about instance counts Go