SPRUJC6B October 2025 – April 2026 AM2752-Q1 , AM2754-Q1
Time Stamp Counter Register
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| Instance Name | Physical Address |
|---|---|
| ECAP0 | 2310 0000h |
| ECAP1 | 2311 0000h |
| ECAP2 | 2312 0000h |
| ECAP3 | 2313 0000h |
| ECAP4 | 2314 0000h |
| ECAP5 | 2315 0000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TSCNT | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TSCNT | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TSCNT | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TSCNT | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | TSCNT | R/W | 0h | Active 32 bit Counter register which is used as the Capture time-base Reset Source: vbus_rst_mod_g_rst_n |