SPRUJC6B October 2025 – April 2026 AM2752-Q1 , AM2754-Q1
Counter Timer IRQSTATUS Register. This bit clears the interrupt event. SW can also read this bit to indicate that the interrupt is active and enabled. This register exists only if NUMTIMR > 0
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 8C08h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TIM_INTN_IE | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TIM_INTN_IE | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TIM_INTN_IE | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TIM_INTN_IE | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | TIM_INTN_IE | R/W | 0h | IRQSTATUS value. The individual bits is this field correspond to individual interrupts generated for each timer associated with Counter Timer Control Register (CTCRn : INT). |