SPRUJ79A November   2024  – December 2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3.   ► C29x SYSTEM RESOURCES
    1.     Technical Reference Manual Overview
  4. 1 C29x Processor
    1. 1.1 CPU Architecture
      1. 1.1.1 C29x Related Collateral
    2. 1.2 Lock and Commit Registers
    3. 1.3 C29x CPU Registers
      1. 1.3.1 C29CPU Base Address Table
      2. 1.3.2 C29_RTINT_STACK Registers
      3. 1.3.3 C29_SECCALL_STACK Registers
      4. 1.3.4 C29_SECURE_REGS Registers
      5. 1.3.5 C29_DIAG_REGS Registers
      6. 1.3.6 C29_SELFTEST_REGS Registers
  5. 2 System Control and Interrupts
    1. 2.1  C29x System Control Introduction
    2. 2.2  System Control Functional Description
      1. 2.2.1 Device Identification
      2. 2.2.2 Device Configuration Registers
    3. 2.3  Resets
      1. 2.3.1 Reset Sources
      2. 2.3.2 External Reset (XRS)
      3. 2.3.3 Simulate External Reset
      4. 2.3.4 Power-On Reset (POR)
      5. 2.3.5 Debugger Reset (SYSRS)
      6. 2.3.6 Watchdog Reset (WDRS)
      7. 2.3.7 ESM NMI Watchdog Reset (NMIWDRS)
      8. 2.3.8 EtherCAT SubordinateDevice Controller (ESC) Module Reset Output
    4. 2.4  Interrupts
      1. 2.4.1 External Interrupts (XINT)
    5. 2.5  Safety Features
      1. 2.5.1 Write Protection on Registers
        1. 2.5.1.1 LOCK Protection on System Configuration Registers
        2. 2.5.1.2 EALLOW Protection
      2. 2.5.2 PIPE Vector Address Validity Check
      3. 2.5.3 NMIWDs
      4. 2.5.4 System Control Registers Parity Protection
      5. 2.5.5 ECC Enabled RAMs, Shared RAMs Protection
      6. 2.5.6 ECC Enabled Flash Memory
      7. 2.5.7 ERRORSTS Pin
    6. 2.6  Clocking
      1. 2.6.1 Clock Sources
        1. 2.6.1.1 Primary Internal Oscillator (INTOSC2)
        2. 2.6.1.2 Backup Internal Oscillator (INTOSC1)
        3. 2.6.1.3 External Oscillator (XTAL)
        4. 2.6.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 2.6.2 Derived Clocks
        1. 2.6.2.1 Oscillator Clock (OSCCLK)
        2. 2.6.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 2.6.3 Device Clock Domains
        1. 2.6.3.1 System Clock (PLLSYSCLK)
        2. 2.6.3.2 CPU Clock (CPUCLK)
        3. 2.6.3.3 Peripheral Clock (PERx.SYSCLK)
        4. 2.6.3.4 MCAN Bit Clock
        5. 2.6.3.5 CPU Timer2 Clock (TIMER2CLK)
      4. 2.6.4 External Clock Output (XCLKOUT)
      5. 2.6.5 Clock Connectivity
      6. 2.6.6 Using an External Crystal or Resonator
        1. 2.6.6.1 X1/X2 Precondition Circuit
      7. 2.6.7 PLL
        1. 2.6.7.1 System Clock Setup
        2. 2.6.7.2 SYS PLL Bypass
      8. 2.6.8 Clock (OSCCLK) Failure Detection
        1. 2.6.8.1 Missing Clock Detection Logic
        2. 2.6.8.2 Dual Clock Comparator (DCC)
    7. 2.7  Bus Architecture
      1. 2.7.1 Safe Interconnect
        1. 2.7.1.1 Safe Interconnect for Read Operation
        2. 2.7.1.2 Safe Interconnect for Write Operation
      2. 2.7.2 Peripheral Access Configuration using FRAMESEL
      3. 2.7.3 Bus Arbitration
    8. 2.8  32-Bit CPU Timers 0/1/2
    9. 2.9  Watchdog Timers
      1. 2.9.1 Servicing the Watchdog Timer
      2. 2.9.2 Minimum Window Check
      3. 2.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 2.9.4 Watchdog Operation in Low-Power Modes
      5. 2.9.5 Emulation Considerations
    10. 2.10 Low-Power Modes
      1. 2.10.1 IDLE
      2. 2.10.2 STANDBY
    11. 2.11 Memory Subsystem (MEMSS)
      1. 2.11.1 Introduction
      2. 2.11.2 Features
      3. 2.11.3 Configuration Bits
        1. 2.11.3.1 Memory Initialization
      4. 2.11.4 RAM
        1. 2.11.4.1  MEMSS Architecture
        2. 2.11.4.2  RAM Memory Controller Overview
        3. 2.11.4.3  Memory Controllers
          1. 2.11.4.3.1 128-Bit LPx and CPx Memory Controller
          2. 2.11.4.3.2 64-Bit LDx and CDx Memory Controller
          3. 2.11.4.3.3 M0 Memory Controller
        4. 2.11.4.4  RTDMA Burst Support
        5. 2.11.4.5  Atomic Memory Operations
        6. 2.11.4.6  RAM ECC
        7. 2.11.4.7  Read-Modify-Write Operations
        8. 2.11.4.8  Dataline Buffer
        9. 2.11.4.9  HSM Sync Bridge
        10. 2.11.4.10 Access Bridges
          1. 2.11.4.10.1 Debug Access Bridge
          2. 2.11.4.10.2 Global Access Bridge
          3. 2.11.4.10.3 Program Access Bridge
      5. 2.11.5 ROM
        1. 2.11.5.1 ROM Dataline Buffer
        2. 2.11.5.2 ROM Prefetch
      6. 2.11.6 Arbitration
      7. 2.11.7 Test Modes
      8. 2.11.8 Emulation Mode
    12. 2.12 System Control Register Configuration Restrictions
    13. 2.13 Software
      1. 2.13.1  SYSCTL Registers to Driverlib Functions
      2. 2.13.2  MEMSS Registers to Driverlib Functions
      3. 2.13.3  CPU Registers to Driverlib Functions
      4. 2.13.4  CPUTIMER Registers to Driverlib Functions
      5. 2.13.5  XINT Registers to Driverlib Functions
      6. 2.13.6  LPOST Registers to Driverlib Functions
      7. 2.13.7  SYSCTL Examples
        1. 2.13.7.1 Missing clock detection (MCD) - SINGLE_CORE
        2. 2.13.7.2 XCLKOUT (External Clock Output) Configuration - SINGLE_CORE
      8. 2.13.8  TIMER Examples
        1. 2.13.8.1 Timer Academy Lab - SINGLE_CORE
        2. 2.13.8.2 CPU Timers - SINGLE_CORE
        3. 2.13.8.3 CPU Timers - SINGLE_CORE
      9. 2.13.9  WATCHDOG Examples
        1. 2.13.9.1 Watchdog - SINGLE_CORE
      10. 2.13.10 LPM Examples
        1. 2.13.10.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO - SINGLE_CORE
        2. 2.13.10.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog - SINGLE_CORE
        3. 2.13.10.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO - SINGLE_CORE
        4. 2.13.10.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog - SINGLE_CORE
    14. 2.14 SYSCTRL Registers
      1. 2.14.1  SYSCTRL Base Address Table
      2. 2.14.2  DEV_CFG_REGS Registers
      3. 2.14.3  MEMSS_L_CONFIG_REGS Registers
      4. 2.14.4  MEMSS_C_CONFIG_REGS Registers
      5. 2.14.5  MEMSS_M_CONFIG_REGS Registers
      6. 2.14.6  MEMSS_MISCI_REGS Registers
      7. 2.14.7  SYNCBRIDGEMPU_REGS Registers
      8. 2.14.8  CPU_SYS_REGS Registers
      9. 2.14.9  CPU_PER_CFG_REGS Registers
      10. 2.14.10 WD_REGS Registers
      11. 2.14.11 CPUTIMER_REGS Registers
      12. 2.14.12 XINT_REGS Registers
  6. 3 ROM Code and Peripheral Booting
    1. 3.1 Introduction
      1. 3.1.1 ROM Related Collateral
    2. 3.2 Device Boot Sequence
    3. 3.3 Device Boot Modes
      1. 3.3.1 Default Boot Modes
      2. 3.3.2 Custom Boot Modes
    4. 3.4 Device Boot Configurations
      1. 3.4.1 Configuring Boot Mode Pins
      2. 3.4.2 Configuring Boot Mode Table Options
      3. 3.4.3 Boot Mode Example Use Cases
        1. 3.4.3.1 Zero Boot Mode Select Pins
        2. 3.4.3.2 One Boot Mode Select Pin
        3. 3.4.3.3 Three Boot Mode Select Pins
    5. 3.5 Device Boot Flow Diagrams
      1. 3.5.1 Device Boot Flow
      2. 3.5.2 CPU1 Boot Flow
      3. 3.5.3 Emulation Boot Flow
      4. 3.5.4 Standalone Boot Flow
    6. 3.6 Device Reset and Exception Handling
      1. 3.6.1 Reset Causes and Handling
      2. 3.6.2 Exceptions and Interrupts Handling
    7. 3.7 Boot ROM Description
      1. 3.7.1  Boot ROM Configuration Registers
        1. 3.7.1.1 MPOST and LPOST Configurations
      2. 3.7.2  Entry Points
      3. 3.7.3  Wait Points
      4. 3.7.4  Memory Maps
        1. 3.7.4.1 Boot ROM Memory-Maps
        2. 3.7.4.2 Reserved RAM Memory-Maps
      5. 3.7.5  BootROM SSU APRs
      6. 3.7.6  ROM Structure and Status Information
      7. 3.7.7  Boot Modes and Loaders
        1. 3.7.7.1 Boot Modes
          1. 3.7.7.1.1 Flash Boot
          2. 3.7.7.1.2 RAM Boot
          3. 3.7.7.1.3 Wait Boot
        2. 3.7.7.2 Bootloaders
          1. 3.7.7.2.1 SPI Boot Mode
          2. 3.7.7.2.2 I2C Boot Mode
          3. 3.7.7.2.3 Parallel Boot Mode
          4. 3.7.7.2.4 CAN Boot Mode
          5. 3.7.7.2.5 CAN-FD Boot Mode
          6. 3.7.7.2.6 UART Boot Mode
      8. 3.7.8  GPIO Assignments
      9. 3.7.9  HSM and C29x ROM Task Ownership and Interactions
        1. 3.7.9.1 Application Authentication by HSM
      10. 3.7.10 Boot Status Information
        1. 3.7.10.1 Booting Status
      11. 3.7.11 BootROM Timing
    8. 3.8 Software
      1. 3.8.1 BOOT Examples
  7. 4 Lockstep Compare Module (LCM)
    1. 4.1 Introduction
      1. 4.1.1 Features
      2. 4.1.2 Block Diagram
      3. 4.1.3 Lockstep Compare Modules
    2. 4.2 Enabling LCM Comparators
    3. 4.3 LCM Redundant Module Configuration
    4. 4.4 LCM Error Handling
    5. 4.5 Register Parity Error Protection
    6. 4.6 Functional Logic
      1. 4.6.1 Comparator Logic
      2. 4.6.2 Self-Test Logic
        1. 4.6.2.1 Match Test Mode
        2. 4.6.2.2 Mismatch Test Mode
      3. 4.6.3 Error Injection Tests
        1. 4.6.3.1 Comparator Error Force Test
        2. 4.6.3.2 Register Parity Error Test
    7. 4.7 Software
      1. 4.7.1 LCM Registers to Driverlib Functions
    8. 4.8 LCM Registers
      1. 4.8.1 LCM Base Address Table
      2. 4.8.2 LCM_REGS Registers
  8. 5 Peripheral Interrupt Priority and Expansion (PIPE)
    1. 5.1 Introduction
      1. 5.1.1 Features
      2. 5.1.2 Interrupt Concepts
      3. 5.1.3 PIPE Related Collateral
    2. 5.2 Interrupt Controller Architecture
      1. 5.2.1 Dynamic Priority Arbitration Block
      2. 5.2.2 Post Processing Block
      3. 5.2.3 Memory-Mapped Registers
    3. 5.3 Interrupt Propagation
    4. 5.4 Configuring Interrupts
      1. 5.4.1 Enabling and Disabling Interrupts
      2. 5.4.2 Prioritization
        1. 5.4.2.1 User-Configured Interrupt Priority
        2. 5.4.2.2 Index-Based Fixed Interrupt Priority
      3. 5.4.3 Interrupt Blocking
      4. 5.4.4 Nesting and Priority Grouping
      5. 5.4.5 Stack Protection
      6. 5.4.6 Context
      7. 5.4.7 Live Firmware Update (LFU) Vector Mapping
    5. 5.5 Safety and Security
      1. 5.5.1 Access Control
      2. 5.5.2 PIPE Errors
      3. 5.5.3 Register Data Integrity and Safety
      4. 5.5.4 Self-Test and Diagnostics
    6. 5.6 Software
      1. 5.6.1 PIPE Registers to Driverlib Functions
      2. 5.6.2 INTERRUPT Examples
        1. 5.6.2.1 RTINT vs INT Latency example - SINGLE_CORE
        2. 5.6.2.2 INT and RTINT Nesting Example - SINGLE_CORE
        3. 5.6.2.3 RTINT Nesting limit - SINGLE_CORE
    7. 5.7 PIPE Registers
      1. 5.7.1 PIPE Base Address Table
      2. 5.7.2 PIPE_REGS Registers
  9. 6  Error Aggregator
    1. 6.1 Introduction
    2. 6.2 Error Aggregator Modules
    3. 6.3 Error Propagation Path from Source to CPU
    4. 6.4 Error Aggregator Interface
      1. 6.4.1 Functional Description
    5. 6.5 Error Condition Handling User Guide
    6. 6.6 Error Type Information
    7. 6.7 Error Sources Information
    8. 6.8 Software
      1. 6.8.1 ERROR_AGGREGATOR Registers to Driverlib Functions
    9. 6.9 ERRORAGGREGATOR Registers
      1. 6.9.1 ERRORAGGREGATOR Base Address Table
      2. 6.9.2 HSM_ERROR_AGGREGATOR_CONFIG_REGS Registers
      3. 6.9.3 ERROR_AGGREGATOR_CONFIG_REGS Registers
  10. 7  Error Signaling Module (ESM_C29)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 ESM Related Collateral
    2. 7.2 ESM Subsystem
      1. 7.2.1 System ESM
        1. 7.2.1.1 Error Pin Monitor Event
      2. 7.2.2 Safety Aggregator
        1. 7.2.2.1 EDC Controller Interface Description
        2. 7.2.2.2 Read Operation on EDC Controller
        3. 7.2.2.3 Write Operation on EDC Controller
        4. 7.2.2.4 Safety Aggregator Error Injection
      3. 7.2.3 ESM Subsystem Integration View
    3. 7.3 ESM Functional Description
      1. 7.3.1 Error Event Inputs
      2. 7.3.2 Error Interrupt Outputs
        1. 7.3.2.1 High-Priority Watchdog
        2. 7.3.2.2 Critical-Priority Interrupt Output
      3. 7.3.3 Error Pin Output (ERR_O/ERRORSTS)
        1. 7.3.3.1 Minimum Time Interval
        2. 7.3.3.2 PWM Mode
      4. 7.3.4 Reset Type Information for ESM Registers
      5. 7.3.5 Clock Stop
      6. 7.3.6 Commit/Lock for MMRs
      7. 7.3.7 Safety Protection for MMRs
      8. 7.3.8 Register Configuration Tieoffs
        1. 7.3.8.1 Group0 High-Priority Tieoff
        2. 7.3.8.2 High-Priority Watchdog Enable Tieoff
    4. 7.4 ESM Configuration Guide
    5. 7.5 Interrupt Condition Control and Handling
      1. 7.5.1 ESM Low-Priority Error Interrupt
      2. 7.5.2 ESM High-Priority Error Interrupt
      3. 7.5.3 Critical-Priority Error Interrupt
      4. 7.5.4 High-Priority Watchdog Interrupt
      5. 7.5.5 Safety Aggregator Interrupt Control and Handling
    6. 7.6 Software
      1. 7.6.1 ESM_CPU Registers to Driverlib Functions
      2. 7.6.2 ESM_SYS Registers to Driverlib Functions
      3. 7.6.3 ESM_SAFETY_AGGREGATOR Registers to Driverlib Functions
      4. 7.6.4 ESM Examples
        1. 7.6.4.1 ESM Multicore Example (CPU1,CPU3) - MULTI_CORE
        2. 7.6.4.2 ESM Multicore Example (CPU1,CPU3) - MULTI_CORE
        3. 7.6.4.3 ESM - SINGLE_CORE
        4. 7.6.4.4 ESM - SINGLE_CORE
    7. 7.7 ESM Registers
      1. 7.7.1 ESM Base Address Table
      2. 7.7.2 ESM_CPU_REGS Registers
      3. 7.7.3 ESM_SYSTEM_REGS Registers
      4. 7.7.4 ESM_SAFETYAGG_REGS Registers
      5. 7.7.5 EDC_REGS Registers
  11. 8 Flash Module
    1. 8.1 Introduction to Flash Memory
      1. 8.1.1 FLASH Related Collateral
      2. 8.1.2 Features
      3. 8.1.3 Flash Tools
      4. 8.1.4 Block Diagram
    2. 8.2 Flash Subsystem Overview
    3. 8.3 Flash Banks and Pumps
    4. 8.4 Flash Read Interfaces
      1. 8.4.1 Bank Modes and Swapping
      2. 8.4.2 Flash Wait States
      3. 8.4.3 Buffer and Cache Mechanisms
        1. 8.4.3.1 Prefetch Mechanism and Block Cache
        2. 8.4.3.2 Data Line Buffer
        3. 8.4.3.3 Sequential Data Pre-read Mode
      4. 8.4.4 Flash Read Arbitration
      5. 8.4.5 Error Correction Code (ECC) Protection
      6. 8.4.6 Procedure to Change Flash Read Interface Registers
    5. 8.5 Flash Erase and Program
      1. 8.5.1 Flash Semaphore and Update Protection
      2. 8.5.2 Erase
      3. 8.5.3 Program
    6. 8.6 Read-While-Write Constraints
    7. 8.7 Migrating an Application from RAM to Flash
    8. 8.8 Flash Registers
      1. 8.8.1 FLASH Base Address Table
      2. 8.8.2 FLASH_CMD_REGS_FLC1 Registers
      3. 8.8.3 FLASH_CMD_REGS_FLC2 Registers
      4. 8.8.4 FRI_CTRL_REGS Registers
  12. 9 Safety and Security Unit (SSU)
    1. 9.1  Introduction
      1. 9.1.1 SSU Related Collateral
      2. 9.1.2 Block Diagram
      3. 9.1.3 System SSU Configuration Example
    2. 9.2  Access Protection Ranges
      1. 9.2.1 Access Protection Inheritance
    3. 9.3  LINKs
    4. 9.4  STACKs
    5. 9.5  ZONEs
    6. 9.6  SSU-CPU Interface
      1. 9.6.1 SSU Operation in Lockstep Mode
    7. 9.7  SSU Operation Modes
    8. 9.8  Security Configuration and Flash Management
      1. 9.8.1 BANKMGMT Sectors
      2. 9.8.2 SECCFG Sectors
      3. 9.8.3 SECCFG Sector Address Mapping
      4. 9.8.4 SECCFG Sector Memory Map
      5. 9.8.5 SECCFG CRC
    9. 9.9  Flash Write/Erase Access Control
      1. 9.9.1 Permanent Flash Lock (Write/Erase Protection)
      2. 9.9.2 Updating Flash MAIN Sectors
      3. 9.9.3 Firmware-Over-The-Air Updates (FOTA)
      4. 9.9.4 Updating Flash SECCFG Sectors
      5. 9.9.5 Reading Flash SECCFG Sectors
    10. 9.10 RAMOPEN Feature
    11. 9.11 Booting of CPU2 and CPU3
    12. 9.12 Debug Authorization
      1. 9.12.1 Global CPU Debug Enable
      2. 9.12.2 ZONE Debug
      3. 9.12.3 Authentication for Debug Access
        1. 9.12.3.1 Password-based Authentication
        2. 9.12.3.2 CPU-based Authentication
    13. 9.13 Hardcoded Protections
    14. 9.14 SSU Register Access Permissions
      1. 9.14.1 Permissions for SSU General Control Registers
      2. 9.14.2 Permissions for SSU CPU1 Configuration Registers
      3. 9.14.3 Permissions for SSU CPU2+ Configuration Registers
      4. 9.14.4 Permissions for CPU1 Access Protection Registers
      5. 9.14.5 Permissions for CPU2+ Access Protection Registers
    15. 9.15 SSU Fault Signals
    16. 9.16 Software
      1. 9.16.1 SSU Registers to Driverlib Functions
    17. 9.17 SSU Registers
      1. 9.17.1 SSU Base Address Table
      2. 9.17.2 SSU_GEN_REGS Registers
      3. 9.17.3 SSU_CPU1_CFG_REGS Registers
      4. 9.17.4 SSU_CPU2_CFG_REGS Registers
      5. 9.17.5 SSU_CPU3_CFG_REGS Registers
      6. 9.17.6 SSU_CPU1_AP_REGS Registers
      7. 9.17.7 SSU_CPU2_AP_REGS Registers
      8. 9.17.8 SSU_CPU3_AP_REGS Registers
    18. 9.18 C29DEBUGSS Registers
      1. 9.18.1 C29DEBUGSS Base Address Table
      2. 9.18.2 SECAP_HANDLER_REGS Registers
  13. 10Configurable Logic Block (CLB)
    1. 10.1  Introduction
      1. 10.1.1 CLB Related Collateral
    2. 10.2  Description
      1. 10.2.1 CLB Clock
    3. 10.3  CLB Input/Output Connection
      1. 10.3.1 Overview
      2. 10.3.2 CLB Input Selection
      3. 10.3.3 CLB Output Selection
      4. 10.3.4 CLB Output Signal Multiplexer
    4. 10.4  CLB Tile
      1. 10.4.1 Static Switch Block
      2. 10.4.2 Counter Block
        1. 10.4.2.1 Counter Description
        2. 10.4.2.2 Counter Operation
        3. 10.4.2.3 Serializer Mode
        4. 10.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 10.4.3 FSM Block
      4. 10.4.4 LUT4 Block
      5. 10.4.5 Output LUT Block
      6. 10.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 10.4.7 High Level Controller (HLC)
        1. 10.4.7.1 High Level Controller Events
        2. 10.4.7.2 High Level Controller Instructions
        3. 10.4.7.3 <Src> and <Dest>
        4. 10.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 10.5  CPU Interface
      1. 10.5.1 Register Description
      2. 10.5.2 Non-Memory Mapped Registers
    6. 10.6  RTDMA Access
    7. 10.7  CLB Data Export Through SPI RX Buffer
    8. 10.8  CLB Pipeline Mode
    9. 10.9  Software
      1. 10.9.1 CLB Registers to Driverlib Functions
      2. 10.9.2 CLB Examples
        1. 10.9.2.1 CLB Example Lab - SINGLE_CORE
        2. 10.9.2.2 CLB eCAP Example Lab - SINGLE_CORE
        3. 10.9.2.3 CLB Combinational Logic - SINGLE_CORE
        4. 10.9.2.4 CLB GPIO Input Filter - SINGLE_CORE
        5. 10.9.2.5 CLB Auxilary PWM - SINGLE_CORE
        6. 10.9.2.6 CLB PWM Protection - SINGLE_CORE
    10. 10.10 CLB Registers
      1. 10.10.1 CLB Base Address Table
      2. 10.10.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 10.10.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 10.10.4 CLB_DATA_EXCHANGE_REGS Registers
  14. 11Dual-Clock Comparator (DCC)
    1. 11.1 Introduction
      1. 11.1.1 Features
      2. 11.1.2 Block Diagram
    2. 11.2 Module Operation
      1. 11.2.1 Configuring DCC Counters
      2. 11.2.2 Single-Shot Measurement Mode
      3. 11.2.3 Continuous Monitoring Mode
      4. 11.2.4 Error Conditions
    3. 11.3 Interrupts
    4. 11.4 Software
      1. 11.4.1 DCC Registers to Driverlib Functions
      2. 11.4.2 DCC Examples
        1. 11.4.2.1 DCC Single shot Clock verification - SINGLE_CORE
        2. 11.4.2.2 DCC Single shot Clock measurement - SINGLE_CORE
        3. 11.4.2.3 DCC Continuous clock monitoring - SINGLE_CORE
    5. 11.5 DCC Registers
      1. 11.5.1 DCC Base Address Table
      2. 11.5.2 DCC_REGS Registers
  15. 12Real-Time Direct Memory Access (RTDMA)
    1. 12.1  Introduction
      1. 12.1.1 Features
      2. 12.1.2 RTDMA Related Collateral
      3. 12.1.3 Block Diagram
    2. 12.2  RTDMA Trigger Source Options
    3. 12.3  RTDMA Bus
    4. 12.4  Address Pointer and Transfer Control
    5. 12.5  Pipeline Timing and Throughput
    6. 12.6  Channel Priority
      1. 12.6.1 Round-Robin Mode
      2. 12.6.2 Software Configurable Priority of Channels
    7. 12.7  Overrun Detection Feature
    8. 12.8  Burst Mode
    9. 12.9  Safety and Security
      1. 12.9.1 Safety
        1. 12.9.1.1 Lockstep Mode
        2. 12.9.1.2 Memory Protection Unit (MPU)
          1. 12.9.1.2.1 MPU Errors
      2. 12.9.2 Security
      3. 12.9.3 RTDMA Errors
      4. 12.9.4 Self-Test and Diagnostics
    10. 12.10 Software
      1. 12.10.1 RTDMA Registers to Driverlib Functions
      2. 12.10.2 RTDMA Examples
        1. 12.10.2.1 RTDMA Academy Lab - SINGLE_CORE
        2. 12.10.2.2 RTDMA Transfer - SINGLE_CORE
        3. 12.10.2.3 RTDMA Transfer with MPU - SINGLE_CORE
        4. 12.10.2.4 RTDMA - MULTI_CORE
        5. 12.10.2.5 RTDMA Example - MULTI_CORE
        6. 12.10.2.6 RTDMA example with Resource Allocator - MULTI_CORE
        7. 12.10.2.7 RTDMA example with Resource Allocator - MULTI_CORE
    11. 12.11 RTDMA Registers
      1. 12.11.1 RTDMA Base Address Table
      2. 12.11.2 RTDMA_REGS Registers
      3. 12.11.3 RTDMA_DIAG_REGS Registers
      4. 12.11.4 RTDMA_SELFTEST_REGS Registers
      5. 12.11.5 RTDMA_MPU_REGS Registers
      6. 12.11.6 RTDMA_CH_REGS Registers
  16. 13External Memory Interface (EMIF)
    1. 13.1 Introduction
      1. 13.1.1 Purpose of the Peripheral
      2. 13.1.2 Features
        1. 13.1.2.1 Asynchronous Memory Support
        2. 13.1.2.2 Synchronous DRAM Memory Support
      3. 13.1.3 Functional Block Diagram
      4. 13.1.4 Configuring Device Pins
    2. 13.2 EMIF Module Architecture
      1. 13.2.1  EMIF Clock Control
      2. 13.2.2  EMIF Requests
      3. 13.2.3  EMIF Signal Descriptions
      4. 13.2.4  EMIF Signal Multiplexing Control
      5. 13.2.5  SDRAM Controller and Interface
        1. 13.2.5.1  SDRAM Commands
        2. 13.2.5.2  Interfacing to SDRAM
        3. 13.2.5.3  SDRAM Configuration Registers
        4. 13.2.5.4  SDRAM Auto-Initialization Sequence
        5. 13.2.5.5  SDRAM Configuration Procedure
        6. 13.2.5.6  EMIF Refresh Controller
          1. 13.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 13.2.5.7  Self-Refresh Mode
        8. 13.2.5.8  Power-Down Mode
        9. 13.2.5.9  SDRAM Read Operation
        10. 13.2.5.10 SDRAM Write Operations
        11. 13.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 13.2.6  Asynchronous Controller and Interface
        1. 13.2.6.1 Interfacing to Asynchronous Memory
        2. 13.2.6.2 Accessing Larger Asynchronous Memories
        3. 13.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 13.2.6.4 Read and Write Operations in Normal Mode
          1. 13.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 13.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 13.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 13.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 13.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 13.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 13.2.7  Data Bus Parking
      8. 13.2.8  Reset and Initialization Considerations
      9. 13.2.9  Interrupt Support
        1. 13.2.9.1 Interrupt Events
      10. 13.2.10 RTDMA Event Support
      11. 13.2.11 EMIF Signal Multiplexing
      12. 13.2.12 Memory Map
      13. 13.2.13 Priority and Arbitration
      14. 13.2.14 System Considerations
        1. 13.2.14.1 Asynchronous Request Times
      15. 13.2.15 Power Management
        1. 13.2.15.1 Power Management Using Self-Refresh Mode
        2. 13.2.15.2 Power Management Using Power Down Mode
      16. 13.2.16 Emulation Considerations
    3. 13.3 EMIF Subsystem (EMIFSS)
      1. 13.3.1 Burst Support
      2. 13.3.2 EMIFSS Performance Improvement
      3. 13.3.3 Buffer Module
        1. 13.3.3.1 CPU Write FIFO
      4. 13.3.4 Emulation Mode
    4. 13.4 Example Configuration
      1. 13.4.1 Hardware Interface
      2. 13.4.2 Software Configuration
        1. 13.4.2.1 Configuring the SDRAM Interface
          1. 13.4.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 13.4.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 13.4.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 13.4.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 13.4.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 13.4.2.2 Configuring the Flash Interface
          1. 13.4.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    5. 13.5 Software
      1. 13.5.1 EMIF Registers to Driverlib Functions
      2. 13.5.2 EMIF Examples
    6. 13.6 EMIF Registers
      1. 13.6.1 EMIF Base Address Table
      2. 13.6.2 EMIF_REGS Registers
  17. 14General-Purpose Input/Output (GPIO)
    1. 14.1  Introduction
      1. 14.1.1 GPIO Related Collateral
    2. 14.2  Configuration Overview
    3. 14.3  Digital Inputs on ADC Pins (AIOs)
    4. 14.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 14.5  Digital General-Purpose I/O Control
    6. 14.6  Input Qualification
      1. 14.6.1 No Synchronization (Asynchronous Input)
      2. 14.6.2 Synchronization to SYSCLKOUT Only
      3. 14.6.3 Qualification Using a Sampling Window
    7. 14.7  PMBUS and I2C Signals
    8. 14.8  GPIO and Peripheral Muxing
      1. 14.8.1 GPIO Muxing
      2. 14.8.2 Peripheral Muxing
    9. 14.9  Internal Pullup Configuration Requirements
    10. 14.10 Open-Drain Configuration Requirements
    11. 14.11 Software
      1. 14.11.1 GPIO Registers to Driverlib Functions
      2. 14.11.2 GPIO Examples
        1. 14.11.2.1 Device GPIO Toggle - SINGLE_CORE
        2. 14.11.2.2 XINT/XBAR example - SINGLE_CORE
        3. 14.11.2.3 External Interrupt (XINT) - SINGLE_CORE
      3. 14.11.3 LED Examples
        1. 14.11.3.1 LED Blinky Example - MULTI_CORE
        2. 14.11.3.2 LED Blinky Example (CPU1,CPU3) - MULTI_CORE
        3. 14.11.3.3 LED Blinky example - SINGLE_CORE
        4. 14.11.3.4 LED Blinky Example (CPU1|CPU2|CPU3) - MULTI_CORE
        5. 14.11.3.5 LED Blinky Example (CPU2) - MULTI_CORE
        6. 14.11.3.6 LED Blinky Example (CPU3) - MULTI_CORE
        7. 14.11.3.7 LED Blinky Example - MULTI_CORE
        8. 14.11.3.8 LED Blinky Example (CPU1,CPU3) - MULTI_CORE
    12. 14.12 GPIO Registers
      1. 14.12.1 GPIO Base Address Table
      2. 14.12.2 GPIO_CTRL_REGS Registers
      3. 14.12.3 GPIO_DATA_REGS Registers
      4. 14.12.4 GPIO_DATA_READ_REGS Registers
  18. 15Interprocessor Communication (IPC)
    1. 15.1 Introduction
    2. 15.2 IPC Flags and Interrupts
    3. 15.3 IPC Command Registers
    4. 15.4 Free-Running Counter
    5. 15.5 IPC Communication Protocol
    6. 15.6 Software
      1. 15.6.1 IPC Registers to Driverlib Functions
      2. 15.6.2 IPC Examples
        1. 15.6.2.1 IPC basic message passing example with interrupt - MULTI_CORE
        2. 15.6.2.2 IPC basic message passing example with interrupt - MULTI_CORE
        3. 15.6.2.3 IPC basic message passing example with interrupt - MULTI_CORE
        4. 15.6.2.4 IPC basic message passing example with interrupt - MULTI_CORE
        5. 15.6.2.5 IPC basic message passing example with interrupt - MULTI_CORE
        6. 15.6.2.6 IPC basic message passing example with interrupt - MULTI_CORE
    7. 15.7 IPC Registers
      1. 15.7.1 IPC Base Address Table
      2. 15.7.2 IPC_COUNTER_REGS Registers
      3. 15.7.3 CPU1_IPC_SEND_REGS Registers
      4. 15.7.4 CPU2_IPC_SEND_REGS Registers
      5. 15.7.5 CPU3_IPC_SEND_REGS Registers
      6. 15.7.6 CPU1_IPC_RCV_REGS Registers
      7. 15.7.7 CPU2_IPC_RCV_REGS Registers
      8. 15.7.8 CPU3_IPC_RCV_REGS Registers
  19. 16Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 16.1 Introduction
    2. 16.2 Enhanced Bus Comparator Unit
      1. 16.2.1 Enhanced Bus Comparator Unit Operations
      2. 16.2.2 Stack Qualification
      3. 16.2.3 Event Masking and Exporting
    3. 16.3 System Event Counter Unit
      1. 16.3.1 System Event Counter Modes
        1. 16.3.1.1 Counting Active Levels Versus Edges
        2. 16.3.1.2 Max and Min Mode
        3. 16.3.1.3 Cumulative Mode
        4. 16.3.1.4 Input Signal Selection
      2. 16.3.2 Reset on Event
      3. 16.3.3 Operation Conditions
    4. 16.4 Program Counter Trace
      1. 16.4.1 Built-in CCS™ Trace
      2. 16.4.2 Functional Block Diagram
      3. 16.4.3 Trace Qualification Modes
        1. 16.4.3.1 Trace Input Signal Conditioning
      4. 16.4.4 Trace Memory
      5. 16.4.5 PC Trace Software Operation
      6. 16.4.6 Trace Operation in Debug Mode
    5. 16.5 ERAD Ownership, Initialization, and Reset
      1. 16.5.1 Feature Level Ownership
      2. 16.5.2 Feature Access Security Mechanism
      3. 16.5.3 PC Trace Access Security Mechanism
    6. 16.6 ERAD Programming Sequence
      1. 16.6.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 16.6.2 Timer and Counter Programming Sequence
    7. 16.7 Software
      1. 16.7.1 ERAD Registers to Driverlib Functions
  20. 17Data Logger and Trace (DLT)
    1. 17.1 Introduction
      1. 17.1.1 Features
      2. 17.1.2 DLT Related Collateral
      3. 17.1.3 Interfaces
        1. 17.1.3.1 Block Diagram
    2. 17.2 Functional Overview
      1. 17.2.1 DLT Configuration
        1. 17.2.1.1 LINK Filter
        2. 17.2.1.2 TAG Filter
        3. 17.2.1.3 ERAD Event Trigger
        4. 17.2.1.4 Concurrent FILTERING modes
      2. 17.2.2 Time-stamping
      3. 17.2.3 FIFO Construction
        1. 17.2.3.1 FIFO Interrupt
    3. 17.3 Software
      1. 17.3.1 DLT Registers to Driverlib Functions
      2. 17.3.2 DLT Examples
        1. 17.3.2.1 DLT TAG filter example - SINGLE_CORE
        2. 17.3.2.2 DLT TAG filter example - SINGLE_CORE
        3. 17.3.2.3 DLT ERAD filter example - SINGLE_CORE
    4. 17.4 DLT Registers
      1. 17.4.1 DLT Base Address Table
      2. 17.4.2 DLT_CORE_REGS Registers
      3. 17.4.3 DLT_FIFO_REGS Registers
  21. 18Waveform Analyzer Diagnostic (WADI)
    1. 18.1 WADI Overview
      1. 18.1.1 Features
      2. 18.1.2 WADI Related Collateral
      3. 18.1.3 Block Diagram
      4. 18.1.4 Description
    2. 18.2 Signal and Trigger Input Configuration
      1. 18.2.1 SIG1 and SIG2 Configuration
      2. 18.2.2 Trigger 1 and Trigger 2
    3. 18.3 WADI Block
      1. 18.3.1 Overview
      2. 18.3.2 Counters
      3. 18.3.3 Pulse Width
        1. 18.3.3.1 Pulse Width Single Measurement
        2. 18.3.3.2 Pulse Width Aggregation
        3. 18.3.3.3 Pulse Width Average and Peak
      4. 18.3.4 Edge Count
        1. 18.3.4.1 Edge Count with Fixed Window
        2. 18.3.4.2 Edge Count with Moving Window
      5. 18.3.5 Signal1 to Signal2 Comparison
      6. 18.3.6 Dead Band and Phase
      7. 18.3.7 Simultaneous Measurement
    4. 18.4 Safe State Sequencer (SSS)
      1. 18.4.1 SSS Configuration
    5. 18.5 Lock and Commit Registers
    6. 18.6 Interrupt and Error Handling
    7. 18.7 RTDMA Interfaces
      1. 18.7.1 RTDMA Trigger
    8. 18.8 Software
      1. 18.8.1 WADI Registers to Driverlib Functions
      2. 18.8.2 WADI Examples
        1. 18.8.2.1 WADI Pulse Width Measurement - SINGLE_CORE
        2. 18.8.2.2 WADI Frequency Measurement - SINGLE_CORE
        3. 18.8.2.3 WADI Phase Overlap Measurement - SINGLE_CORE
        4. 18.8.2.4 WADI Deadband Measurement - SINGLE_CORE
        5. 18.8.2.5 WADI Frequency Measurement with SSS - SINGLE_CORE
        6. 18.8.2.6 WADI Pulse Wdith Check with DMA trigger - SINGLE_CORE
    9. 18.9 WADI Registers
      1. 18.9.1 WADI Base Address Table
      2. 18.9.2 WADI_CONFIG_REGS Registers
      3. 18.9.3 WADI_OPER_SSS_REGS Registers
  22. 19Crossbar (X-BAR)
    1. 19.1 X-BAR Related Collateral
    2. 19.2 Input X-BAR, ICL XBAR, MINDB XBAR
      1. 19.2.1 ICL and MINDB X-BAR
    3. 19.3 ePWM , CLB, and GPIO Output X-BAR
      1. 19.3.1 ePWM X-BAR
        1. 19.3.1.1 ePWM X-BAR Architecture
      2. 19.3.2 CLB X-BAR
        1. 19.3.2.1 CLB X-BAR Architecture
      3. 19.3.3 GPIO Output X-BAR
        1. 19.3.3.1 GPIO Output X-BAR Architecture
      4. 19.3.4 X-BAR Flags
    4. 19.4 Software
      1. 19.4.1 INPUT_XBAR Registers to Driverlib Functions
      2. 19.4.2 EPWM_XBAR Registers to Driverlib Functions
      3. 19.4.3 CLB_XBAR Registers to Driverlib Functions
      4. 19.4.4 OUTPUT_XBAR Registers to Driverlib Functions
      5. 19.4.5 MDL_XBAR Registers to Driverlib Functions
      6. 19.4.6 ICL_XBAR Registers to Driverlib Functions
      7. 19.4.7 XBAR Registers to Driverlib Functions
      8. 19.4.8 XBAR Examples
        1. 19.4.8.1 Input XBAR to Output XBAR Connection - SINGLE_CORE
        2. 19.4.8.2 Output XBAR Pulse Stretch - SINGLE_CORE
    5. 19.5 XBAR Registers
      1. 19.5.1 XBAR Base Address Table
      2. 19.5.2 INPUT_XBAR_REGS Registers
      3. 19.5.3 EPWM_XBAR_REGS Registers
      4. 19.5.4 CLB_XBAR_REGS Registers
      5. 19.5.5 OUTPUTXBAR_REGS Registers
      6. 19.5.6 MDL_XBAR_REGS Registers
      7. 19.5.7 ICL_XBAR_REGS Registers
      8. 19.5.8 OUTPUTXBAR_FLAG_REGS Registers
      9. 19.5.9 XBAR_REGS Registers
  23. 20Embedded Pattern Generator (EPG)
    1. 20.1 Introduction
      1. 20.1.1 Features
      2. 20.1.2 EPG Block Diagram
      3. 20.1.3 EPG Related Collateral
    2. 20.2 Clock Generator Modules
      1. 20.2.1 DCLK (50% duty cycle clock)
      2. 20.2.2 Clock Stop
    3. 20.3 Signal Generator Module
    4. 20.4 EPG Peripheral Signal Mux Selection
    5. 20.5 Application Software Notes
    6. 20.6 EPG Example Use Cases
      1. 20.6.1 EPG Example: Synchronous Clocks with Offset
        1. 20.6.1.1 Synchronous Clocks with Offset Register Configuration
      2. 20.6.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 20.6.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 20.6.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 20.6.3.1 Serial Data Bit Stream (MSB first) Register Configuration
      4. 20.6.4 EPG Example: Clock and Data Pair
        1. 20.6.4.1 Clock and Data Pair Register Configuration
      5. 20.6.5 EPG Example: Clock and Skewed Data Pair
        1. 20.6.5.1 Clock and Skewed Data Pair Register Configuration
      6. 20.6.6 EPG Example: Capturing Serial Data with a Known Baud Rate
        1. 20.6.6.1 Capturing Serial Data with a Known Baud Rate Register Configuration
    7. 20.7 EPG Interrupt
    8. 20.8 Software
      1. 20.8.1 EPG Registers to Driverlib Functions
      2. 20.8.2 EPG Examples
        1. 20.8.2.1 EPG Generating Synchronous Clocks - SINGLE_CORE
        2. 20.8.2.2 EPG Generating Two Offset Clocks - SINGLE_CORE
        3. 20.8.2.3 EPG Generating Two Offset Clocks With SIGGEN - SINGLE_CORE
        4. 20.8.2.4 EPG Generate Serial Data - SINGLE_CORE
        5. 20.8.2.5 EPG Generate Serial Data Shift Mode - SINGLE_CORE
    9. 20.9 EPG Registers
      1. 20.9.1 EPG Base Address Table
      2. 20.9.2 EPG_REGS Registers
      3. 20.9.3 EPG_MUX_REGS Registers
  24.   ► ANALOG PERIPHERALS
    1.     Technical Reference Manual Overview
  25. 21Analog Subsystem
    1. 21.1 Introduction
      1. 21.1.1 Features
      2. 21.1.2 Block Diagram
    2. 21.2 Optimizing Power-Up Time
    3. 21.3 Digital Inputs on ADC Pins (AIOs)
    4. 21.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 21.5 Analog Pins and Internal Connections
    6. 21.6 Software
      1. 21.6.1 ASYSCTL Registers to Driverlib Functions
    7. 21.7 Lock Registers
    8. 21.8 ASBSYS Registers
      1. 21.8.1 ASBSYS Base Address Table
      2. 21.8.2 ANALOG_SUBSYS_REGS Registers
  26. 22Analog-to-Digital Converter (ADC)
    1. 22.1  Introduction
      1. 22.1.1 Features
      2. 22.1.2 ADC Related Collateral
      3. 22.1.3 Block Diagram
    2. 22.2  ADC Configurability
      1. 22.2.1 ADC Clock Configuration
      2. 22.2.2 Resolution
      3. 22.2.3 Voltage Reference
        1. 22.2.3.1 External Reference Mode
        2. 22.2.3.2 Internal Reference Mode
        3. 22.2.3.3 Ganged References
        4. 22.2.3.4 Selecting Reference Mode
      4. 22.2.4 Signal Mode
        1. 22.2.4.1 Expected Conversion Results
        2. 22.2.4.2 Interpreting Conversion Results
    3. 22.3  SOC Principle of Operation
      1. 22.3.1 ADC Sequencer
      2. 22.3.2 SOC Configuration
      3. 22.3.3 Trigger Operation
        1. 22.3.3.1 Global Software Trigger
        2. 22.3.3.2 Trigger Repeaters
          1. 22.3.3.2.1 Oversampling Mode
          2. 22.3.3.2.2 Undersampling Mode
          3. 22.3.3.2.3 Trigger Phase Delay
          4. 22.3.3.2.4 Re-trigger Spread
          5. 22.3.3.2.5 Trigger Repeater Configuration
            1. 22.3.3.2.5.1 Register Shadow Updates
          6. 22.3.3.2.6 Re-Trigger Logic
          7. 22.3.3.2.7 Multi-Path Triggering Behavior
      4. 22.3.4 ADC Acquisition (Sample and Hold) Window
      5. 22.3.5 ADC Input Models
      6. 22.3.6 Channel Selection
        1. 22.3.6.1 External Channel Selection
          1. 22.3.6.1.1 External Channel Selection Timing
    4. 22.4  SOC Configuration Examples
      1. 22.4.1 Single Conversion from ePWM Trigger
      2. 22.4.2 Oversampled Conversion from ePWM Trigger
      3. 22.4.3 Multiple Conversions from CPU Timer Trigger
      4. 22.4.4 Software Triggering of SOCs
    5. 22.5  ADC Conversion Priority
    6. 22.6  Burst Mode
      1. 22.6.1 Burst Mode Example
      2. 22.6.2 Burst Mode Priority Example
    7. 22.7  EOC and Interrupt Operation
      1. 22.7.1 Interrupt Overflow
      2. 22.7.2 Continue to Interrupt Mode
      3. 22.7.3 Early Interrupt Configuration Mode
    8. 22.8  Post-Processing Blocks
      1. 22.8.1 PPB Offset Correction
      2. 22.8.2 PPB Error Calculation
      3. 22.8.3 PPB Result Delta Calculation
      4. 22.8.4 PPB Limit Detection and Zero-Crossing Detection
        1. 22.8.4.1 PPB Digital Trip Filter
      5. 22.8.5 PPB Oversampling
        1. 22.8.5.1 Accumulation, Minimum, Maximum, and Average Functions
        2. 22.8.5.2 Outlier Rejection
    9. 22.9  Result Safety Checker
      1. 22.9.1 Result Safety Checker Operation
      2. 22.9.2 Result Safety Checker Interrupts and Events
    10. 22.10 Opens/Shorts Detection Circuit (OSDETECT)
      1. 22.10.1 Open Short Detection Implementation
      2. 22.10.2 Detecting an Open Input Pin
      3. 22.10.3 Detecting a Shorted Input Pin
    11. 22.11 Power-Up Sequence
    12. 22.12 ADC Calibration
      1. 22.12.1 ADC Zero Offset Calibration
    13. 22.13 ADC Timings
      1. 22.13.1 ADC Timing Diagrams
      2. 22.13.2 Post-Processing Block Timings
    14. 22.14 Additional Information
      1. 22.14.1 Ensuring Synchronous Operation
        1. 22.14.1.1 Basic Synchronous Operation
        2. 22.14.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 22.14.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 22.14.1.4 Synchronous Operation with Different Resolutions
        5. 22.14.1.5 Non-overlapping Conversions
      2. 22.14.2 Choosing an Acquisition Window Duration
      3. 22.14.3 Achieving Simultaneous Sampling
      4. 22.14.4 Result Register Mapping
      5. 22.14.5 Internal Temperature Sensor
      6. 22.14.6 Designing an External Reference Circuit
      7. 22.14.7 Internal Test Mode
      8. 22.14.8 ADC Gain and Offset Calibration
    15. 22.15 Software
      1. 22.15.1 ADC Registers to Driverlib Functions
      2. 22.15.2 ADC Examples
        1. 22.15.2.1  Using Analog Subsystems Lab - Sysconfig - SINGLE_CORE
        2. 22.15.2.2  ADC Software Triggering - SINGLE_CORE
        3. 22.15.2.3  ADC ePWM Triggering - SINGLE_CORE
        4. 22.15.2.4  ADC Temperature Sensor Conversion - SINGLE_CORE
        5. 22.15.2.5  ADC Synchronous SOC Software Force (adc_soc_software_sync) - SINGLE_CORE
        6. 22.15.2.6  ADC Continuous Triggering (adc_soc_continuous) - SINGLE_CORE
        7. 22.15.2.7  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma) - SINGLE_CORE
        8. 22.15.2.8  ADC PPB Offset (adc_ppb_offset) - SINGLE_CORE
        9. 22.15.2.9  ADC PPB Limits (adc_ppb_limits) - SINGLE_CORE
        10. 22.15.2.10 ADC PPB Delay Capture (adc_ppb_delay) - SINGLE_CORE
        11. 22.15.2.11 ADC ePWM Triggering Multiple SOC - SINGLE_CORE
        12. 22.15.2.12 ADC Burst Mode - SINGLE_CORE
        13. 22.15.2.13 ADC Burst Mode Oversampling - SINGLE_CORE
        14. 22.15.2.14 ADC SOC Oversampling - SINGLE_CORE
        15. 22.15.2.15 ADC PPB PWM trip (adc_ppb_pwm_trip) - SINGLE_CORE
        16. 22.15.2.16 ADC Trigger Repeater Oversampling - SINGLE_CORE
        17. 22.15.2.17 ADC Trigger Repeater Undersampling - SINGLE_CORE
        18. 22.15.2.18 ADC Safety Checker - SINGLE_CORE
        19. 22.15.2.19 ADC Fast Oversampling (with Trigger Repeater) - SINGLE_CORE
    16. 22.16 ADC Registers
      1. 22.16.1 ADC Base Address Table
      2. 22.16.2 ADC_RESULT_REGS Registers
      3. 22.16.3 ADC_REGS Registers
      4. 22.16.4 ADC_SAFECHECK_REGS Registers
      5. 22.16.5 ADC_SAFECHECK_INTEVT_REGS Registers
      6. 22.16.6 ADC_GLOBAL_REGS Registers
  27. 23Buffered Digital-to-Analog Converter (DAC)
    1. 23.1 Introduction
      1. 23.1.1 DAC Related Collateral
      2. 23.1.2 DAC Features
      3. 23.1.3 Block Diagram
    2. 23.2 Using the DAC
      1. 23.2.1 Initialization Sequence
      2. 23.2.2 DAC Offset Adjustment
      3. 23.2.3 EPWMSYNCPER Signal
    3. 23.3 Lock Registers
    4. 23.4 Software
      1. 23.4.1 DAC Registers to Driverlib Functions
      2. 23.4.2 DAC Examples
        1. 23.4.2.1 Buffered DAC Enable - SINGLE_CORE
        2. 23.4.2.2 Buffered DAC Random - SINGLE_CORE
    5. 23.5 DAC Registers
      1. 23.5.1 DAC Base Address Table
      2. 23.5.2 DAC_REGS Registers
  28. 24Comparator Subsystem (CMPSS)
    1. 24.1 Introduction
      1. 24.1.1 Features
      2. 24.1.2 CMPSS Related Collateral
      3. 24.1.3 Block Diagram
    2. 24.2 Comparator
    3. 24.3 Reference DAC
    4. 24.4 Ramp Generator
      1. 24.4.1 Ramp Generator Overview
      2. 24.4.2 Ramp Generator Behavior
      3. 24.4.3 Ramp Generator Behavior at Corner Cases
    5. 24.5 Digital Filter
      1. 24.5.1 Filter Initialization Sequence
    6. 24.6 Using the CMPSS
      1. 24.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 24.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 24.6.3 Calibrating the CMPSS
      4. 24.6.4 Enabling and Disabling the CMPSS Clock
    7. 24.7 Software
      1. 24.7.1 CMPSS Registers to Driverlib Functions
      2. 24.7.2 CMPSS Examples
        1. 24.7.2.1 CMPSS Asynchronous Trip - SINGLE_CORE
        2. 24.7.2.2 CMPSS Digital Filter Configuration - SINGLE_CORE
    8. 24.8 CMPSS Registers
      1. 24.8.1 CMPSS Base Address Table
      2. 24.8.2 CMPSS_REGS Registers
      3. 24.8.3 CMPSS_LITE_REGS Registers
    9. 24.9 CMPSS Registers
      1. 24.9.1 CMPSS Base Address Table
      2. 24.9.2 CMPSS_REGS Registers
  29.   ► CONTROL PERIPHERALS
    1.     Technical Reference Manual Overview
  30. 25Enhanced Capture (eCAP)
    1. 25.1 Introduction
      1. 25.1.1 Features
      2. 25.1.2 ECAP Related Collateral
    2. 25.2 Description
    3. 25.3 Configuring Device Pins for the eCAP
    4. 25.4 Capture and APWM Operating Mode
    5. 25.5 Capture Mode Description
      1. 25.5.1  Event Prescaler
      2. 25.5.2  Glitch Filter
      3. 25.5.3  Edge Polarity Select and Qualifier
      4. 25.5.4  Continuous/One-Shot Control
      5. 25.5.5  32-Bit Counter and Phase Control
      6. 25.5.6  CAP1-CAP4 Registers
      7. 25.5.7  eCAP Synchronization
        1. 25.5.7.1 Example 1 - Using SWSYNC with ECAP Module
      8. 25.5.8  Interrupt Control
      9. 25.5.9  RTDMA Interrupt
      10. 25.5.10 ADC SOC Event
      11. 25.5.11 Shadow Load and Lockout Control
      12. 25.5.12 APWM Mode Operation
      13. 25.5.13 Signal Monitoring Unit
        1. 25.5.13.1 Pulse Width and Period Monitoring
          1. 25.5.13.1.1 eCAP - eCAP Global Strobe Selection
        2. 25.5.13.2 Edge Monitoring
    6. 25.6 Application of the eCAP Module
      1. 25.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 25.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 25.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 25.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 25.7 Application of the APWM Mode
      1. 25.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 25.8 Software
      1. 25.8.1 ECAP Registers to Driverlib Functions
      2. 25.8.2 ECAP Examples
        1. 25.8.2.1 eCAP APWM Phase-shift Example - SINGLE_CORE
        2. 25.8.2.2 eCAP APWM Example - SINGLE_CORE
        3. 25.8.2.3 eCAP Capture PWM Example - SINGLE_CORE
        4. 25.8.2.4 eCAP APWM Phase-shift Example - SINGLE_CORE
        5. 25.8.2.5 ecap_ex4_dma_transfer - SINGLE_CORE
    9. 25.9 ECAP Registers
      1. 25.9.1 ECAP Base Address Table
      2. 25.9.2 ECAP_REGS Registers
      3. 25.9.3 ECAP_SIGNAL_MONITORING Registers
      4. 25.9.4 HRCAP_REGS Registers
  31. 26High Resolution Capture (HRCAP)
    1. 26.1 Introduction
      1. 26.1.1 HRCAP Related Collateral
      2. 26.1.2 Features
      3. 26.1.3 Description
    2. 26.2 Operational Details
      1. 26.2.1 HRCAP Clocking
      2. 26.2.2 HRCAP Initialization Sequence
      3. 26.2.3 HRCAP Interrupts
      4. 26.2.4 HRCAP Calibration
        1. 26.2.4.1 Applying the Scale Factor
    3. 26.3 Known Exceptions
    4. 26.4 Software
      1. 26.4.1 HRCAP Examples
        1. 26.4.1.1 HRCAP Capture and Calibration Example - SINGLE_CORE
    5. 26.5 HRCAP Registers
      1. 26.5.1 HRCAP Base Address Table
      2. 26.5.2 HRCAP_REGS Registers
  32. 27Enhanced Pulse Width Modulator (ePWM)
    1. 27.1  Introduction
      1. 27.1.1 EPWM Related Collateral
      2. 27.1.2 Submodule Overview
    2. 27.2  Configuring Device Pins
    3. 27.3  ePWM Modules Overview
    4. 27.4  Time-Base (TB) Submodule
      1. 27.4.1 Purpose of the Time-Base Submodule
      2. 27.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 27.4.3 Calculating PWM Period and Frequency
        1. 27.4.3.1 Time-Base Period Shadow Register
        2. 27.4.3.2 Time-Base Clock Synchronization
        3. 27.4.3.3 Time-Base Counter Synchronization
        4. 27.4.3.4 ePWM SYNC Selection
      4. 27.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 27.4.5 Simultaneous Writes Between ePWM Register Instances
      6. 27.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 27.4.7 Global Load
        1. 27.4.7.1 Global Load Pulse Pre-Scalar
        2. 27.4.7.2 One-Shot Load Mode
        3. 27.4.7.3 One-Shot Sync Mode
    5. 27.5  Counter-Compare (CC) Submodule
      1. 27.5.1 Purpose of the Counter-Compare Submodule
      2. 27.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 27.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 27.5.4 Count Mode Timing Waveforms
    6. 27.6  Action-Qualifier (AQ) Submodule
      1. 27.6.1 Purpose of the Action-Qualifier Submodule
      2. 27.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 27.6.3 Action-Qualifier Event Priority
      4. 27.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 27.6.5 Configuration Requirements for Common Waveforms
    7. 27.7  XCMP Complex Waveform Generator Mode
      1. 27.7.1 XCMP Allocation to CMPA and CMPB
      2. 27.7.2 XCMP Shadow Buffers
      3. 27.7.3 XCMP Operation
    8. 27.8  Dead-Band Generator (DB) Submodule
      1. 27.8.1 Purpose of the Dead-Band Submodule
      2. 27.8.2 Dead-band Submodule Additional Operating Modes
      3. 27.8.3 Operational Highlights for the Dead-Band Submodule
    9. 27.9  PWM Chopper (PC) Submodule
      1. 27.9.1 Purpose of the PWM Chopper Submodule
      2. 27.9.2 Operational Highlights for the PWM Chopper Submodule
      3. 27.9.3 Waveforms
        1. 27.9.3.1 One-Shot Pulse
        2. 27.9.3.2 Duty Cycle Control
    10. 27.10 Trip-Zone (TZ) Submodule
      1. 27.10.1 Purpose of the Trip-Zone Submodule
      2. 27.10.2 Operational Highlights for the Trip-Zone Submodule
        1. 27.10.2.1 Trip-Zone Configurations
      3. 27.10.3 Generating Trip Event Interrupts
    11. 27.11 Diode Emulation (DE) Submodule
      1. 27.11.1 DEACTIVE Mode
      2. 27.11.2 Exiting DE Mode
      3. 27.11.3 Re-Entering DE Mode
      4. 27.11.4 DE Monitor
    12. 27.12 Minimum Dead-Band (MINDB) + Illegal Combination Logic (ICL) Submodules
      1. 27.12.1 Minimum Dead-Band (MINDB)
      2. 27.12.2 Illegal Combo Logic (ICL)
    13. 27.13 Event-Trigger (ET) Submodule
      1. 27.13.1 Operational Overview of the ePWM Event-Trigger Submodule
    14. 27.14 Digital Compare (DC) Submodule
      1. 27.14.1 Purpose of the Digital Compare Submodule
      2. 27.14.2 Enhanced Trip Action Using CMPSS
      3. 27.14.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 27.14.4 Operation Highlights of the Digital Compare Submodule
        1. 27.14.4.1 Digital Compare Events
        2. 27.14.4.2 Event Filtering
        3. 27.14.4.3 Valley Switching
        4. 27.14.4.4 Event Detection
          1. 27.14.4.4.1 Input Signal Detection
          2. 27.14.4.4.2 MIN and MAX Detection Circuit
    15. 27.15 ePWM Crossbar (X-BAR)
    16. 27.16 Applications to Power Topologies
      1. 27.16.1  Overview of Multiple Modules
      2. 27.16.2  Key Configuration Capabilities
      3. 27.16.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 27.16.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 27.16.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 27.16.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 27.16.7  Practical Applications Using Phase Control Between PWM Modules
      8. 27.16.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 27.16.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 27.16.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 27.16.11 Controlling H-Bridge LLC Resonant Converter
    17. 27.17 Register Lock Protection
    18. 27.18 High-Resolution Pulse Width Modulator (HRPWM)
      1. 27.18.1 Operational Description of HRPWM
        1. 27.18.1.1 Controlling the HRPWM Capabilities
        2. 27.18.1.2 HRPWM Source Clock
        3. 27.18.1.3 Configuring the HRPWM
        4. 27.18.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 27.18.1.5 Principle of Operation
          1. 27.18.1.5.1 Edge Positioning
          2. 27.18.1.5.2 Scaling Considerations
          3. 27.18.1.5.3 Duty Cycle Range Limitation
          4. 27.18.1.5.4 High-Resolution Period
            1. 27.18.1.5.4.1 High-Resolution Period Configuration
        6. 27.18.1.6 Deadband High-Resolution Operation
        7. 27.18.1.7 Scale Factor Optimizing Software (SFO)
        8. 27.18.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 27.18.1.8.1 #Defines for HRPWM Header Files
          2. 27.18.1.8.2 Implementing a Simple Buck Converter
            1. 27.18.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 27.18.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 27.18.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 27.18.1.8.3.1 PWM DAC Function Initialization Code
            2. 27.18.1.8.3.2 PWM DAC Function Run-Time Code
      2. 27.18.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 27.18.2.1 Scale Factor Optimizer Function - int SFO()
        2. 27.18.2.2 Software Usage
          1. 27.18.2.2.1 A Sample of How to Add "Include" Files
          2.        1169
          3. 27.18.2.2.2 Declaring an Element
          4.        1171
          5. 27.18.2.2.3 Initializing With a Scale Factor Value
          6.        1173
          7. 27.18.2.2.4 SFO Function Calls
    19. 27.19 Software
      1. 27.19.1 EPWM Registers to Driverlib Functions
      2. 27.19.2 HRPWMCAL Registers to Driverlib Functions
      3. 27.19.3 EPWM Examples
        1. 27.19.3.1  ePWM Trip Zone - SINGLE_CORE
        2. 27.19.3.2  ePWM Up Down Count Action Qualifier with FRAMESEL and IPC - MULTI_CORE
        3. 27.19.3.3  ePWM Up Down Count Action Qualifier with FRAMESEL and IPC - MULTI_CORE
        4. 27.19.3.4  ePWM Up Down Count Action Qualifier - SINGLE_CORE
        5. 27.19.3.5  ePWM Synchronization - SINGLE_CORE
        6. 27.19.3.6  ePWM Digital Compare - SINGLE_CORE
        7. 27.19.3.7  ePWM Digital Compare Event Filter Blanking Window - SINGLE_CORE
        8. 27.19.3.8  ePWM Valley Switching - SINGLE_CORE
        9. 27.19.3.9  ePWM Digital Compare Edge Filter - SINGLE_CORE
        10. 27.19.3.10 ePWM Deadband - SINGLE_CORE
        11. 27.19.3.11 ePWM DMA - SINGLE_CORE
        12. 27.19.3.12 ePWM Chopper - SINGLE_CORE
        13. 27.19.3.13 EPWM Configure Signal - SINGLE_CORE
        14. 27.19.3.14 Realization of Monoshot mode - SINGLE_CORE
        15. 27.19.3.15 EPWM Action Qualifier (epwm_up_aq) - SINGLE_CORE
        16. 27.19.3.16 ePWM XCMP Mode - SINGLE_CORE
        17. 27.19.3.17 ePWM Event Detection - SINGLE_CORE
      4. 27.19.4 HRPWM Examples
        1. 27.19.4.1 HRPWM Duty Control with SFO - SINGLE_CORE
        2. 27.19.4.2 HRPWM Period Control - SINGLE_CORE
        3. 27.19.4.3 HRPWM XCMP Mode - SINGLE_CORE
    20. 27.20 EPWM Registers
      1. 27.20.1 EPWM Base Address Table
      2. 27.20.2 EPWM_REGS Registers
      3. 27.20.3 EPWM_XCMP_REGS Registers
      4. 27.20.4 DE_REGS Registers
      5. 27.20.5 MINDB_LUT_REGS Registers
      6. 27.20.6 HRPWMCAL_REGS Registers
  33. 28Enhanced Quadrature Encoder Pulse (eQEP)
    1. 28.1  Introduction
      1. 28.1.1 EQEP Related Collateral
    2. 28.2  Configuring Device Pins
    3. 28.3  Description
      1. 28.3.1 EQEP Inputs
      2. 28.3.2 Functional Description
      3. 28.3.3 eQEP Memory Map
    4. 28.4  Quadrature Decoder Unit (QDU)
      1. 28.4.1 Position Counter Input Modes
        1. 28.4.1.1 Quadrature Count Mode
        2. 28.4.1.2 Direction-Count Mode
        3. 28.4.1.3 Up-Count Mode
        4. 28.4.1.4 Down-Count Mode
      2. 28.4.2 eQEP Input Polarity Selection
      3. 28.4.3 Position-Compare Sync Output
    5. 28.5  Position Counter and Control Unit (PCCU)
      1. 28.5.1 Position Counter Operating Modes
        1. 28.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 28.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 28.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 28.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 28.5.2 Position Counter Latch
        1. 28.5.2.1 Index Event Latch
        2. 28.5.2.2 Strobe Event Latch
      3. 28.5.3 Position Counter Initialization
      4. 28.5.4 eQEP Position-compare Unit
    6. 28.6  eQEP Edge Capture Unit
    7. 28.7  eQEP Watchdog
    8. 28.8  eQEP Unit Timer Base
    9. 28.9  QMA Module
      1. 28.9.1 Modes of Operation
        1. 28.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 28.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 28.9.2 Interrupt and Error Generation
    10. 28.10 eQEP Interrupt Structure
    11. 28.11 Software
      1. 28.11.1 EQEP Registers to Driverlib Functions
      2. 28.11.2 EQEP Examples
        1. 28.11.2.1 Frequency Measurement Using eQEP via unit timeout interrupt - SINGLE_CORE
        2. 28.11.2.2 Frequency Measurement Using eQEP via unit timeout interrupt - SINGLE_CORE
        3. 28.11.2.3 Motor speed and direction measurement using eQEP via unit timeout interrupt - SINGLE_CORE
    12. 28.12 EQEP Registers
      1. 28.12.1 EQEP Base Address Table
      2. 28.12.2 EQEP_REGS Registers
  34. 29Sigma Delta Filter Module (SDFM)
    1. 29.1  Introduction
      1. 29.1.1 SDFM Related Collateral
      2. 29.1.2 Features
      3. 29.1.3 Block Diagram
    2. 29.2  Configuring Device Pins
    3. 29.3  Input Qualification
    4. 29.4  Input Control Unit
    5. 29.5  SDFM Clock Control
    6. 29.6  Sinc Filter
      1. 29.6.1 Data Rate and Latency of the Sinc Filter
    7. 29.7  Data (Primary) Filter Unit
      1. 29.7.1 32-bit or 16-bit Data Filter Output Representation
      2. 29.7.2 Data FIFO
      3. 29.7.3 SDSYNC Event
    8. 29.8  Comparator (Secondary) Filter Unit
      1. 29.8.1 Higher Threshold (HLT) Comparators
      2. 29.8.2 Lower Threshold (LLT) Comparators
      3. 29.8.3 Digital Filter
    9. 29.9  Theoretical SDFM Filter Output
    10. 29.10 Interrupt Unit
      1. 29.10.1 SDFM (SDyERR) Interrupt Sources
      2. 29.10.2 Data Ready (DRINT) Interrupt Sources
    11. 29.11 SDFM Registers
      1. 29.11.1 SDFM Base Address Table
      2. 29.11.2 SDFM_REGS Registers
  35.   ► COMMUNICATION PERIPHERALS
    1.     Technical Reference Manual Overview
  36. 30Modular Controller Area Network (MCAN)
    1. 30.1 MCAN Introduction
      1. 30.1.1 MCAN Related Collateral
      2. 30.1.2 MCAN Features
    2. 30.2 MCAN Environment
    3. 30.3 CAN Network Basics
    4. 30.4 MCAN Integration
    5. 30.5 MCAN Functional Description
      1. 30.5.1  Module Clocking Requirements
      2. 30.5.2  Interrupt Requests
      3. 30.5.3  Operating Modes
        1. 30.5.3.1 Software Initialization
        2. 30.5.3.2 Normal Operation
        3. 30.5.3.3 CAN FD Operation
      4. 30.5.4  Transmitter Delay Compensation
        1. 30.5.4.1 Description
        2. 30.5.4.2 Transmitter Delay Compensation Measurement
      5. 30.5.5  Restricted Operation Mode
      6. 30.5.6  Bus Monitoring Mode
      7. 30.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 30.5.7.1 Frame Transmission in DAR Mode
      8. 30.5.8  Clock Stop Mode
        1. 30.5.8.1 Suspend Mode
        2. 30.5.8.2 Wakeup Request
      9. 30.5.9  Test Modes
        1. 30.5.9.1 External Loop Back Mode
        2. 30.5.9.2 Internal Loop Back Mode
      10. 30.5.10 Timestamp Generation
        1. 30.5.10.1 External Timestamp Counter
      11. 30.5.11 Timeout Counter
      12. 30.5.12 Safety
        1. 30.5.12.1 ECC Wrapper
        2. 30.5.12.2 ECC Aggregator
          1. 30.5.12.2.1 ECC Aggregator Overview
          2. 30.5.12.2.2 ECC Aggregator Registers
        3. 30.5.12.3 Reads to ECC Control and Status Registers
        4. 30.5.12.4 ECC Interrupts
      13. 30.5.13 Rx Handling
        1. 30.5.13.1 Acceptance Filtering
          1. 30.5.13.1.1 Range Filter
          2. 30.5.13.1.2 Filter for Specific IDs
          3. 30.5.13.1.3 Classic Bit Mask Filter
          4. 30.5.13.1.4 Standard Message ID Filtering
          5. 30.5.13.1.5 Extended Message ID Filtering
        2. 30.5.13.2 Rx FIFOs
          1. 30.5.13.2.1 Rx FIFO Blocking Mode
          2. 30.5.13.2.2 Rx FIFO Overwrite Mode
        3. 30.5.13.3 Dedicated Rx Buffers
          1. 30.5.13.3.1 Rx Buffer Handling
      14. 30.5.14 Tx Handling
        1. 30.5.14.1 Transmit Pause
        2. 30.5.14.2 Dedicated Tx Buffers
        3. 30.5.14.3 Tx FIFO
        4. 30.5.14.4 Tx Queue
        5. 30.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 30.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 30.5.14.7 Transmit Cancellation
        8. 30.5.14.8 Tx Event Handling
      15. 30.5.15 FIFO Acknowledge Handling
      16. 30.5.16 Message RAM
        1. 30.5.16.1 Message RAM Configuration
        2. 30.5.16.2 Rx Buffer and FIFO Element
        3. 30.5.16.3 Tx Buffer Element
        4. 30.5.16.4 Tx Event FIFO Element
        5. 30.5.16.5 Standard Message ID Filter Element
        6. 30.5.16.6 Extended Message ID Filter Element
    6. 30.6 Software
      1. 30.6.1 MCAN Examples
        1. 30.6.1.1 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
        2. 30.6.1.2 MCAN Loopback with Polling Example Using SYSCONFIG Tool - SINGLE_CORE
        3. 30.6.1.3 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
        4. 30.6.1.4 MCAN External Transmit using Tx Buffer - SINGLE_CORE
        5. 30.6.1.5 MCAN receive using Rx Buffer - SINGLE_CORE
        6. 30.6.1.6 MCAN External Transmit using Tx Buffer - SINGLE_CORE
    7. 30.7 MCAN Registers
      1. 30.7.1 MCAN Base Address Table
      2. 30.7.2 MCANSS_REGS Registers
      3. 30.7.3 MCAN_REGS Registers
      4. 30.7.4 MCAN_ERROR_REGS Registers
  37. 31EtherCAT® SubordinateDevice Controller (ESC)
    1. 31.1 Introduction
      1. 31.1.1  EtherCAT Related Collateral
      2. 31.1.2  ESC Features
      3. 31.1.3  ESC Subsystem Integrated Features
      4. 31.1.4  ESC versus Beckhoff ET1100
      5. 31.1.5  EtherCAT IP Block Diagram
      6. 31.1.6  ESC Functional Blocks
        1. 31.1.6.1  Interface to EtherCAT MainDevice
        2. 31.1.6.2  Process Data Interface
        3. 31.1.6.3  General-Purpose Inputs and Outputs
        4. 31.1.6.4  EtherCAT Processing Unit (EPU)
        5. 31.1.6.5  Fieldbus Memory Management Unit (FMMU)
        6. 31.1.6.6  Sync Manager
        7. 31.1.6.7  Monitoring
        8. 31.1.6.8  Reset Controller
        9. 31.1.6.9  PHY Management
        10. 31.1.6.10 Distributed Clock (DC)
        11. 31.1.6.11 EEPROM
        12. 31.1.6.12 Status / LEDs
      7. 31.1.7  EtherCAT Physical Layer
        1. 31.1.7.1 MII Interface
        2. 31.1.7.2 PHY Management Interface
          1. 31.1.7.2.1 PHY Address Configuration
          2. 31.1.7.2.2 PHY Reset Signal
          3. 31.1.7.2.3 PHY Clock
      8. 31.1.8  EtherCAT Protocol
      9. 31.1.9  EtherCAT State Machine (ESM)
      10. 31.1.10 More Information on EtherCAT
      11. 31.1.11 Beckhoff® Automation EtherCAT IP Errata
    2. 31.2 ESC and ESCSS Description
      1. 31.2.1  ESC RAM Parity and Memory Address Maps
        1. 31.2.1.1 ESC RAM Parity Logic
        2. 31.2.1.2 CPU1 ESC Memory Address Map
        3. 31.2.1.3 CPU2 ESC Memory Address Map
      2. 31.2.2  Local Host Communication
        1. 31.2.2.1 Byte Accessibility Through PDI
        2. 31.2.2.2 Software Details for Operation Across Clock Domains
      3. 31.2.3  Debug Emulation Mode Operation
      4. 31.2.4  ESC SubSystem
        1. 31.2.4.1 CPU1 Bus Interface
        2. 31.2.4.2 CPU2/CPU3 Bus Interface
      5. 31.2.5  Interrupts and Interrupt Mapping
      6. 31.2.6  Power, Clocks, and Resets
        1. 31.2.6.1 Power
        2. 31.2.6.2 Clocking
        3. 31.2.6.3 Resets
          1. 31.2.6.3.1 Chip-Level Reset
          2. 31.2.6.3.2 EtherCAT Soft Resets
          3. 31.2.6.3.3 Reset Out (RESET_OUT)
      7. 31.2.7  LED Controls
      8. 31.2.8  SubordinateDevice Node Configuration and EEPROM
      9. 31.2.9  General-Purpose Inputs and Outputs
        1. 31.2.9.1 General-Purpose Inputs
        2. 31.2.9.2 General-Purpose Output
      10. 31.2.10 Distributed Clocks – Sync and Latch
        1. 31.2.10.1 Clock Synchronization
        2. 31.2.10.2 SYNC Signals
          1. 31.2.10.2.1 Seeking Host Intervention
        3. 31.2.10.3 LATCH Signals
          1. 31.2.10.3.1 Timestamping
        4. 31.2.10.4 Device Control and Synchronization
          1. 31.2.10.4.1 Synchronization of PWM
          2. 31.2.10.4.2 ECAP SYNC Inputs
          3. 31.2.10.4.3 SYNC Signal Conditioning and Rerouting
    3. 31.3 Software Initialization Sequence and Allocating Ownership
    4. 31.4 ESC Configuration Constants
    5. 31.5 Software
      1. 31.5.1 ECAT_SS Registers to Driverlib Functions
      2. 31.5.2 ETHERNET Examples
    6. 31.6 ETHERCAT Registers
      1. 31.6.1 ETHERCAT Base Address Table
      2. 31.6.2 ESCSS_REGS Registers
      3. 31.6.3 ESCSS_CONFIG_REGS Registers
  38. 32Fast Serial Interface (FSI)
    1. 32.1 Introduction
      1. 32.1.1 FSI Related Collateral
      2. 32.1.2 FSI Features
    2. 32.2 System-level Integration
      1. 32.2.1 CPU Interface
      2. 32.2.2 Signal Description
        1. 32.2.2.1 Configuring Device Pins
      3. 32.2.3 FSI Interrupts
        1. 32.2.3.1 Transmitter Interrupts
        2. 32.2.3.2 Receiver Interrupts
        3. 32.2.3.3 Configuring Interrupts
        4. 32.2.3.4 Handling Interrupts
      4. 32.2.4 RTDMA Interface
      5. 32.2.5 External Frame Trigger Mux
    3. 32.3 FSI Functional Description
      1. 32.3.1 Introduction to Operation
      2. 32.3.2 FSI Transmitter Module
        1. 32.3.2.1 Initialization
        2. 32.3.2.2 FSI_TX Clocking
        3. 32.3.2.3 Transmitting Frames
          1. 32.3.2.3.1 Software Triggered Frames
          2. 32.3.2.3.2 Externally Triggered Frames
          3. 32.3.2.3.3 Ping Frame Generation
            1. 32.3.2.3.3.1 Automatic Ping Frames
            2. 32.3.2.3.3.2 Software Triggered Ping Frame
            3. 32.3.2.3.3.3 Externally Triggered Ping Frame
          4. 32.3.2.3.4 Transmitting Frames with RTDMA
        4. 32.3.2.4 Transmit Buffer Management
        5. 32.3.2.5 CRC Submodule
        6. 32.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 32.3.2.7 Reset
      3. 32.3.3 FSI Receiver Module
        1. 32.3.3.1  Initialization
        2. 32.3.3.2  FSI_RX Clocking
        3. 32.3.3.3  Receiving Frames
          1. 32.3.3.3.1 Receiving Frames with RTDMA
        4. 32.3.3.4  Ping Frame Watchdog
        5. 32.3.3.5  Frame Watchdog
        6. 32.3.3.6  Delay Line Control
        7. 32.3.3.7  Buffer Management
        8. 32.3.3.8  CRC Submodule
        9. 32.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 32.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 32.3.3.11 FSI_RX Reset
      4. 32.3.4 Frame Format
        1. 32.3.4.1 FSI Frame Phases
        2. 32.3.4.2 Frame Types
          1. 32.3.4.2.1 Ping Frames
          2. 32.3.4.2.2 Error Frames
          3. 32.3.4.2.3 Data Frames
        3. 32.3.4.3 Multi-Lane Transmission
      5. 32.3.5 Flush Sequence
      6. 32.3.6 Internal Loopback
      7. 32.3.7 CRC Generation
      8. 32.3.8 ECC Module
      9. 32.3.9 FSI-SPI Compatibility Mode
        1. 32.3.9.1 Available SPI Modes
          1. 32.3.9.1.1 FSITX as SPI Controller, Transmit Only
            1. 32.3.9.1.1.1 Initialization
            2. 32.3.9.1.1.2 Operation
          2. 32.3.9.1.2 FSIRX as SPI Peripheral, Receive Only
            1. 32.3.9.1.2.1 Initialization
            2. 32.3.9.1.2.2 Operation
          3. 32.3.9.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
            1. 32.3.9.1.3.1 Initialization
            2. 32.3.9.1.3.2 Operation
    4. 32.4 FSI Programing Guide
      1. 32.4.1 Establishing the Communication Link
        1. 32.4.1.1 Establishing the Communication Link from the Main Device
        2. 32.4.1.2 Establishing the Communication Link from the Remote Device
      2. 32.4.2 Register Protection
      3. 32.4.3 Emulation Mode
    5. 32.5 Software
      1. 32.5.1 FSI Registers to Driverlib Functions
      2. 32.5.2 FSI Examples
        1. 32.5.2.1 Lab solution on Using Communication Peripherals - SINGLE_CORE
        2. 32.5.2.2 FSI Loopback:CPU Control - SINGLE_CORE
        3. 32.5.2.3 FSI data transfers upon CPU Timer event - SINGLE_CORE
    6. 32.6 FSI Registers
      1. 32.6.1 FSI Base Address Table
      2. 32.6.2 FSI_TX_REGS Registers
      3. 32.6.3 FSI_RX_REGS Registers
  39. 33Inter-Integrated Circuit Module (I2C)
    1. 33.1 Introduction
      1. 33.1.1 I2C Related Collateral
      2. 33.1.2 Features
      3. 33.1.3 Features Not Supported
      4. 33.1.4 Functional Overview
      5. 33.1.5 Clock Generation
      6. 33.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 33.1.6.1 Formula for the Controller Clock Period
    2. 33.2 Configuring Device Pins
    3. 33.3 I2C Module Operational Details
      1. 33.3.1  Input and Output Voltage Levels
      2. 33.3.2  Selecting Pullup Resistors
      3. 33.3.3  Data Validity
      4. 33.3.4  Operating Modes
      5. 33.3.5  I2C Module START and STOP Conditions
      6. 33.3.6  Non-repeat Mode versus Repeat Mode
      7. 33.3.7  Serial Data Formats
        1. 33.3.7.1 7-Bit Addressing Format
        2. 33.3.7.2 10-Bit Addressing Format
        3. 33.3.7.3 Free Data Format
        4. 33.3.7.4 Using a Repeated START Condition
      8. 33.3.8  Clock Synchronization
      9. 33.3.9  Clock Stretching
      10. 33.3.10 Arbitration
      11. 33.3.11 Digital Loopback Mode
      12. 33.3.12 NACK Bit Generation
    4. 33.4 Interrupt Requests Generated by the I2C Module
      1. 33.4.1 Basic I2C Interrupt Requests
      2. 33.4.2 I2C FIFO Interrupts
    5. 33.5 Resetting or Disabling the I2C Module
    6. 33.6 Software
      1. 33.6.1 I2C Registers to Driverlib Functions
      2. 33.6.2 I2C Examples
        1. 33.6.2.1 I2C Digital Loopback with FIFO Interrupts - SINGLE_CORE
        2. 33.6.2.2 I2C EEPROM - SINGLE_CORE
        3. 33.6.2.3 I2C Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        4. 33.6.2.4 I2C Extended Clock Stretching Controller TX - SINGLE_CORE
        5. 33.6.2.5 I2C Extended Clock Stretching Target RX - SINGLE_CORE
    7. 33.7 I2C Registers
      1. 33.7.1 I2C Base Address Table
      2. 33.7.2 I2C_REGS Registers
  40. 34Power Management Bus Module (PMBus)
    1. 34.1 Introduction
      1. 34.1.1 PMBUS Related Collateral
      2. 34.1.2 Features
      3. 34.1.3 Block Diagram
    2. 34.2 Configuring Device Pins
    3. 34.3 Target Mode Operation
      1. 34.3.1 Configuration
      2. 34.3.2 Message Handling
        1. 34.3.2.1  Quick Command
        2. 34.3.2.2  Send Byte
        3. 34.3.2.3  Receive Byte
        4. 34.3.2.4  Write Byte and Write Word
        5. 34.3.2.5  Read Byte and Read Word
        6. 34.3.2.6  Process Call
        7. 34.3.2.7  Block Write
        8. 34.3.2.8  Block Read
        9. 34.3.2.9  Block Write-Block Read Process Call
        10. 34.3.2.10 Alert Response
        11. 34.3.2.11 Extended Command
        12. 34.3.2.12 Group Command
    4. 34.4 Controller Mode Operation
      1. 34.4.1 Configuration
      2. 34.4.2 Message Handling
        1. 34.4.2.1  Quick Command
        2. 34.4.2.2  Send Byte
        3. 34.4.2.3  Receive Byte
        4. 34.4.2.4  Write Byte and Write Word
        5. 34.4.2.5  Read Byte and Read Word
        6. 34.4.2.6  Process Call
        7. 34.4.2.7  Block Write
        8. 34.4.2.8  Block Read
        9. 34.4.2.9  Block Write-Block Read Process Call
        10. 34.4.2.10 Alert Response
        11. 34.4.2.11 Extended Command
        12. 34.4.2.12 Group Command
    5. 34.5 Software
      1. 34.5.1 PMBUS Registers to Driverlib Functions
      2. 34.5.2 PMBUS Examples
        1. 34.5.2.1 PMBus in I2C Mode Controller - SINGLE_CORE
        2. 34.5.2.2 PMBus in I2C Mode Target - SINGLE_CORE
    6. 34.6 PMBUS Registers
      1. 34.6.1 PMBUS Base Address Table
      2. 34.6.2 PMBUS_REGS Registers
  41. 35Universal Asynchronous Receiver/Transmitter (UART)
    1. 35.1 Introduction
      1. 35.1.1 Features
      2. 35.1.2 UART Related Collateral
      3. 35.1.3 Block Diagram
    2. 35.2 Functional Description
      1. 35.2.1 Transmit and Receive Logic
      2. 35.2.2 Baud-Rate Generation
      3. 35.2.3 Data Transmission
      4. 35.2.4 Serial IR (SIR)
      5. 35.2.5 9-Bit UART Mode
      6. 35.2.6 FIFO Operation
      7. 35.2.7 Interrupts
      8. 35.2.8 Loopback Operation
      9. 35.2.9 RTDMA Operation
        1. 35.2.9.1 Receiving Data Using UART with RTDMA
        2. 35.2.9.2 Transmitting Data Using UART with RTDMA
    3. 35.3 Initialization and Configuration
    4. 35.4 Software
      1. 35.4.1 UART Registers to Driverlib Functions
      2. 35.4.2 UART Examples
        1. 35.4.2.1 UART Academy Lab - SINGLE_CORE
        2. 35.4.2.2 UART Loopback - SINGLE_CORE
        3. 35.4.2.3 UART Loopback with Interrupt - SINGLE_CORE
        4. 35.4.2.4 UART Loopback with DMA - SINGLE_CORE
        5. 35.4.2.5 UART Echoback - SINGLE_CORE
    5. 35.5 UART Registers
      1. 35.5.1 UART Base Address Table
      2. 35.5.2 UART_REGS Registers
      3. 35.5.3 UART_REGS_WRITE Registers
  42. 36Local Interconnect Network (LIN)
    1. 36.1 LIN Overview
      1. 36.1.1 LIN Mode Features
      2. 36.1.2 SCI Mode Features
      3. 36.1.3 Block Diagram
    2. 36.2 Serial Communications Interface Module
      1. 36.2.1 SCI Communication Formats
        1. 36.2.1.1 SCI Frame Formats
        2. 36.2.1.2 SCI Asynchronous Timing Mode
        3. 36.2.1.3 SCI Baud Rate
          1. 36.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 36.2.1.4 SCI Multiprocessor Communication Modes
          1. 36.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 36.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 36.2.1.5 SCI Multibuffered Mode
      2. 36.2.2 SCI Interrupts
        1. 36.2.2.1 Transmit Interrupt
        2. 36.2.2.2 Receive Interrupt
        3. 36.2.2.3 WakeUp Interrupt
        4. 36.2.2.4 Error Interrupts
      3. 36.2.3 SCI RTDMA Interface
        1. 36.2.3.1 Receive RTDMA Requests
        2. 36.2.3.2 Transmit RTDMA Requests
      4. 36.2.4 SCI Configurations
        1. 36.2.4.1 Receiving Data
          1. 36.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 36.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 36.2.4.2 Transmitting Data
          1. 36.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 36.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 36.2.5 SCI Low-Power Mode
        1. 36.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 36.3 Local Interconnect Network Module
      1. 36.3.1 LIN Communication Formats
        1. 36.3.1.1  LIN Standards
        2. 36.3.1.2  Message Frame
          1. 36.3.1.2.1 Message Header
          2. 36.3.1.2.2 Response
        3. 36.3.1.3  Synchronizer
        4. 36.3.1.4  Baud Rate
          1. 36.3.1.4.1 Fractional Divider
          2. 36.3.1.4.2 Superfractional Divider
            1. 36.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 36.3.1.5  Header Generation
          1. 36.3.1.5.1 Event Triggered Frame Handling
          2. 36.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 36.3.1.6  Extended Frames Handling
        7. 36.3.1.7  Timeout Control
          1. 36.3.1.7.1 No-Response Error (NRE)
          2. 36.3.1.7.2 Bus Idle Detection
          3. 36.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 36.3.1.8  TXRX Error Detector (TED)
          1. 36.3.1.8.1 Bit Errors
          2. 36.3.1.8.2 Physical Bus Errors
          3. 36.3.1.8.3 ID Parity Errors
          4. 36.3.1.8.4 Checksum Errors
        9. 36.3.1.9  Message Filtering and Validation
        10. 36.3.1.10 Receive Buffers
        11. 36.3.1.11 Transmit Buffers
      2. 36.3.2 LIN Interrupts
      3. 36.3.3 Servicing LIN Interrupts
      4. 36.3.4 LIN RTDMA Interface
        1. 36.3.4.1 LIN Receive RTDMA Requests
        2. 36.3.4.2 LIN Transmit RTDMA Requests
      5. 36.3.5 LIN Configurations
        1. 36.3.5.1 Receiving Data
          1. 36.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 36.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 36.3.5.2 Transmitting Data
          1. 36.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 36.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 36.4 Low-Power Mode
      1. 36.4.1 Entering Sleep Mode
      2. 36.4.2 Wakeup
      3. 36.4.3 Wakeup Timeouts
    5. 36.5 Emulation Mode
    6. 36.6 Software
      1. 36.6.1 LIN Registers to Driverlib Functions
      2. 36.6.2 LIN Examples
        1. 36.6.2.1 LIN Internal Loopback with Interrupts - SINGLE_CORE
        2. 36.6.2.2 LIN SCI Mode Internal Loopback with Interrupts - SINGLE_CORE
        3. 36.6.2.3 LIN SCI MODE Internal Loopback with DMA - SINGLE_CORE
        4. 36.6.2.4 LIN Internal Loopback without interrupts (polled mode) - SINGLE_CORE
        5. 36.6.2.5 LIN SCI MODE (Single Buffer) Internal Loopback with DMA - SINGLE_CORE
    7. 36.7 LIN Registers
      1. 36.7.1 LIN Base Address Table
      2. 36.7.2 LIN_REGS Registers
  43. 37Serial Peripheral Interface (SPI)
    1. 37.1 Introduction
      1. 37.1.1 Features
      2. 37.1.2 Block Diagram
    2. 37.2 System-Level Integration
      1. 37.2.1 SPI Module Signals
      2. 37.2.2 Configuring Device Pins
        1. 37.2.2.1 GPIOs Required for High-Speed Mode
      3. 37.2.3 SPI Interrupts
      4. 37.2.4 RTDMA Support
    3. 37.3 SPI Operation
      1. 37.3.1  Introduction to Operation
      2. 37.3.2  Controller Mode
      3. 37.3.3  Peripheral Mode
      4. 37.3.4  Data Format
        1. 37.3.4.1 Transmission of Bit from SPIRXBUF
      5. 37.3.5  Baud Rate Selection
        1. 37.3.5.1 Baud Rate Determination
        2. 37.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
        3. 37.3.5.3 Baud Rate Calculation
      6. 37.3.6  SPI Clocking Schemes
      7. 37.3.7  SPI FIFO Description
      8. 37.3.8  SPI RTDMA Transfers
        1. 37.3.8.1 Transmitting Data Using SPI with RTDMA
        2. 37.3.8.2 Receiving Data Using SPI with RTDMA
      9. 37.3.9  SPI High-Speed Mode
      10. 37.3.10 SPI 3-Wire Mode Description
    4. 37.4 Programming Procedure
      1. 37.4.1 Initialization Upon Reset
      2. 37.4.2 Configuring the SPI
      3. 37.4.3 Configuring the SPI for High-Speed Mode
      4. 37.4.4 Data Transfer Example
      5. 37.4.5 SPI 3-Wire Mode Code Examples
        1. 37.4.5.1 3-Wire Controller Mode Transmit
        2.       1753
          1. 37.4.5.2.1 3-Wire Controller Mode Receive
        3.       1755
          1. 37.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       1757
          1. 37.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 37.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 37.5 Software
      1. 37.5.1 SPI Registers to Driverlib Functions
      2. 37.5.2 SPI Examples
        1. 37.5.2.1 SPI Digital Loopback - SINGLE_CORE
        2. 37.5.2.2 SPI Digital Loopback with FIFO Interrupts - SINGLE_CORE
        3. 37.5.2.3 SPI Digital External Loopback without FIFO Interrupts - SINGLE_CORE
        4. 37.5.2.4 SPI Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        5. 37.5.2.5 SPI Digital Loopback with DMA - SINGLE_CORE
    6. 37.6 SPI Registers
      1. 37.6.1 SPI Base Address Table
      2. 37.6.2 SPI_REGS Registers
  44. 38Single Edge Nibble Transmission (SENT)
    1. 38.1 Introduction
      1. 38.1.1 Features
      2. 38.1.2 SENT Related Collateral
    2. 38.2 Advanced Topologies: MTPG
      1. 38.2.1 MTPG Features
      2. 38.2.2 MTPG Description
      3. 38.2.3 Channel Triggers
      4. 38.2.4 Timeout
    3. 38.3 Protocol Description
      1. 38.3.1 Nibble Frame Format
      2. 38.3.2 Cyclic Redundancy Check (CRC)
      3. 38.3.3 Short Serial Message Format
      4. 38.3.4 Enhanced Serial Message Format
      5. 38.3.5 Enhanced Serial Message Format CRC
      6. 38.3.6 Receive Modes
    4. 38.4 RTDMA Trigger
    5. 38.5 Interrupts Configuration
    6. 38.6 Glitch Filter
    7. 38.7 Software
      1. 38.7.1 SENT Registers to Driverlib Functions
      2. 38.7.2 SENT Examples
        1. 38.7.2.1 SENT Single Sensor - SINGLE_CORE
    8. 38.8 SENT Registers
      1. 38.8.1 SENT Base Address Table
      2. 38.8.2 SENT_CFG Registers
      3. 38.8.3 SENT_MEM Registers
      4. 38.8.4 SENT_MTPG Registers
  45.   ► SECURITY PERIPHERALS
    1.     Technical Reference Manual Overview
  46. 39Security Modules
    1. 39.1 Hardware Security Module (HSM)
      1. 39.1.1 HSM Related Collateral
    2. 39.2 Cryptographic Accelerators
  47. 40Revision History

33.7.2 I2C_REGS Registers

Table 33-9 lists the memory-mapped registers for the I2C_REGS registers. All register offset addresses not listed in Table 33-9 should be considered as reserved locations and the register contents should not be modified.

Table 33-9 I2C_REGS Registers
OffsetAcronymRegister NameProtection
0hI2COARI2C Own address
2hI2CIERI2C Interrupt Enable
4hI2CSTRI2C Status
6hI2CCLKLI2C Clock low-time divider
8hI2CCLKHI2C Clock high-time divider
AhI2CCNTI2C Data count
ChI2CDRRI2C Data receive
EhI2CTARI2C TARGET address
10hI2CDXRI2C Data Transmit
12hI2CMDRI2C Mode
14hI2CISRCI2C Interrupt Source
16hI2CEMDRI2C Extended Mode
18hI2CPSCI2C Prescaler
40hI2CFFTXI2C FIFO Transmit
42hI2CFFRXI2C FIFO Receive

Complex bit access types are encoded to fit into small table cells. Table 33-10 shows the codes that are used for access types in this section.

Table 33-10 I2C_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

37.7.2.1 I2COAR Register (Offset = 0h) [Reset = 0000h]

I2COAR is shown in Figure 33-21 and described in Table 33-11.

Return to the Summary Table.

The I2C own address register (I2COAR) is a 16-bit register. The I2C module uses this register to specify its own TARGET address, which distinguishes it from other TARGETs connected to the I2C-bus. If the 7-bit addressing mode is selected (XA = 0 in I2CMDR), only bits 6-0 are used
write 0s to bits 9-7.

Figure 33-21 I2COAR Register
15141312111098
RESERVEDOAR
R-0hR/W-0h
76543210
OAR
R/W-0h
Table 33-11 I2COAR Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0OARR/W0hIn 7-bit addressing mode (XA = 0 in I2CMDR):
00h-7Fh Bits 6-0 provide the 7-bit TARGET address of the I2C module. Write 0s to bits 9-7.

In 10-bit addressing mode (XA = 1 in I2CMDR):
000h-3FFh Bits 9-0 provide the 10-bit TARGET address of the I2C module.

Reset type: SYSRSn

37.7.2.2 I2CIER Register (Offset = 2h) [Reset = 0000h]

I2CIER is shown in Figure 33-22 and described in Table 33-12.

Return to the Summary Table.

I2CIER is used by the CPU to individually enable or disable I2C interrupt requests.

Figure 33-22 I2CIER Register
15141312111098
SCL_ECSRESERVED
R/W-0hR-0h
76543210
RESERVEDAATSCDXRDYRRDYARDYNACKARBL
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 33-12 I2CIER Register Field Descriptions
BitFieldTypeResetDescription
15SCL_ECSR/W0hSCL Extended Automatic Clock Stretch interrupt enable

Reset type: SYSRSn


0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled
14-7RESERVEDR0hReserved
6AATR/W0hAddressed as TARGET interrupt enable

Reset type: SYSRSn


0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled
5SCDR/W0hStop condition detected interrupt enable

Reset type: SYSRSn


0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled
4XRDYR/W0hTransmit-data-ready interrupt enable bit.
This bit should not be set when using FIFO mode.

Reset type: SYSRSn


0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled
3RRDYR/W0hReceive-data-ready interrupt enable bit.
This bit should not be set when using FIFO mode.

Reset type: SYSRSn


0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled
2ARDYR/W0hRegister-access-ready interrupt enable

Reset type: SYSRSn


0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled
1NACKR/W0hNo-acknowledgment interrupt enable

Reset type: SYSRSn


0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled
0ARBLR/W0hArbitration-lost interrupt enable

Reset type: SYSRSn


0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled

37.7.2.3 I2CSTR Register (Offset = 4h) [Reset = 0410h]

I2CSTR is shown in Figure 33-23 and described in Table 33-13.

Return to the Summary Table.

The I2C status register (I2CSTR) is a 16-bit register used to determine which interrupt has occurred and to read status information.

Figure 33-23 I2CSTR Register
15141312111098
SCL_ECSTDIRNACKSNTBBRSFULLXSMTAATAD0
R/W1C-0hR/W1C-0hR/W1C-0hR-0hR-0hR-1hR-0hR-0h
76543210
RESERVEDBYTESENTSCDXRDYRRDYARDYNACKARBL
R-0hR/W1C-0hR/W1C-0hR-1hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 33-13 I2CSTR Register Field Descriptions
BitFieldTypeResetDescription
15SCL_ECSR/W1C0hSCL Status bit in extended automatic clock stretching mode
0: SCL line is pulled high.
1: SCL line is pulled low after ACK (or) NACK phase. Writing '1' to this bit releases SCL. SCL line is pulled high.

Note: This bit is applicable only for extended clock stretching mode

Reset type: SYSRSn


0h (R/W) = SCL line is not pulled low in extended automatic clock stretching mode. SCL_ECS bit is cleared by one o fthe following events:
- It is manually cleared. To clear this bit, write a 1 to it.
- The I2C module is reset.
1h (R/W) = SCL line is pulled low in extended automatic clock stretching mode.
14TDIRR/W1C0hTARGET direction bit

Reset type: SYSRSn


0h (R/W) = I2C is not addressed as a TARGET transmitter. TDIR is cleared by one of the following events:
- It is manually cleared. To clear this bit, write a 1 to it.
- Digital loopback mode is enabled.
- A START or STOP condition occurs on the I2C bus.
1h (R/W) = I2C is addressed as a TARGET transmitter.
13NACKSNTR/W1C0hNACK sent bit.
This bit is used when the I2C module is in the receiver mode. One instance in which NACKSNT is affected is when the NACK mode is used (see the description for NACKMOD in

Reset type: SYSRSn


0h (R/W) = NACK not sent. NACKSNT bit is cleared by any one of the following events:
- It is manually cleared. To clear this bit, write a 1 to it.
- The I2C module is reset (either when 0 is written to the IRS bit of I2CMDR or when the whole device is reset).
1h (R/W) = NACK sent: A no-acknowledge bit was sent during the acknowledge cycle on the I2C-bus.
12BBR0hBus busy bit.
BB indicates whether the I2C-bus is busy or is free for another data transfer. See the paragraph following the table for more information

Reset type: SYSRSn


0h (R/W) = Bus free. BB is cleared by any one of the following events:
- The I2C module receives or transmits a STOP bit (bus free).
- The I2C module is reset.
1h (R/W) = Bus busy: The I2C module has received or transmitted a START bit on the bus.
11RSFULLR0hReceive shift register full bit.
RSFULL indicates an overrun condition during reception. Overrun occurs when new data is received into the shift register (I2CRSR) and the old data has not been read from the receive register (I2CDRR). As new bits arrive from the SDA pin, they overwrite the bits in I2CRSR. The new data will not be copied to ICDRR until the previous data is read.

Reset type: SYSRSn


0h (R/W) = No overrun detected. RSFULL is cleared by any one of the following events:
- I2CDRR is read by the CPU. Emulator reads of the I2CDRR do not affect this bit.
- The I2C module is reset.
1h (R/W) = Overrun detected
10XSMTR1hTransmit shift register empty bit.
XSMT = 0 indicates that the transmitter has experienced underflow. Underflow occurs when the transmit shift register (I2CXSR) is empty but the data transmit register (I2CDXR) has not been loaded since the last I2CDXR-to-I2CXSR transfer. The next I2CDXR-to-I2CXSR transfer will not occur until new data is in I2CDXR. If new data is not transferred in time, the previous data may be re-transmitted on the SDA pin.

Reset type: SYSRSn


0h (R/W) = Underflow detected (empty)
1h (R/W) = No underflow detected (not empty). XSMT is set by one of the following events:
- Data is written to I2CDXR.
- The I2C module is reset
9AATR0hAddressed-as-TARGET bit

Reset type: SYSRSn


0h (R/W) = In the 7-bit addressing mode, the AAT bit is cleared when receiving a NACK, a STOP condition, or a repeated START condition. In the 10-bit addressing mode, the AAT bit is cleared when receiving a NACK, a STOP condition, or by a TARGET address different from the I2C peripheral's own TARGET address.
1h (R/W) = The I2C module has recognized its own TARGET address or an address of all zeros (general call).
8AD0R0hAddress 0 bits

Reset type: SYSRSn


0h (R/W) = AD0 has been cleared by a START or STOP condition.
1h (R/W) = An address of all zeros (general call) is detected.
7RESERVEDR0hReserved
6BYTESENTR/W1C0hByte Transmit over indication.
BYTESENT is set when the CONTROLLER/TARGET has successfully sent the byte on SCL/SDA lines. This is diagnostic register which needs to be explicitly cleared by Software. In case not cleared the stale status would keep reflecting as no automated clear incorporated to avoid corner conditions.

Reset type: SYSRSn


0h (R/W) = The I2C module has not finished transmitting the next data byte. BYTESENT is cleared by any one of the following events:
- It is manually cleared. To clear this bit, write a 1 to it.
- The I2C module is reset.
1h (R/W) = The I2C module has completed the transmission of a byte.
5SCDR/W1C0hStop condition detected bit.
SCD is set when the I2C sends or receives a STOP condition. The I2C module delays clearing of the I2CMDR[STP] bit until the SCD bit is set.

Reset type: SYSRSn


0h (R/W) = STOP condition not detected since SCD was last cleared. SCD is cleared by any one of the following events:
- I2CISRC is read by the CPU when it contains the value 110b (stop condition detected). Emulator reads of the I2CISRC do not affect this bit.
- SCD is manually cleared. To clear this bit, write a 1 to it.
- The I2C module is reset.
1h (R/W) = A STOP condition has been detected on the I2C bus.
4XRDYR1hTransmit-data-ready interrupt flag bit. When not in FIFO mode, XRDY indicates that the data transmit register (I2CDXR) is ready to accept new data.
FCM=0 : When the previous data has been copied from I2CDXR to the transmit shift register (I2CXSR). The CPU can poll XRDY or use the XRDY interrupt request When in FIFO mode, use TXFFINT instead.
FCM=1: XRDY is asserted only when next data is required
it gets deasserted with write to I2CDXR. Both Polling and interrupt based data transfers are allowed in the FCM mode.

Reset type: SYSRSn


0h (R/W) = I2CDXR not ready. XRDY is cleared when data is written to I2CDXR.
1h (R/W) = I2CDXR ready: Data has been copied from I2CDXR to I2CXSR.
XRDY is also forced to 1 when the I2C module is reset.
3RRDYR/W1C0hReceive-data-ready interrupt flag bit.
When not in FIFO mode, RRDY indicates that the data receive register (I2CDRR) is ready to be read because data has been copied from the receive shift register (I2CRSR) to I2CDRR. The CPU can poll RRDY or use the RRDY interrupt request When in FIFO mode, use RXFFINT instead.

Reset type: SYSRSn


0h (R/W) = I2CDRR not ready. RRDY is cleared by any one of the following events:
- I2CDRR is read by the CPU. Emulator reads of the I2CDRR do not affect this bit.
- RRDY is manually cleared. To clear this bit, write a 1 to it.
- The I2C module is reset.
1h (R/W) = I2CDRR ready: Data has been copied from I2CRSR to I2CDRR.
2ARDYR/W1C0hRegister-access-ready interrupt flag bit (only Applicable when the I2C module is in the CONTROLLER mode).
ARDY indicates that the I2C module registers are ready to be accessed because the previously programmed address, data, and command values have been used. The CPU can poll ARDY or use the ARDY interrupt request

Reset type: SYSRSn


0h (R/W) = The registers are not ready to be accessed. ARDY is cleared by any one of the following events:
- The I2C module starts using the current register contents.
- ARDY is manually cleared. To clear this bit, write a 1 to it.
- The I2C module is reset.
1h (R/W) = The registers are ready to be accessed.
In the nonrepeat mode (RM = 0 in I2CMDR): If STP = 0 in I2CMDR, the ARDY bit is set when the internal data counter counts down to 0. If STP = 1, ARDY is not affected (instead, the I2C module generates a STOP condition when the counter reaches 0).
In the repeat mode (RM = 1): ARDY is set at the end of each byte transmitted from I2CDXR.
1NACKR/W1C0hNo-acknowledgment interrupt flag bit.
NACK applies when the I2C module is a CONTROLLER transmitter (or) TARGET transmitter. NACK indicates whether the I2C module has detected an acknowledge bit (ACK) or a noacknowledge bit (NACK). The CPU can poll NACK or use the NACK interrupt request.

Reset type: SYSRSn


0h (R/W) = ACK received/NACK not received. This bit is cleared by any one of the following events:
- An acknowledge bit (ACK) has been sent by the TARGET receiver.
- NACK is manually cleared. To clear this bit, write a 1 to it.
- The CPU reads the interrupt source register (I2CISRC) and the register contains the code for a NACK interrupt. Emulator reads of the I2CISRC do not affect this bit.
- The I2C module is reset.
1h (R/W) = NACK bit received. The hardware detects that a no-acknowledge (NACK) bit has been received.
Note: While the I2C module performs a general call transfer, NACK is 1, even if one or more TARGETs send acknowledgment.
0ARBLR/W1C0hArbitration-lost interrupt flag bit (only applicable when the I2C module is a CONTROLLER-transmitter).
ARBL primarily indicates when the I2C module has lost an arbitration contest with another CONTROLLERtransmitter. The CPU can poll ARBL or use the ARBL interrupt request.

Reset type: SYSRSn


0h (R/W) = Arbitration not lost. AL is cleared by any one of the following events:
- AL is manually cleared. To clear this bit, write a 1 to it.
- The CPU reads the interrupt source register (I2CISRC) and the register contains the code for an
AL interrupt. Emulator reads of the I2CISRC do not affect this bit.
- The I2C module is reset.
1h (R/W) = Arbitration lost. AL is set by any one of the following events:
- The I2C module senses that it has lost an arbitration with two or more competing transmitters that started a transmission almost simultaneously.
- The I2C module attempts to start a transfer while the BB (bus busy) bit is set to 1.
When AL becomes 1, the CNT and STP bits of I2CMDR are cleared, and the I2C module becomes a TARGET-receiver.

37.7.2.4 I2CCLKL Register (Offset = 6h) [Reset = 0000h]

I2CCLKL is shown in Figure 33-24 and described in Table 33-14.

Return to the Summary Table.

I2C Clock low-time divider

Figure 33-24 I2CCLKL Register
15141312111098
I2CCLKL
R/W-0h
76543210
I2CCLKL
R/W-0h
Table 33-14 I2CCLKL Register Field Descriptions
BitFieldTypeResetDescription
15-0I2CCLKLR/W0hClock low-time divide-down value.
To produce the low time duration of the CONTROLLER clock, the period of the module clock is multiplied by (ICCL + d). d is an adjustment factor based on the prescaler. See the Clock Divider Registers section of the Introduction for details.

Note: These bits must be set to a non-zero value for proper I2C clock generation.

Reset type: SYSRSn

37.7.2.5 I2CCLKH Register (Offset = 8h) [Reset = 0000h]

I2CCLKH is shown in Figure 33-25 and described in Table 33-15.

Return to the Summary Table.

I2C Clock high-time divider

Figure 33-25 I2CCLKH Register
15141312111098
I2CCLKH
R/W-0h
76543210
I2CCLKH
R/W-0h
Table 33-15 I2CCLKH Register Field Descriptions
BitFieldTypeResetDescription
15-0I2CCLKHR/W0hClock high-time divide-down value.
To produce the high time duration of the CONTROLLER clock, the period of the module clock is multiplied by (ICCL + d). d is an adjustment factor based on the prescaler. See the Clock Divider Registers section of the Introduction for details.

Note: These bits must be set to a non-zero value for proper I2C clock generation.

Reset type: SYSRSn

37.7.2.6 I2CCNT Register (Offset = Ah) [Reset = 0000h]

I2CCNT is shown in Figure 33-26 and described in Table 33-16.

Return to the Summary Table.

I2CCNT is a 16-bit register used to indicate how many data bytes to transfer when the I2C module is configured as a transmitter, or to receive when configured as a CONTROLLER receiver. In the repeat mode (RM = 1), I2CCNT is not used.

The value written to I2CCNT is copied to an internal data counter. The internal data counter is decremented by 1 for each byte transferred (I2CCNT remains unchanged). If a STOP condition is requested in the CONTROLLER mode (STP = 1 in I2CMDR), the I2C module terminates the transfer with a STOP condition when the countdown is complete (that is, when the last byte has been transferred).

Figure 33-26 I2CCNT Register
15141312111098
I2CCNT
R/W-0h
76543210
I2CCNT
R/W-0h
Table 33-16 I2CCNT Register Field Descriptions
BitFieldTypeResetDescription
15-0I2CCNTR/W0hData count value. I2CCNT indicates the number of data bytes to transfer or receive.
If a STOP condition is specified (STP=1) then I2CCNT will decrease after each byte is sent until it reaches zero, which in turn will generate a STOP condition.
The value in I2CCNT is a don't care when the RM bit in I2CMDR is set to 1.

Reset type: SYSRSn


0h (R/W) = data count value is 65536
1h (R/W) = data count value is 1
2h (R/W) = data count value is 2
FFFFh (R/W) = data count value is 65535

37.7.2.7 I2CDRR Register (Offset = Ch) [Reset = 0000h]

I2CDRR is shown in Figure 33-27 and described in Table 33-17.

Return to the Summary Table.

I2CDRR is a 16-bit register used by the CPU to read received data. The I2C module can receive a data byte with 1 to 8 bits. The number of bits is selected with the bit count (BC) bits in I2CMDR. One bit at a time is shifted in from the SDA pin to the receive shift register (I2CRSR). When a complete data byte has been received, the I2C module copies the data byte from I2CRSR to I2CDRR. The CPU cannot access I2CRSR directly.

If a data byte with fewer than 8 bits is in I2CDRR, the data value is right-justified, and the other bits of I2CDRR(7-0) are undefined. For example, if BC = 011 (3-bit data size), the receive data is in I2CDRR(2-0), and the content of I2CDRR(7-3) is undefined.

When in the receive FIFO mode, the I2CDRR register acts as the receive FIFO buffer.

Figure 33-27 I2CDRR Register
15141312111098
RESERVED
R-0h
76543210
DATA
R-0h
Table 33-17 I2CDRR Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0hReserved
7-0DATAR0hReceive data

Reset type: SYSRSn

37.7.2.8 I2CTAR Register (Offset = Eh) [Reset = 03FFh]

I2CTAR is shown in Figure 33-28 and described in Table 33-18.

Return to the Summary Table.

The I2C TARGET address register (I2CSAR) is a 16-bit register for storing the next TARGET address that will be transmitted by the I2C module when it is a CONTROLLER. The SAR field of I2CSAR contains a 7-bit or 10-bit TARGET address. When the I2C module is not using the free data format (FDF = 0 in I2CMDR), it uses this address to initiate data transfers with a TARGET, or TARGETs. When the address is nonzero, the address is for a particular TARGET. When the address is 0, the address is a general call to all TARGETs. If the 7-bit addressing mode is selected (XA = 0 in I2CMDR), only bits 6-0 of I2CSAR are used
write 0s to bits 9-7.

Figure 33-28 I2CTAR Register
15141312111098
RESERVEDTAR
R-0hR/W-3FFh
76543210
TAR
R/W-3FFh
Table 33-18 I2CTAR Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0TARR/W3FFhIn 7-bit addressing mode (XA = 0 in I2CMDR):
00h-7Fh Bits 6-0 provide the 7-bit TARGET address that the I2C module transmits when it is in the CONTROLLER-transmitter
mode. Write 0s to bits 9-7.

In 10-bit addressing mode (XA = 1 in I2CMDR):
000h-3FFh Bits 9-0 provide the 10-bit TARGET address that the I2C module transmits when it is in the CONTROLLER transmitter mode.

Reset type: SYSRSn

37.7.2.9 I2CDXR Register (Offset = 10h) [Reset = 0000h]

I2CDXR is shown in Figure 33-29 and described in Table 33-19.

Return to the Summary Table.

The CPU writes transmit data to I2CDXR. This 16-bit register accepts a data byte with 1 to 8 bits. Before writing to I2CDXR, specify how many bits are in a data byte by loading the appropriate value into the bit count (BC) bits of I2CMDR. When writing a data byte with fewer than 8 bits, make sure the value is right-aligned in I2CDXR.

After a data byte is written to I2CDXR, the I2C module copies the data byte to the transmit shift register (I2CXSR). The CPU cannot access I2CXSR directly. From I2CXSR, the I2C module shifts the data byte out on the SDA pin, one bit at a time.

When in the transmit FIFO mode, the I2CDXR register acts as the transmit FIFO buffer.

Figure 33-29 I2CDXR Register
15141312111098
RESERVED
R-0h
76543210
DATA
R/W-0h
Table 33-19 I2CDXR Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0hReserved
7-0DATAR/W0hTransmit data

Reset type: SYSRSn

37.7.2.10 I2CMDR Register (Offset = 12h) [Reset = 0000h]

I2CMDR is shown in Figure 33-30 and described in Table 33-20.

Return to the Summary Table.

The I2C mode register (I2CMDR) is a 16-bit register that contains the control bits of the I2C module.

Figure 33-30 I2CMDR Register
15141312111098
NACKMODFREESTTRESERVEDSTPCNTTRXXA
R/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RMDLBIRSSTBFDFBC
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 33-20 I2CMDR Register Field Descriptions
BitFieldTypeResetDescription
15NACKMODR/W0hNACK mode bit. This bit is only applicable when the I2C module is acting as a receiver.

Reset type: SYSRSn


0h (R/W) = In the TARGET-receiver mode: The I2C module sends an acknowledge (ACK) bit to the transmitter during each acknowledge cycle on the bus. The I2C module only sends a no-acknowledge (NACK) bit if you set the NACKMOD bit.

In the CONTROLLER-receiver mode: The I2C module sends an ACK bit during each acknowledge cycle until the internal data counter counts down to 0. At that point, the I2C module sends a NACK bit to the transmitter. To have a NACK bit sent earlier, you must set the NACKMOD bit
1h (R/W) = In either TARGET-receiver or CONTROLLER-receiver mode: The I2C module sends a NACK bit to the transmitter during the next acknowledge cycle on the bus. Once the NACK bit has been sent, NACKMOD is cleared.

Important: To send a NACK bit in the next acknowledge cycle, you must set NACKMOD before the rising edge of the last data bit.
14FREER/W0hThis bit controls the action taken by the I2C module when a debugger breakpoint is encountered.

Reset type: SYSRSn


0h (R/W) = When I2C module is CONTROLLER:
If SCL is low when the breakpoint occurs, the I2C module stops immediately and keeps driving SCL low, whether the I2C module is the transmitter or the receiver. If SCL is high, the I2C module waits until SCL becomes low and then stops.
When I2C module is TARGET:
A breakpoint forces the I2C module to stop when the current transmission/reception is complete.
1h (R/W) = The I2C module runs free
that is, it continues to operate when a breakpoint occurs.
13STTR/W0hSTART condition bit (only applicable when the I2C module is a CONTROLLER). The RM, STT, and STP bits determine when the I2C module starts and stops data transmissions (see Table 9-6). Note that the STT and STP bits can be used to terminate the repeat mode, and that this bit is not writable when IRS = 0.

Reset type: SYSRSn


0h (R/W) = In the CONTROLLER mode, STT is automatically cleared after the START condition has been generated.
1h (R/W) = In the CONTROLLER mode, setting STT to 1 causes the I2C module to generate a START condition on the I2C-bus
12RESERVEDR0hReserved
11STPR/W0hSTOP condition bit (only applicable when the I2C module is a CONTROLLER).
In the CONTROLLER mode, the RM,STT, and STP bits determine when the I2C module starts and stops data transmissions.
Note that the STT and STP bits can be used to terminate the repeat mode, and that this bit is not writable when IRS=0. When in non-repeat mode, at least one byte must be transferred before a stop condition can be generated. The I2C module delays clearing of this bit until after the I2CSTR[SCD] bit is set. To avoid disrupting the I2C state machine, the user must wait until this bit is clear before initiating a new message.

Reset type: SYSRSn


0h (R/W) = STP is automatically cleared after the STOP condition has been generated
1h (R/W) = STP has been set by the device to generate a STOP condition when the internal data counter of the I2C module counts down to 0.
10CNTR/W0hCONTROLLER mode bit.
CNT determines whether the I2C module is in the TARGET mode or the CONTROLLER mode. CNT is automatically changed from 1 to 0 when the I2C CONTROLLER generates a STOP condition

Reset type: SYSRSn


0h (R/W) = TARGET mode. The I2C module is a TARGET and receives the serial clock from the CONTROLLER.
1h (R/W) = CONTROLLER mode. The I2C module is a CONTROLLER and generates the serial clock on the SCL pin.
9TRXR/W0hTransmitter mode bit.
When relevant, TRX selects whether the I2C module is in the transmitter mode or the receiver mode.

Reset type: SYSRSn


0h (R/W) = Receiver mode. The I2C module is a receiver and receives data on the SDA pin.
1h (R/W) = Transmitter mode. The I2C module is a transmitter and transmits data on the SDA pin.
8XAR/W0hExpanded address enable bit.

Reset type: SYSRSn


0h (R/W) = 7-bit addressing mode (normal address mode). The I2C module transmits 7-bit TARGET addresses (from bits 6-0 of I2CTAR), and its own TARGET address has 7 bits (bits 6-0 of I2COAR).
1h (R/W) = 10-bit addressing mode (expanded address mode). The I2C module transmits 10-bit TARGET addresses (from bits 9-0 of I2CTAR), and its own TARGET address has 10 bits (bits 9-0 of I2COAR).
7RMR/W0hRepeat mode bit (only applicable when the I2C module is a CONTROLLER-transmitter or CONTROLLER-receiver).
The RM, STT, and STP bits determine when the I2C module starts and stops data transmissions

Reset type: SYSRSn


0h (R/W) = Nonrepeat mode. The value in the data count register (I2CCNT) determines how many bytes are
received/transmitted by the I2C module.
1h (R/W) = Repeat mode. A data byte is transmitted each time the I2CDXR register is written to (or until the transmit FIFO is empty when in FIFO mode) until the STP bit is manually set. The value of I2CCNT is ignored. The ARDY bit/interrupt can be used to determine when the I2CDXR (or FIFO) is ready for more data, or when the data has all been sent and the CPU is allowed to write to the STP bit.
6DLBR/W0hDigital loopback mode bit.

Reset type: SYSRSn


0h (R/W) = Digital loopback mode is disabled.
1h (R/W) = Digital loopback mode is enabled. For proper operation in this mode, the CNT bit must be 1.
In the digital loopback mode, data transmitted out of I2CDXR is received in I2CDRR after n device cycles by an internal path, where:
n = ((I2C input clock frequency/module clock frequency) x 8)
The transmit clock is also the receive clock. The address transmitted on the SDA pin is the address in I2COAR.
Note: The free data format (FDF = 1) is not supported in the digital loopback mode.
5IRSR/W0hI2C module reset bit.

Reset type: SYSRSn


0h (R/W) = The I2C module is in reset/disabled. When this bit is cleared to 0, all status bits (in I2CSTR) are set to their default values.
1h (R/W) = The I2C module is enabled. This has the effect of releasing the I2C bus if the I2C peripheral is holding it.
4STBR/W0hSTART byte mode bit. This bit is only applicable when the I2C module is a CONTROLLER. As described in version 2.1 of the Philips Semiconductors I2C-bus specification, the START byte can be used to help a TARGET that needs extra time to detect a START condition. When the I2C module is a TARGET, it ignores a START byte from a CONTROLLER, regardless of the value of the STB bit.

Reset type: SYSRSn


0h (R/W) = The I2C module is not in the START byte mode.
1h (R/W) = The I2C module is in the START byte mode. When you set the START condition bit (STT), the I2C module begins the transfer with more than just a START condition. Specifically, it generates:
1. A START condition
2. A START byte (0000 0001b)
3. A dummy acknowledge clock pulse
4. A repeated START condition
Then, as normal, the I2C module sends the TARGET address that is in I2CTAR.
3FDFR/W0hFree data format mode bit.

Reset type: SYSRSn


0h (R/W) = Free data format mode is disabled. Transfers use the 7-/10-bit addressing format selected by the XA bit.
1h (R/W) = Free data format mode is enabled. Transfers have the free data (no address) format described in Section 9.2.5.
The free data format is not supported in the digital loopback mode (DLB=1).
2-0BCR/W0hBit count bits.
BC defines the number of bits (1 to 8) in the next data byte that is to be received or transmitted by the I2C module. The number of bits selected with BC must match the data size of the other device. Notice that when BC = 000b, a data byte has 8 bits. BC does not affect address bytes, which always have 8 bits.
Note: If the bit count is less than 8, receive data is right-justified in I2CDRR(7-0), and the other bits of I2CDRR(7-0) are undefined. Also, transmit data written to I2CDXR must be right-justified

Reset type: SYSRSn


0h (R/W) = 8 bits per data byte
1h (R/W) = 1 bit per data byte
2h (R/W) = 2 bits per data byte
3h (R/W) = 3 bits per data byte
4h (R/W) = 4 bits per data byte
5h (R/W) = 5 bits per data byte
6h (R/W) = 6 bits per data byte
7h (R/W) = 7 bits per data byte

37.7.2.11 I2CISRC Register (Offset = 14h) [Reset = 0000h]

I2CISRC is shown in Figure 33-31 and described in Table 33-21.

Return to the Summary Table.

The I2C interrupt source register (I2CISRC) is a 16-bit register used by the CPU to determine which event generated the I2C interrupt.

Figure 33-31 I2CISRC Register
15141312111098
RESERVEDWRITE_ZEROS
R-0hR/W-0h
76543210
RESERVEDINTCODE
R-0hR-0h
Table 33-21 I2CISRC Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0hReserved
11-8WRITE_ZEROSR/W0hTI internal testing bits
These reserved bit locations should always be written as zeros.

Reset type: SYSRSn

7-4RESERVEDR0hReserved
3-0INTCODER0hInterrupt code bits.
The binary code in INTCODE indicates the event that generated an I2C interrupt.

A CPU read will clear this field. If another lower priority interrupt is pending and enabled, the value corresponding to that interrupt will then be loaded. Otherwise, the value will stay cleared.
The interrupt events below are listed in descending order of priority. That is INTCODE 1 (Arbitration lost) has the highest priority and INTCODE 7 (Addressed as TARGET) has the lowest priority.
In the case of an arbitration lost, a no-acknowledgment condition detected, or a stop condition detected, a CPU read will also clear the associated interrupt flag bit in the I2CSTR register.
Emulator reads will not affect the state of this field or of the status bits in the I2CSTR register.

Reset type: SYSRSn


0h (R/W) = None
1h (R/W) = Arbitration lost
2h (R/W) = No-acknowledgment condition detected
3h (R/W) = Registers ready to be accessed
4h (R/W) = Receive data ready
5h (R/W) = Transmit data ready
6h (R/W) = Stop condition detected
7h (R/W) = Addressed as TARGET
8h (R/W) = Extended Automatic Clock Stretching

37.7.2.12 I2CEMDR Register (Offset = 16h) [Reset = 0001h]

I2CEMDR is shown in Figure 33-32 and described in Table 33-22.

Return to the Summary Table.

The I2CEMDR is a 16-bit register that enables additional I2C features such as forward / backward compatibility and types of clock stretching.

Figure 33-32 I2CEMDR Register
15141312111098
RESERVEDRESERVEDNACK_CM
R/W-0hR-0hR/W-0h
76543210
SCLKEYMCSECSFCMBC
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1h
Table 33-22 I2CEMDR Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0hReserved
14-9RESERVEDR0hReserved
8NACK_CMR/W0hNACK Compatibility mode
0: I2CSTR.NACK bit and NACK interrupt gets triggered when NACK is received in Controller Transmitter mode.
1: I2CSTR.NACK bit and NACK interrupt gets triggered when NACK is received in both Controller Transmitter mode and Target Transmitter mode

Reset type: SYSRSn

7-4SCLKEYR/W0hClock Stretching Key.
0xA: Writes to all bits related to Clock Stretching modes in this register are enabled.
Other Values: Writes to all bits related to Clock Stretching modes in this register are ignored.

Reset type: SYSRSn

3MCSR/W0hManual Clock Stretching mode
0: Manual Clock Stretching is disabled and SCL line is pulled high.
1: Manual Clock Stretching is enabled and SCL line is pulled low, allowing software to control clock stretching before or after every ACK / NACK cycle.

Note: When SCLKEY is not set to 0xA, Manual Clock Stretching mode will remain disabled.
Note: MCS should be disabled when other clock stretching modes are enabled to prevent a bus hang.

Reset type: SYSRSn

2ECSR/W0hExtended Automatic Clock Stretching mode
0: Extended Automatic Clock Stretching feature is disabled
1: Extended Automatic Clock Stretching feature is enabled. When enabled, I2C target automatically clock stretches after every ACK / NACK cycle.

Note: When SCLKEY is not set to 0xA, Extended Automatic Clock Stretching mode will remain disabled.

Reset type: SYSRSn

1FCMR/W0hForward Compatibility mode.
This bit when programmed brings the functionality of Tx request only when Tx data required regardless of data status in Tx buffer for non-FIFO mode.
This register affects the XRDY behavior hence needs to be set after releasing the IRS (I2CMDR[5]).

Reset type: SYSRSn

0BCR/W1hBackwards compatibility mode.
This bit affects the timing of the transmit status bits (XRDY and XSMT) in the I2CSTR register when in TARGET transmitter mode.

Reset type: SYSRSn


0h (R/W) = See the 'Backwards Compatibility Mode Bit, TARGET Transmitter' Figure for details.
1h (R/W) = See the 'Backwards Compatibility Mode Bit, TARGET Transmitter' Figure for details.

37.7.2.13 I2CPSC Register (Offset = 18h) [Reset = 0000h]

I2CPSC is shown in Figure 33-33 and described in Table 33-23.

Return to the Summary Table.

The I2C prescaler register (I2CPSC) is a 16-bit register (see Figure 14-21) used for dividing down the I2C input clock to obtain the desired module clock for the operation of the I2C module. See the device-specific data manual for the supported range of values for the module clock frequency.

IPSC must be initialized while the I2C module is in reset (IRS = 0 in I2CMDR). The prescaled frequency takes effect only when IRS is changed to 1. Changing the IPSC value while IRS = 1 has no effect.

Figure 33-33 I2CPSC Register
15141312111098
RESERVED
R-0h
76543210
IPSC
R/W-0h
Table 33-23 I2CPSC Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0hReserved
7-0IPSCR/W0hI2C prescaler divide-down value.
IPSC determines how much the CPU clock is divided to create the module clock of the I2C module:
module clock frequency = I2C input clock frequency/(IPSC + 1)
Note: IPSC must be initialized while the I2C module is in reset (IRS = 0 in I2CMDR).

Reset type: SYSRSn

37.7.2.14 I2CFFTX Register (Offset = 40h) [Reset = 0000h]

I2CFFTX is shown in Figure 33-34 and described in Table 33-24.

Return to the Summary Table.

The I2C transmit FIFO register (I2CFFTX) is a 16-bit register that contains the I2C FIFO mode enable bit as well as the control and status bits for the transmit FIFO mode of operation on the I2C peripheral.

Figure 33-34 I2CFFTX Register
15141312111098
RESERVEDI2CFFENTXFFRSTTXFFST
R-0hR/W-0hR/W-0hR-0h
76543210
TXFFINTTXFFINTCLRTXFFIENATXFFIL
R-0hR-0/W1S-0hR/W-0hR/W-0h
Table 33-24 I2CFFTX Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0hReserved
14I2CFFENR/W0hI2C FIFO mode enable bit.
This bit must be enabled for either the transmit or the receive FIFO to operate correctly.

Reset type: SYSRSn


0h (R/W) = Disable the I2C FIFO mode.
1h (R/W) = Enable the I2C FIFO mode.
13TXFFRSTR/W0hTransmit FIFO Reset

Reset type: SYSRSn


0h (R/W) = Reset the transmit FIFO pointer to 0000 and hold the transmit FIFO in the reset state.
1h (R/W) = Enable the transmit FIFO operation.
12-8TXFFSTR0hContains the status of the transmit FIFO:
xxxxx Transmit FIFO contains xxxxx bytes.
00000 Transmit FIFO is empty.

Note: Since these bits are reset to zero, the transmit FIFO interrupt flag will be set when the transmit FIFO operation is enabled and the I2C is taken out of reset. This will generate a transmit FIFO interrupt if enabled. To avoid any detrimental effects from this, write a one to the TXFFINTCLR once the transmit FIFO operation is enabled and the I2C is taken out of reset.

Reset type: SYSRSn

7TXFFINTR0hTransmit FIFO interrupt flag.
This bit cleared by a CPU write of a 1 to the TXFFINTCLR bit. If the TXFFIENA bit is set, this bit will generate an interrupt when it is set.

Reset type: SYSRSn


0h (R/W) = Transmit FIFO interrupt condition has not occurred.
1h (R/W) = Transmit FIFO interrupt condition has occurred.
6TXFFINTCLRR-0/W1S0hTransmit FIFO Interrupt Flag Clear

Reset type: SYSRSn


0h (R/W) = Writes of zeros have no effect. Reads return a 0.
1h (R/W) = Writing a 1 to this bit clears the TXFFINT flag.
5TXFFIENAR/W0hTransmit FIFO Interrupt Enable

Reset type: SYSRSn


0h (R/W) = Disabled. TXFFINT flag does not generate an interrupt when set.
1h (R/W) = Enabled. TXFFINT flag does generate an interrupt when set.
4-0TXFFILR/W0hTransmit FIFO interrupt level.

These bits set the status level that will set the transmit interrupt flag. When the TXFFST4-0 bits reach a value equal to or less than these bits, the TXFFINT flag will be set. This will generate an interrupt if the TXFFIENA bit is set. Because the I2C on this device has a 16-level transmit FIFO, these bits cannot be configured for an interrupt of more than 16 FIFO levels.

Reset type: SYSRSn

37.7.2.15 I2CFFRX Register (Offset = 42h) [Reset = 0000h]

I2CFFRX is shown in Figure 33-35 and described in Table 33-25.

Return to the Summary Table.

The I2C receive FIFO register (I2CFFRX) is a 16-bit register that contains the control and status bits for the receive FIFO mode of operation on the I2C peripheral.

Figure 33-35 I2CFFRX Register
15141312111098
RESERVEDRXFFRSTRXFFST
R-0hR/W-0hR-0h
76543210
RXFFINTRXFFINTCLRRXFFIENARXFFIL
R-0hR-0/W1S-0hR/W-0hR/W-0h
Table 33-25 I2CFFRX Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0hReserved
13RXFFRSTR/W0hI2C receive FIFO reset bit

Reset type: SYSRSn


0h (R/W) = Reset the receive FIFO pointer to 0000 and hold the receive FIFO in the reset state.
1h (R/W) = Enable the receive FIFO operation.
12-8RXFFSTR0hContains the status of the receive FIFO:

xxxxx Receive FIFO contains xxxxx bytes
00000 Receive FIFO is empty.

Reset type: SYSRSn

7RXFFINTR0hReceive FIFO interrupt flag.
This bit cleared by a CPU write of a 1 to the RXFFINTCLR bit. If the RXFFIENA bit is set, this bit will generate an interrupt when it is set

Reset type: SYSRSn


0h (R/W) = Receive FIFO interrupt condition has not occurred.
1h (R/W) = Receive FIFO interrupt condition has occurred.
6RXFFINTCLRR-0/W1S0hReceive FIFO interrupt flag clear bit.

Reset type: SYSRSn


0h (R/W) = Writes of zeros have no effect. Reads return a zero.
1h (R/W) = Writing a 1 to this bit clears the RXFFINT flag.
5RXFFIENAR/W0hReceive FIFO interrupt enable bit.

Reset type: SYSRSn


0h (R/W) = Disabled. RXFFINT flag does not generate an interrupt when set.
1h (R/W) = Enabled. RXFFINT flag does generate an interrupt when set.
4-0RXFFILR/W0hReceive FIFO interrupt level.
These bits set the status level that will set the receive interrupt flag. When the RXFFST4-0 bits reach a value equal to or greater than these bits, the RXFFINT flag is set. This will generate an interrupt if the RXFFIENA bit is set.

Note: Since these bits are reset to zero, the receive FIFO interrupt flag will be set if the receive FIFO operation is enabled and the I2C is taken out of reset. This will generate a receive FIFO interrupt if enabled. To avoid this, modify these bits on the same instruction as or prior to setting the RXFFRST bit. Because the I2C on this device has a 16-level receive FIFO, these bits cannot be configured for an interrupt of more than 16 FIFO levels.

Reset type: SYSRSn