首頁 射頻 (RF) 與微波 RF PLL 與合成器
首頁
射頻 (RF) 與微波
RF PLL 與合成器

LMX2820

現行

具有相位同步功能、JESD 和頻率校準 <5μs 的 22.6 GHz 寬頻射頻合成器

立即訂購
產品規格表

LMX2820

現行
產品規格表 立即訂購

產品詳細資料

Frequency (max) (MHz) 22600 Frequency (min) (MHz) 45 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -134 Features Integer-boundary spurs (IBS) removal, Integrated VCO, JESD204B SYSREF, Multi-device sync, Phase adjustment, Ultra-fast VCO Calibration, Wideband Current consumption (mA) 500 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
Frequency (max) (MHz) 22600 Frequency (min) (MHz) 45 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -134 Features Integer-boundary spurs (IBS) removal, Integrated VCO, JESD204B SYSREF, Multi-device sync, Phase adjustment, Ultra-fast VCO Calibration, Wideband Current consumption (mA) 500 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
VQFNP (RTC) 48 49 mm² 7 x 7
  • Output frequency: 45 MHz to 22.6 GHz
  • 36-fs rms jitter (12 kHz – 95 MHz) at 6 GHz
  • High-performance PLL
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –134 dBc/Hz
    • -95 dBc Integer Mode Spurs (fPD=100 MHz)
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • Programmable input multiplier
    • Direct PFD input for offset mixing support allowing PLL N divider to be one for ultra-low jitter
  • 2.5-µs fast VCO calibration time
  • Mute pin with 200-ns mute/unmute time
  • –45-dBc VCO leakage with doubler enabled
  • Support for external VCO up to 22.6-GHz
  • Synchronization of output phase across multiple devices
  • Two differential RF outputs and one differential SYSREF output for JESD204B support
  • Output frequency: 45 MHz to 22.6 GHz
  • 36-fs rms jitter (12 kHz – 95 MHz) at 6 GHz
  • High-performance PLL
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –134 dBc/Hz
    • -95 dBc Integer Mode Spurs (fPD=100 MHz)
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • Programmable input multiplier
    • Direct PFD input for offset mixing support allowing PLL N divider to be one for ultra-low jitter
  • 2.5-µs fast VCO calibration time
  • Mute pin with 200-ns mute/unmute time
  • –45-dBc VCO leakage with doubler enabled
  • Support for external VCO up to 22.6-GHz
  • Synchronization of output phase across multiple devices
  • Two differential RF outputs and one differential SYSREF output for JESD204B support

The LMX2820 is a high-performance, wideband synthesizer that can generate any frequency in the range of 45 MHz to 22.6 GHz. The high performance PLL with figure of merit of –236 dBc/Hz and high phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2820 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. The fast calibration algorithm greatly reduces the VCO calibration time, enabling systems requiring fast frequency hopping. The LMX2820 can generate or repeat SYSREF that is compliant to the JESD204B standard, allowing for its use as a low-noise clock source for high-speed data converters. This synthesizer can also be used with an external VCO. A direct PFD input pin is provided to support offset mixing for low spurious transmission.

The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for onboard low-noise LDOs.

The LMX2820 is a high-performance, wideband synthesizer that can generate any frequency in the range of 45 MHz to 22.6 GHz. The high performance PLL with figure of merit of –236 dBc/Hz and high phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2820 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. The fast calibration algorithm greatly reduces the VCO calibration time, enabling systems requiring fast frequency hopping. The LMX2820 can generate or repeat SYSREF that is compliant to the JESD204B standard, allowing for its use as a low-noise clock source for high-speed data converters. This synthesizer can also be used with an external VCO. A direct PFD input pin is provided to support offset mixing for low spurious transmission.

The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for onboard low-noise LDOs.
filter 尋找其它 RF PLL 與合成器
下載 觀看有字幕稿的影片 影片

您可能會感興趣的類似產品

open-in-new 比較替代產品
功能與所比較的裝置相似
LMX1204 現行 具 JESD204B/C SYSREF 支援和相位同步的 12.8 GHz RF 緩衝器、倍頻器和分頻器 Up to 12.8-GHz clock buffer, multiplier and divider and five-channel JESD support

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 20
重要文件 類型 標題 格式選項 日期
* Data sheet LMX2820 22.6-GHz Wideband PLLatinum RF Synthesizer With Phase Synchronization and JESD204B Support datasheet (Rev. C) PDF | HTML 2021年 2月 4日
Application note Using Instant Calibration With the LMX2820 PDF | HTML 2025年 6月 14日
Application note Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 2025年 4月 11日
Application note Combining More than Two Signals for Better Noise PDF | HTML 2025年 3月 24日
Application brief Compilation of RF Synthesizer Resources PDF | HTML 2024年 10月 22日
Application note Sine to Square Wave Conversion Using Clock Buffers PDF | HTML 2024年 9月 3日
Application brief Common Mistakes While Designing With Rf Clock Synthesizers and How To Mitigate the Same PDF | HTML 2024年 8月 8日
Circuit design MASH_SEED Optimization and Impact on Spurs (LMX2820) PDF | HTML 2024年 8月 8日
Application brief High-Frequency Clock (> 20GHz) Skew Variation Between Two RF Synthesizers Across Temperature PDF | HTML 2024年 4月 26日
Application brief High-Frequency Delay Adjustments Between Two RF Synthesizers PDF | HTML 2024年 4月 26日
Application brief LMX2820 with Internal Doubler versus LMX2594 PDF | HTML 2024年 1月 16日
Application note LMX2820 RF Synthesizer Phase Noise Improvement With Alternative Topologies (Rev. A) PDF | HTML 2023年 5月 22日
Application note External Doubler Extends LMX2820 Operation to 44 GHz PDF | HTML 2023年 3月 31日
User guide How to Phase Synchronize Multiple LMX2820 Devices PDF | HTML 2022年 12月 19日
Application note High Isolation, Fast Frequency Switching With LMX2820 in Ping-Pong Architecture PDF | HTML 2022年 9月 20日
Application note Combining Two LMX2820 Synthesizer Outputs for Improved Phase Noise (Rev. A) PDF | HTML 2022年 3月 3日
User guide LMX2820 Register Map (Rev. A) 2020年 12月 9日
Application note Impact of PLL Jitter to GSPS ADC's SNR and Performance Optimization 2020年 11月 11日
Application note Dramatically Improve Your Lock Time with VCO Instant Calibration PDF | HTML 2020年 9月 17日
Certificate LMX2820EVM EU Declaration of Conformity (DoC) 2020年 6月 9日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

LMX2820EVM — LMX2820 22.6-GHz 寬頻射頻合成器評估模組

此評估模組適用於 22.6-GHz 寬頻 RF 合成器 LMX2820。此合成器支援 JESD204B 相容 SYSREF 訊號緩衝及產生。LMX2820 允許設計人員同步此裝置多重執行個體的輸出。
使用指南: PDF | HTML
TI.com 無法提供
支援軟體

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

支援產品和硬體

支援產品和硬體
下載選項
模擬型號

LMX2820 IBIS model

SNAM245.ZIP (45 KB) - IBIS Model
下載
設計工具

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。
立即進行設計
設計工具

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

支援產品和硬體

支援產品和硬體
下載選項
參考設計

TIDA-010230 — 適用雷達和 EW 應用的多通道射頻收發器、低雜訊時脈參考設計

在現代雷達和電子作戰 (EW) 系統中，有源電子掃描陣列 (AESA) 天線系統通常會搭配高速多通道 RF 收發器使用。這些系統需要能進行精確通道間偏斜調整的超低雜訊時脈，以獲得最佳系統性能，例如訊噪比 (SNR)、無雜散動態範圍 (SFDR)、IMD3 和有效位元數 (ENOB)。此參考設計展示了 LMX2820 和 LMK04832 架構的低雜訊 JESD204B 相容時脈，可為多個 AFE7950 提供最高 X 頻段的操作的並同步成 < 10 ps，此外可於 9-GSPS/3-GSPS DAC/ADC 時脈提高系統性能。
Design guide: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFNP (RTC) 48 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片