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LMK5C22212A

現行

具有 BAW VCO 的三 DPLL、雙 APLL、雙輸入和 12 輸出網路同步器 

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產品規格表

LMK5C22212A

現行
產品規格表 立即訂購

產品詳細資料

Function Clock network synchronizer Number of outputs 12 Output type CML, LVCMOS, LVDS, LVPECL RMS jitter (fs) 47 Features JESD204B Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 1250 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Operating temperature range (°C) -40 to 85 Number of input channels 2
Function Clock network synchronizer Number of outputs 12 Output type CML, LVCMOS, LVDS, LVPECL RMS jitter (fs) 47 Features JESD204B Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 1250 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Operating temperature range (°C) -40 to 85 Number of input channels 2
VQFN (RGC) 64 81 mm² 9 x 9
  • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks
    • 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
    • 50fs typical/ 62fs maximum RMS jitter at 245.76MHz

  • 2 high-performance Digital Phase Locked Loops (DPLLs) with 2 Analog Phase Locked Loops (APLLs)

    • Programmable DPLL loop filter bandwidth from 1mHz to 4kHz
    • < 1ppt DCO frequency adjustment step size
  • 2 differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital Holdover and Hitless Switching
  • 12 differential outputs with programmable HSDS, AC-LVPECL, LVDS and HSCL formats
    • Up to 16 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT0_P/N, OUT1_P/N, GPIO1 and GPIO2 and 10 differential outputs on OUT2_P/N to OUT11_P/N
    • 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 6 compliant
  • I2C or 3-wire/4-wire SPI
  • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks
    • 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
    • 50fs typical/ 62fs maximum RMS jitter at 245.76MHz

  • 2 high-performance Digital Phase Locked Loops (DPLLs) with 2 Analog Phase Locked Loops (APLLs)

    • Programmable DPLL loop filter bandwidth from 1mHz to 4kHz
    • < 1ppt DCO frequency adjustment step size
  • 2 differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital Holdover and Hitless Switching
  • 12 differential outputs with programmable HSDS, AC-LVPECL, LVDS and HSCL formats
    • Up to 16 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT0_P/N, OUT1_P/N, GPIO1 and GPIO2 and 10 differential outputs on OUT2_P/N to OUT11_P/N
    • 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 6 compliant
  • I2C or 3-wire/4-wire SPI

The LMK5C22212A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The network synchronizer integrates 2 DPLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a reference input.

APLL1 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology (known as the BAW APLL) and can generate output clocks with 40fs typical / 60fs maximum 12kHz to 20MHz RMS jitter at 491.52MHz, independent of the jitter and frequency of the XO and DPLL reference inputs. APLL2/DPLL2 provides an option for a second frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference clocks and performs a hitless switch between inputs upon detecting a switchover event. Zero-Delay Mode (ZDM) and phase cancellation can be enabled to control the phase relationship from input to outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.

The LMK5C22212A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The network synchronizer integrates 2 DPLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a reference input.

APLL1 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology (known as the BAW APLL) and can generate output clocks with 40fs typical / 60fs maximum 12kHz to 20MHz RMS jitter at 491.52MHz, independent of the jitter and frequency of the XO and DPLL reference inputs. APLL2/DPLL2 provides an option for a second frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference clocks and performs a hitless switch between inputs upon detecting a switchover event. Zero-Delay Mode (ZDM) and phase cancellation can be enabled to control the phase relationship from input to outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.
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重要文件 類型 標題 格式選項 日期
* Data sheet LMK5C22212A 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With JESD204B/C and BAW for Wireless Communications datasheet PDF | HTML 2024年 11月 22日
Application note Termination Guidelines for Differential and Single-Ended Signals PDF | HTML 2025年 12月 10日
User guide LMK5C22212A Programmer's Guide (Rev. A) PDF | HTML 2025年 11月 17日
Application note Oscillator Power Considerations for PLL Devices PDF | HTML 2025年 10月 30日

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LMK5B12212 評估模組 (EVM) 適用於開發 LMK5B12212 網路時鐘產生器和同步器。EVM 可用於裝置評估、合規測試和系統原型設計。  LMK5B12212 整合了三個類比 PLL (APLL)、三個數位 PLL (DPLL) 與可編程迴路頻寬。EVM 包括 SMA 連接器，用於時鐘輸入、振盪器輸入和時鐘輸出，以便與 50Ω 測試設備介接。板載 TCXO 可用來對 LMK5B12212 操作時的自由運轉、鎖定或維持模式進行評估。EVM 可透過板載 USB 微控制器 (MCU) 介面，使用配備 TICS Pro 軟體圖形使用者介面 (GUI) 的 PC 進行配置。TICS (...)

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