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LMK04828-EP

現行

溫度範圍為 -55°C 至 105°C 且符合 JESD204B 規範的超低雜訊時鐘抖動清除器

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產品規格表

LMK04828-EP

現行
產品規格表 立即訂購

產品詳細資料

Number of input channels 3 Number of outputs 14 RMS jitter (fs) 88 Features JESD204B Output frequency (min) (MHz) 0.001 Output frequency (max) (MHz) 3200 Output type LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.15 Supply voltage (max) (V) 3.3 Operating temperature range (°C) -55 to 105
Number of input channels 3 Number of outputs 14 RMS jitter (fs) 88 Features JESD204B Output frequency (min) (MHz) 0.001 Output frequency (max) (MHz) 3200 Output type LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.15 Supply voltage (max) (V) 3.3 Operating temperature range (°C) -55 to 105
WQFN (NKD) 64 81 mm² 9 x 9
  • EP Features
    • Gold Bondwires
    • Temperature Range: –55 to +105 °C
    • Lead Finish SnPb
  • Maximum Distribution Frequency: 3.2 GHz
  • JESD204B Support
  • Ultra-Low RMS Jitter
    • 88-fs RMS Jitter (12 kHz to 20 MHz)
    • 91-fs RMS Jitter (100 Hz to 20 MHz)
    • –162.5 dBc/Hz Noise Floor at 245.76 MHz
  • Up to 14 Differential Device Clocks From PLL2
    • Up to 7 SYSREF Clocks
    • Maximum Clock Output Frequency 3.2 GHz
    • LVPECL, LVDS, HSDS, LCPECL Programmable Outputs From PLL2
  • Up to 1 Buffered VCXO/Crystal Output From PLL1
    • LVPECL, LVDS, 2xLVCMOS Programmable
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Up to 3 Redundant Input Clocks
      • Automatic and Manual Switchover Modes
      • Hitless Switching and LOS
    • Integrated Low-Noise Crystal Oscillator Circuit
    • Holdover Mode When Input Clocks are Lost
  • PLL2
    • Normalized [1 Hz] PLL Noise Floor of
      –227 dBc/Hz
    • Phase Detector Rate up to 155 MHz
    • OSCin Frequency-Doubler
    • Two Integrated Low-Noise VCOs
  • 50% Duty Cycle Output Divides, 1 to 32
    (Even and Odd)
  • Precision Digital Delay, Dynamically Adjustable
  • 25-ps Step Analog Delay
  • 3.15-V to 3.45-V Operation
  • Package: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8 mm)
  • EP Features
    • Gold Bondwires
    • Temperature Range: –55 to +105 °C
    • Lead Finish SnPb
  • Maximum Distribution Frequency: 3.2 GHz
  • JESD204B Support
  • Ultra-Low RMS Jitter
    • 88-fs RMS Jitter (12 kHz to 20 MHz)
    • 91-fs RMS Jitter (100 Hz to 20 MHz)
    • –162.5 dBc/Hz Noise Floor at 245.76 MHz
  • Up to 14 Differential Device Clocks From PLL2
    • Up to 7 SYSREF Clocks
    • Maximum Clock Output Frequency 3.2 GHz
    • LVPECL, LVDS, HSDS, LCPECL Programmable Outputs From PLL2
  • Up to 1 Buffered VCXO/Crystal Output From PLL1
    • LVPECL, LVDS, 2xLVCMOS Programmable
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Up to 3 Redundant Input Clocks
      • Automatic and Manual Switchover Modes
      • Hitless Switching and LOS
    • Integrated Low-Noise Crystal Oscillator Circuit
    • Holdover Mode When Input Clocks are Lost
  • PLL2
    • Normalized [1 Hz] PLL Noise Floor of
      –227 dBc/Hz
    • Phase Detector Rate up to 155 MHz
    • OSCin Frequency-Doubler
    • Two Integrated Low-Noise VCOs
  • 50% Duty Cycle Output Divides, 1 to 32
    (Even and Odd)
  • Precision Digital Delay, Dynamically Adjustable
  • 25-ps Step Analog Delay
  • 3.15-V to 3.45-V Operation
  • Package: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8 mm)

The LMK04828-EP device is the industry’s highest performance clock conditioner with JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay make the LMK04828-EP ideal for providing flexible high-performance clocking trees.

The LMK04828-EP device is the industry’s highest performance clock conditioner with JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay make the LMK04828-EP ideal for providing flexible high-performance clocking trees.
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重要文件 類型 標題 格式選項 日期
* Data sheet LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner datasheet PDF | HTML 2017年 4月 3日
Application note Multi-Clock Synchronization 2019年 12月 30日

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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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LMK04828 IBIS Model (Rev. F)

SNAM148F.ZIP (175 KB) - IBIS Model
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PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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