LMK05318
- Ultra-low jitter BAW VCO based Ethernet clocks
- 32fs typical RMS jitter at 312.5MHz with 4MHz 1st order high-pass filter (HPF)
- 44fs typical RMS jitter at 156.25MHz with 4MHz 1st order HPF
- 50fs typical/ 80fs maximum RMS jitter at 312.5MHz
- 60fs typical/ 90fs maximum RMS jitter at 156.25MHz
- One high-performance Digital Phase-Locked Loop (DPLL) paired with two Analog Phase-Locked Loops (APLLs):
- 1mHz to 4kHz programmable DPLL loop bandwidth
- < 1ppt per step DCO adjustment for IEEE 1588 PTP clock steering
- Two differential or single-ended DPLL inputs
- 2MHz to 800MHz input frequency
- Digital holdover and hitless switching
- Eight differential outputs with programmable AC-LVPECL, AC-CML,
AC-LVDS, HSCL, and 1.8V LVCMOS output formats.
- 2MHz to 800MHz input frequency
- PCIe Gen 1 to 6 compliant
- I2C, 3-wire SPI, or 4-wire SPI
- 3.3V core supply and 1.8V, 2.5V, or 3.3V output supply
- –40°C to +85°C operating temperature
The LMK05318 is high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of Ethernet-based networking applications.
The device integrates one DPLL and two APLLs to provide hitless switching and jitter attenuation using the programmable loop bandwidths (LBWs) with one external loop filter capacitor to maximize the flexibility and ease of use.
APLL1 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology in VCO1 and can generate 312.5MHz output clocks with 50fs typical RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 features a conventional LC VCO to provide options for a second frequency and/or synchronization domain.
The integrated EEPROM can be used for custom system configurations on start-up. Internal LDO regulators provide excellent power supply noise rejection (PSNR) to reduce the cost and complexity of the power delivery network.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LMK05318 1-DPLL 2-APLL 2-IN 8-OUT Network Synchronizer With BAW VCO for Ethernet-Based Networking Applications datasheet (Rev. C) | PDF | HTML | 2026/5/13 | ||
| 應用說明 | Termination Guidelines for Differential and Single-Ended Signals | PDF | HTML | 2025/12/10 | |||
| 技術文章 | Solving synchronization challenges in Industrial Ethernet | PDF | HTML | 2019/7/19 | |||
| 使用指南 | LMK05318 Registers (Rev. A) | 2019/7/8 | ||||
| 技術文章 | TI BAW resonator innovation puts time on your side | PDF | HTML | 2019/3/5 | |||
| 技術文章 | Are you ready for BAW? | PDF | HTML | 2019/2/27 | |||
| 應用說明 | Understanding clocking needs for high-speed 56G PAM-4 serial links (Rev. A) | 2019/2/22 | ||||
| 應用說明 | Supported synchronization modes for TI network synchronizers (Rev. A) | 2019/2/22 | ||||
| 應用說明 | ITU-T G.8262 compliance test results for the LMK05318 (Rev. A) | 2019/2/22 | ||||
| 白皮書 | TI BAW technology enables ultra-low jitter clocks for high-speed networks | 2019/2/17 | ||||
| 應用說明 | How to use the LMK05318 as a jitter cleaner | 2019/1/16 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
德州儀器 (TI) 的時鐘及合成器 (TICS) 專業級軟體用於編程具有以下前置字元的產品編號的評估模組 (EVM)：CDC、LMK 和 LMX。這些產品包括鎖相迴路及電壓控制振盪器 (PLL+VCO)、合成器和時鐘裝置。
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。
PLLATINUMSIM-SW — PLL 迴路濾波器、相位雜訊、鎖定時間與雜散模擬工具
PLLATINUMSIM-SW 為一模擬工具，可讓使用者建立 PLLatinum™ 積體電路的詳細設計和模擬，包括 LMX 系列的相位鎖定迴路 (PLL) 及合成器。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。