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LMK04208

現行

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產品規格表

LMK04208

現行
產品規格表 立即訂購

產品詳細資料

Number of input channels 2 Number of outputs 7 RMS jitter (fs) 111 Features 0 Delay Output frequency (min) (MHz) 0.329 Output frequency (max) (MHz) 3072 Output type LVCMOS, LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.15 Supply voltage (max) (V) 3.45 Operating temperature range (°C) -40 to 85
Number of input channels 2 Number of outputs 7 RMS jitter (fs) 111 Features 0 Delay Output frequency (min) (MHz) 0.329 Output frequency (max) (MHz) 3072 Output type LVCMOS, LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.15 Supply voltage (max) (V) 3.45 Operating temperature range (°C) -40 to 85
WQFN (NKD) 64 81 mm² 9 x 9
  • Ultra-Low RMS Jitter Performance
    • 111 fs, RMS Jitter (12 kHz to 20 MHz)
    • 123 fs, RMS Jitter (100 Hz to 20 MHz)
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Integrated Low-Noise Crystal Oscillator Circuit
    • Holdover Mode when Input Clocks are Lost
      • Automatic or Manual Triggering/Recovery
  • PLL2
    • Normalized PLL Noise Floor of –227 dBc/Hz
    • Phase Detector Rate of Up to 155 MHz
    • OSCin Frequency-Doubler
    • Integrated Low-Noise VCO or External VCO Mode
  • Two Redundant Input Clocks with LOS
    • Automatic and Manual Switch-Over Modes
  • 50 % Duty Cycle Output Divides, 1 to 1045 (Even and Odd)
  • 6 LVPECL, LVDS, or LVCMOS Programmable Outputs
  • Digital Delay: Fixed or Dynamically Adjustable
  • 25 ps Step Analog Delay Control
  • 7 Differential Outputs, Up to 14 Single-Ended
    • Up to 6 VCXO/Crystal Buffered Outputs
  • Clock Rates of Up to 1536 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Industrial Temperature Range: –40°C to +85°C
  • 3.15-V to 3.45-V Operation
  • 64-Pin WQFN Package (9.0 × 9.0 × 0.8 mm)
  • Ultra-Low RMS Jitter Performance
    • 111 fs, RMS Jitter (12 kHz to 20 MHz)
    • 123 fs, RMS Jitter (100 Hz to 20 MHz)
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Integrated Low-Noise Crystal Oscillator Circuit
    • Holdover Mode when Input Clocks are Lost
      • Automatic or Manual Triggering/Recovery
  • PLL2
    • Normalized PLL Noise Floor of –227 dBc/Hz
    • Phase Detector Rate of Up to 155 MHz
    • OSCin Frequency-Doubler
    • Integrated Low-Noise VCO or External VCO Mode
  • Two Redundant Input Clocks with LOS
    • Automatic and Manual Switch-Over Modes
  • 50 % Duty Cycle Output Divides, 1 to 1045 (Even and Odd)
  • 6 LVPECL, LVDS, or LVCMOS Programmable Outputs
  • Digital Delay: Fixed or Dynamically Adjustable
  • 25 ps Step Analog Delay Control
  • 7 Differential Outputs, Up to 14 Single-Ended
    • Up to 6 VCXO/Crystal Buffered Outputs
  • Clock Rates of Up to 1536 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Industrial Temperature Range: –40°C to +85°C
  • 3.15-V to 3.45-V Operation
  • 64-Pin WQFN Package (9.0 × 9.0 × 0.8 mm)

The LMK04208 is a high performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum™ architecture is capable of 111 fs, RMS jitter (12 kHz to 20 MHz) using a low-noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.

The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.

The LMK04208 is a high performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum™ architecture is capable of 111 fs, RMS jitter (12 kHz to 20 MHz) using a low-noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.

The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.

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* Data sheet LMK04208 Low-Noise Clock Jitter Cleaner with Dual Loop PLLs datasheet PDF | HTML 2016年 9月 1日

設計與開發

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開發板

LMK04208EVM — 具有雙路串接 PLL 和整合 2.9 GHz VCO 的雙輸入、6+1 輸出時鐘抖動清除器

LMK04208EVM 可評估具測試設備或其他評估電路板的 LMK04208，以驗證特定應用項目的區塊或系統需求。  LMK04208 EVM 預先安裝了 122.88 MHz VCXO，適用於雙迴路運作。  若需不同頻率 VCXO 或特定 VCXO 進行性能評估，可替換該 VCXO。  該電路板可經過改裝，停用 VCXO 並將外部參考時鐘連接至 OSCin 埠，以實現 PLL2 單迴路運作模式。  CLKin1 輸入亦可設定為時鐘分頻/延遲/扇出配置模式來驅動電路板運作。  LMK04208 是一款多功能裝置，而 LMK04208 評估模組可讓您評估 LMK04208 的各種配置方式。

使用指南: PDF
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軟體程式設計工具

CODELOADER — CodeLoader Device Register Programming v4.19.0

The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.

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CLOCKDESIGNTOOL — Clock Design Tool Software

The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)

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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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模擬型號

LMK04208 IBIS Model

SNAM200.ZIP (111 KB) - IBIS Model
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設計工具

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。
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PLLATINUMSIM-SW — PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

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