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LMK04832-SP

現行

Radiation-hardened, QML-V, ultra-low-noise, 3.2GHz, 15-output clock jitter cleaner

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產品規格表

LMK04832-SP

現行
立即訂購

產品詳細資料

Number of input channels 3 Number of outputs 15 RMS jitter (fs) 54 Features +/-25ppm, 0 Delay, Integrated VCO, JESD204B, Loss of signal detection, Manual/auto switch, Programmable Delay, SPI Output frequency (max) (MHz) 3255 Output type CML, HSDS, LVCMOS, LVDS, LVPECL Input type HCSL, LVCMOS, LVCMOS (REF_CLK), LVDS, LVPECL, LVPECL (VCXO_CLK) Operating temperature range (°C) -55 to 125
Number of input channels 3 Number of outputs 15 RMS jitter (fs) 54 Features +/-25ppm, 0 Delay, Integrated VCO, JESD204B, Loss of signal detection, Manual/auto switch, Programmable Delay, SPI Output frequency (max) (MHz) 3255 Output type CML, HSDS, LVCMOS, LVDS, LVPECL Input type HCSL, LVCMOS, LVCMOS (REF_CLK), LVDS, LVPECL, LVPECL (VCXO_CLK) Operating temperature range (°C) -55 to 125
CFP (HBE) 64 118.81 mm² (10.9 mm × 10.9 mm)
  • SMD #5962R1723701VXC
    • Total ionizing dose 100 krad (ELDRS-free)
    • SEL immune >120 MeV × cm2/mg
    • SEFI immune >120 MeV × cm2/mg
  • Maximum clock output frequency: 3255 MHz
  • Multi-mode: dual PLL, single PLL, and clock distribution
  • 6-GHz external VCO or distribution input
  • Ultra-low noise, at 2500 MHz:
    • 54-fs RMS jitter (12 kHz to 20 MHz)
    • 64-fs RMS jitter (100 Hz to 20 MHz)
    • –157.6-dBc/Hz noise floor
  • Ultra-low noise, at 3200 MHz:
    • 61-fs RMS jitter (12 kHz to 20 MHz)
    • 67-fs RMS jitter (100 Hz to 100 MHz)
    • –156.5-dBc/Hz noise floor
  • PLL2
    • PLL FOM of –230 dBc/Hz
    • PLL 1/f of –128 dBc/Hz
    • Phase detector rate up to 320 MHz
    • Two integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHz
  • Up to 14 differential device clocks
    • CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs
  • Up to 1 buffered VCXO/XO output
    • LVPECL, LVDS, 2xLVCMOS programmable
  • 1-1023 CLKout divider
  • 1-8191 SYSREF divider
  • 25-ps step analog delay for SYSREF clocks
  • Digital delay and dynamic digital delay for device clock and SYSREF
  • Holdover mode with PLL1
  • 0-delay with PLL1 or PLL2
  • Ambient temperature range: –55 °C to 125 °C
  • SMD #5962R1723701VXC
    • Total ionizing dose 100 krad (ELDRS-free)
    • SEL immune >120 MeV × cm2/mg
    • SEFI immune >120 MeV × cm2/mg
  • Maximum clock output frequency: 3255 MHz
  • Multi-mode: dual PLL, single PLL, and clock distribution
  • 6-GHz external VCO or distribution input
  • Ultra-low noise, at 2500 MHz:
    • 54-fs RMS jitter (12 kHz to 20 MHz)
    • 64-fs RMS jitter (100 Hz to 20 MHz)
    • –157.6-dBc/Hz noise floor
  • Ultra-low noise, at 3200 MHz:
    • 61-fs RMS jitter (12 kHz to 20 MHz)
    • 67-fs RMS jitter (100 Hz to 100 MHz)
    • –156.5-dBc/Hz noise floor
  • PLL2
    • PLL FOM of –230 dBc/Hz
    • PLL 1/f of –128 dBc/Hz
    • Phase detector rate up to 320 MHz
    • Two integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHz
  • Up to 14 differential device clocks
    • CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs
  • Up to 1 buffered VCXO/XO output
    • LVPECL, LVDS, 2xLVCMOS programmable
  • 1-1023 CLKout divider
  • 1-8191 SYSREF divider
  • 25-ps step analog delay for SYSREF clocks
  • Digital delay and dynamic digital delay for device clock and SYSREF
  • Holdover mode with PLL1
  • 0-delay with PLL1 or PLL2
  • Ambient temperature range: –55 °C to 125 °C

The LMK04832-SP is a high performance clock conditioner with JEDEC JESD204B support for space applications.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The LMK04832-SP can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows the LMK04832-SP to provide flexible high performance clocking trees.

The LMK04832-SP comes in a 10.9-mm × 10.9-mm, 64-pin CFP package.

The LMK04832-SP is a high performance clock conditioner with JEDEC JESD204B support for space applications.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The LMK04832-SP can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows the LMK04832-SP to provide flexible high performance clocking trees.

The LMK04832-SP comes in a 10.9-mm × 10.9-mm, 64-pin CFP package.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 LMK04832-SP Space Grade Ultra-Low-Noise JESD204B Dual-Loop Clock Jitter Cleaner datasheet (Rev. C) PDF | HTML 2022/11/10
* 輻射及可靠性報告 LMK04832-SP Single-Event Effects Report 2021/5/13
* 輻射及可靠性報告 LMK04832-SP ELDRS Characterization Report 2020/11/19
* 輻射及可靠性報告 LMK04832-SP TID RLAT Report V009FOGX Wafer 21 2020/11/19
選擇指南 TI Space Products (Rev. L) 2026/3/27
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 2025/6/17
應用說明 Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 2025/6/10
應用說明 Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 2025/4/11
更多文件說明 TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 2025/2/20
應用說明 Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022/10/19
更多文件說明 Total Ionizing Dose and Single Event Effects Test Results of LMK04832-SP 2021/7/18
電子書 Radiation Handbook for Electronics (Rev. A) 2019/5/21

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

LMK04832EVM-CVAL — 適用於超低雜訊、雙迴路、JESD204B 時脈抖動清除器的 LMK04832-SP 評估模組

LMK04832EVM-CVAL 評估模組 (EVM) 提供的平台用於評估性能和
功能，適用於 LMK04832-SP 航太級超低雜訊 JESD204B 雙迴路時脈抖動清除器
技術這樣。
使用指南: PDF | HTML
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支援軟體

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

德州儀器 (TI) 的時鐘及合成器 (TICS) 專業級軟體用於編程具有以下前置字元的產品編號的評估模組 (EVM)：CDC、LMK 和 LMX。這些產品包括鎖相迴路及電壓控制振盪器 (PLL+VCO)、合成器和時鐘裝置。

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模擬型號

LMK04832-SP IBIS model (Rev. A)

SNAM242A.ZIP (168 KB) - IBIS 模型
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設計工具

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。

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設計工具

PLLATINUMSIM-SW — PLL 迴路濾波器、相位雜訊、鎖定時間與雜散模擬工具

PLLATINUMSIM-SW 為一模擬工具，可讓使用者建立 PLLatinum™ 積體電路的詳細設計和模擬，包括 LMX 系列的相位鎖定迴路 (PLL) 及合成器。

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參考設計

TIDA-010191 — 航太級多通道 JESD204B 15-GHz 時脈參考設計

相位陣列天線和數位波束成形技術，是提高未來航太雷達成像和寬頻衛星通訊系統的性能的關鍵技術。數位波束成形與類比波束成形不同，通常每個天線元件需要一套資料轉換器。這些轉換器需要具有具體定義相位關係的時鐘。此參考設計展示如何透過已定義及可調整相位關係，產生低雜訊 MHz 至 GHz 時脈訊號。在發生單一事件後，甚至可能恢復時脈階段。透過操作兩個 ADC12DJ3200QML-SP 評估模組，及在 3.2 GHz 時其對應之 FPGA 架構擷取平台，以及 10-ps 板對板偏斜的情況，藉此來展示 JESD204B 支援。
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