LMK5C33216
- BAW APLL with 40 fs RMS jitter at 491.52 MHz
- Three high-performance digital phase locked loops (DPLLs) with paired analog
phase locked loops (APLLs)
- Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz
- -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20 MHz TDC rate
- Two differential or single-ended DPLL inputs
- 1 Hz to 800 MHz differential
- Hitless switching with phase cancellation and/or phase slew control
- Priority based reference selection
- 16 outputs with programmable format
- 1000 MHz LVPECL/LVDS/HSDS
- 3000 MHz CML on OUT4 and OUT6
- 200 MHz LVCMOS on OUT0 and OUT1
- Single 3.3-V supply with internal LDOs
- I2C or 3-wire/4-wire SPI interface
- Requires single XO/TCXO/OCXO
- 40-bit DPLL or APLL DCO, < 1 ppt
- Holdover with phase build out upon exit
- Zero delay mode with programmable delay
- User programmable EEPROM
- Supports 105 °C PCB temperature
The LMK5C33216 is a high-performance network clock generator, synchronizer, and jitter attenuator with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications.
The LMK5C33216 integrates 3 DPLLs with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a DPLL reference input. The APLL reference determines the long term frequency accuracy.
The 3 APLLs may operate independent of their paired DPLL and be cascaded from another APLL to provide programmable frequency translation. APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) VCBO technology and can generate output clocks with 40-fs RMS jitter independent of the jitter and frequency of the XO and reference inputs. APLL1 and APLL2 provide options for additional frequency domains.
The device is fully programmable through I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW datasheet (Rev. B) | PDF | HTML | 2021/3/10 | ||
| 應用說明 | Termination Guidelines for Differential and Single-Ended Signals | PDF | HTML | 2025/12/10 | |||
| 應用說明 | ITU-T G.8262 Compliance Test Results for the LMK5C33216 | PDF | HTML | 2020/12/23 | |||
| 使用指南 | LMK5C33216 Programming Guide | PDF | HTML | 2020/12/18 |
設計與開發
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LMK5C33216EVM — LMK5C33216 時鐘同步器 DPLL 2 輸入 16 輸出評估模組
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
德州儀器 (TI) 的時鐘及合成器 (TICS) 專業級軟體用於編程具有以下前置字元的產品編號的評估模組 (EVM)：CDC、LMK 和 LMX。這些產品包括鎖相迴路及電壓控制振盪器 (PLL+VCO)、合成器和時鐘裝置。
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。
PLLATINUMSIM-SW — PLL 迴路濾波器、相位雜訊、鎖定時間與雜散模擬工具
PLLATINUMSIM-SW 為一模擬工具，可讓使用者建立 PLLatinum™ 積體電路的詳細設計和模擬，包括 LMX 系列的相位鎖定迴路 (PLL) 及合成器。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。