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LMK5C33216

現行

配備 JESD204B 的超低抖動時鐘同步器，用於與 BAW 進行無線通訊

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產品規格表

LMK5C33216

現行
產品規格表 立即訂購

產品詳細資料

Function Clock network synchronizer Number of outputs 16 Output type CML, LVCMOS, LVDS, LVPECL RMS jitter (fs) 50 Features JESD204B Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 3000 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Operating temperature range (°C) -40 to 85 Number of input channels 2
Function Clock network synchronizer Number of outputs 16 Output type CML, LVCMOS, LVDS, LVPECL RMS jitter (fs) 50 Features JESD204B Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 3000 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Operating temperature range (°C) -40 to 85 Number of input channels 2
VQFN (RGC) 64 81 mm² 9 x 9
  • BAW APLL with 40 fs RMS jitter at 491.52 MHz
  • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs)
    • Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz
    • -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20 MHz TDC rate
  • Two differential or single-ended DPLL inputs
    • 1 Hz to 800 MHz differential
    • Hitless switching with phase cancellation and/or phase slew control
    • Priority based reference selection
  • 16 outputs with programmable format
    • 1000 MHz LVPECL/LVDS/HSDS
    • 3000 MHz CML on OUT4 and OUT6
    • 200 MHz LVCMOS on OUT0 and OUT1
  • Single 3.3-V supply with internal LDOs
  • I2C or 3-wire/4-wire SPI interface
  • Requires single XO/TCXO/OCXO
  • 40-bit DPLL or APLL DCO, < 1 ppt
  • Holdover with phase build out upon exit
  • Zero delay mode with programmable delay
  • User programmable EEPROM
  • Supports 105 °C PCB temperature
  • BAW APLL with 40 fs RMS jitter at 491.52 MHz
  • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs)
    • Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz
    • -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20 MHz TDC rate
  • Two differential or single-ended DPLL inputs
    • 1 Hz to 800 MHz differential
    • Hitless switching with phase cancellation and/or phase slew control
    • Priority based reference selection
  • 16 outputs with programmable format
    • 1000 MHz LVPECL/LVDS/HSDS
    • 3000 MHz CML on OUT4 and OUT6
    • 200 MHz LVCMOS on OUT0 and OUT1
  • Single 3.3-V supply with internal LDOs
  • I2C or 3-wire/4-wire SPI interface
  • Requires single XO/TCXO/OCXO
  • 40-bit DPLL or APLL DCO, < 1 ppt
  • Holdover with phase build out upon exit
  • Zero delay mode with programmable delay
  • User programmable EEPROM
  • Supports 105 °C PCB temperature

The LMK5C33216 is a high-performance network clock generator, synchronizer, and jitter attenuator with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications.

The LMK5C33216 integrates 3 DPLLs with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a DPLL reference input. The APLL reference determines the long term frequency accuracy.

The 3 APLLs may operate independent of their paired DPLL and be cascaded from another APLL to provide programmable frequency translation. APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) VCBO technology and can generate output clocks with 40-fs RMS jitter independent of the jitter and frequency of the XO and reference inputs. APLL1 and APLL2 provide options for additional frequency domains.

The device is fully programmable through I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks.

The LMK5C33216 is a high-performance network clock generator, synchronizer, and jitter attenuator with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications.

The LMK5C33216 integrates 3 DPLLs with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a DPLL reference input. The APLL reference determines the long term frequency accuracy.

The 3 APLLs may operate independent of their paired DPLL and be cascaded from another APLL to provide programmable frequency translation. APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) VCBO technology and can generate output clocks with 40-fs RMS jitter independent of the jitter and frequency of the XO and reference inputs. APLL1 and APLL2 provide options for additional frequency domains.

The device is fully programmable through I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks.

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重要文件 類型 標題 格式選項 日期
* Data sheet LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW datasheet (Rev. B) PDF | HTML 2021年 3月 10日
Application note Termination Guidelines for Differential and Single-Ended Signals PDF | HTML 2025年 12月 10日
Application note ITU-T G.8262 Compliance Test Results for the LMK5C33216 PDF | HTML 2020年 12月 23日
User guide LMK5C33216 Programming Guide PDF | HTML 2020年 12月 18日

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LMK5C33216EVM — LMK5C33216 時鐘同步器 DPLL 2 輸入 16 輸出評估模組

LMK5C33216EVM 是適用於 LMK5C33216 網路時鐘產生器和同步器的評估模組 (EVM)。EVM 可用於裝置評估、合規測試和系統原型設計。  LMK5C33216 整合了三個類比 PLL (APLL)、三個數位 PLL (DPLL) 與可編程迴路頻寬。EVM 包括 SMA 連接器，用於時鐘輸入、振盪器輸入和時鐘輸出，以便與 50-Ω 測試設備介接。板載 TCXO 可用來對 LMK5C33216 操作時的自由運轉、鎖定或維持模式進行評估。EVM 可透過板載 USB 微控制器 (MCU) 介面，使用配備 TI TICS Pro 軟體圖形使用者介面 (GUI) 的 PC (...)
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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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LMK5C33216 IBIS model

SNAM241.ZIP (206 KB) - IBIS Model
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