產品詳細資料

Frequency (max) (MHz) 15000 Frequency (min) (MHz) 10 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129 Features Flexible ramp generation, Integer-boundary spurs (IBS) removal, Integrated VCO, JESD204B SYSREF, Multi-device sync, Phase adjustment, Wideband Current consumption (mA) 340 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
Frequency (max) (MHz) 15000 Frequency (min) (MHz) 10 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129 Features Flexible ramp generation, Integer-boundary spurs (IBS) removal, Integrated VCO, JESD204B SYSREF, Multi-device sync, Phase adjustment, Wideband Current consumption (mA) 340 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
VQFN (RHA) 40 36 mm² (6 mm × 6 mm)
  • 10-MHz to 15-GHz output frequency
  • –110 dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
  • 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
  • Programmable output power
  • PLL key specifications
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –129 dBc/Hz
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • 32-bit fractional-N divider
  • Remove integer boundary spurs with programmable input multiplier
  • Synchronization of output phase across multiple devices
  • Support for SYSREF with 9-ps resolution programmable delay
  • Frequency ramp and chirp generation ability for FMCW applications
  • < 20-µs VCO calibration speed
  • 3.3-V single power supply operation
  • 10-MHz to 15-GHz output frequency
  • –110 dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
  • 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
  • Programmable output power
  • PLL key specifications
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –129 dBc/Hz
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • 32-bit fractional-N divider
  • Remove integer boundary spurs with programmable input multiplier
  • Synchronization of output phase across multiple devices
  • Support for SYSREF with 9-ps resolution programmable delay
  • Frequency ramp and chirp generation ability for FMCW applications
  • < 20-µs VCO calibration speed
  • 3.3-V single power supply operation

The LMX2594 is a high-performance, wideband synthesizer that can generate any frequency from 10 MHz to 15 GHz without using an internal doubler, thus eliminating the need for sub-harmonic filters. The high-performance PLL with figure of merit of –236 dBc/Hz and high-phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2594 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows changing frequencies faster than 20 µs. The LMX2594 adds support for generating or repeating SYSREF (compliant to JESD204B standard) designed for low-noise clock sources in high-speed data converters. A fine delay adjustment (9-ps resolution) is provided in this configuration to account for delay differences of board traces.

The output drivers within LMX2594 deliver output power as high as 7 dBm at 15-GHz carrier frequency. The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for on-board low noise LDOs.

The LMX2594 is a high-performance, wideband synthesizer that can generate any frequency from 10 MHz to 15 GHz without using an internal doubler, thus eliminating the need for sub-harmonic filters. The high-performance PLL with figure of merit of –236 dBc/Hz and high-phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2594 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows changing frequencies faster than 20 µs. The LMX2594 adds support for generating or repeating SYSREF (compliant to JESD204B standard) designed for low-noise clock sources in high-speed data converters. A fine delay adjustment (9-ps resolution) is provided in this configuration to account for delay differences of board traces.

The output drivers within LMX2594 deliver output power as high as 7 dBm at 15-GHz carrier frequency. The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for on-board low noise LDOs.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 LMX2594 15-GHz Wideband PLLATINUM™ RF Synthesizer With Phase Synchronization and JESD204B Support datasheet (Rev. C) PDF | HTML 2019/4/17
應用說明 VCO Design Basic and Key Parameter for GSM Application (Rev. A) PDF | HTML 2026/4/21
應用說明 Leveraging TI’s Clock Tools For Converter Designs PDF | HTML 2026/4/20
應用說明 Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 2025/4/11
Application brief Compilation of RF Synthesizer Resources PDF | HTML 2024/10/22
應用說明 Sine to Square Wave Conversion Using Clock Buffers PDF | HTML 2024/9/3
Circuit design MASH_SEED Optimization and Impact on Spurs (LMX2820) PDF | HTML 2024/8/8
Application brief Using the MSP430FR5969 EVM to Program the LMX2594 PLL Synthesizer PDF | HTML 2024/4/26
Application brief LMX2820 with Internal Doubler versus LMX2594 PDF | HTML 2024/1/16
應用說明 Streamline RF Synthesizer VCO Calibration and Optimize PLL Lock Time (Rev. A) 2021/8/27
應用說明 Impact of PLL Jitter to GSPS ADC's SNR and Performance Optimization 2020/11/11
應用說明 Powering Sensitive Noise ADC Designs with the TPS62913 Low-Noise Buck Converter PDF | HTML 2020/9/30
技術文章 Step-by-step considerations for designing wide-bandwidth multichannel systems PDF | HTML 2019/6/4
技術文章 Preparing for 5G applications: sync your multichannel JESD204B data acquisition sy PDF | HTML 2017/8/28
技術文章 How to implement FM modulation PDF | HTML 2017/8/3
技術文章 High-speed data converter clocking for JESD204B PDF | HTML 2017/7/7

設計與開發

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開發板

ADC08DJ5200RFEVM — 具有雙路 5.2 GSPS 或單路 GSPS-10.4 且適用於射頻取樣 8 位元 ADC 的 ADC08DJ5200RF 評估模組

ADC08DJ5200RF 評估模組 (EVM) 是用於評估 ADC08DJ5200RF 的平台。ADC08DJ5200RF 是一款低功耗、8 位元、雙通道 5.2-GSPS 或單通道 10.4-GSPS 的射頻取樣類比轉數位轉換器 (ADC),具有緩衝類比輸入、整合式數位降壓轉換器與 JESD204B/C 介面。此 EVM 具有變壓器耦合類比輸入,可適應廣泛的訊號來源和頻率。

ADC08DJ5200RFEVM 隨附 LMX2594 時脈合成器和 LMK04828 JESD204B/C 時脈產生器,可配置成提供適何完整 JESD204B/C 子類別 1 時脈解決方案的超低抖動 ADC (...)

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ADC12DJ4000RFEVM — 適用於 4GSPS 雙通道或 8GSPS 單通道、射頻取樣、12 位元 ADC 的 ADC12DJ4000RF 評估模組

ADC12DJ4000RF 評估模組 (EVM) 專為評估 ADC12DJ4000RF 高速類比轉數位轉換器 (ADC) 所設計。本 EVM 搭載 ADC12DJ4000RF 晶片,該晶片為具備 JESD204B 介面的 12 位元、雙通道 4GSPS 或單通道 8GSPS ADC。
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LMX2594EVM — 具有相位同步功能且符合 JESD204B 標準的 LMX2594EVM 15 GHz 寬頻射頻合成器評估模組

LMX2594EVM 評估模組 (EVM) 是用於開發 LMX2594 的平台。LMX2594 是業界首款內建電壓控制振盪器 (VCO) 的 PLL,其基頻 VCO 輸出可達 15GHz。領先業界的 PLL 品質因數 (FOM) 為 –236dBc/Hz 和 1/f 的 –129dBc/Hz。此裝置支援 JESD204B 標準(可產生或重複 SYSREF 訊號),因此最適合時鐘高速資料轉換器。EVM 測量的整合式抖動在 9-GHz 載波頻率下低於 50 fs。透過提供 SYNC 訊號,使用者可在多個 LMX2594 裝置中同步輸出相位。LMX2594 (...)

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LMX2594PSEVM — 適用於 15-GHz 射頻合成器及多裝置相位同步的 LMX2594 評估模組

LMX2594 評估模組 (EVM) 是用於評估 LMX2594 寬頻 RF 合成器的相位同步 (PS) 功能的平台。LMX2594PSEVM 包含兩個共用相同參考時鐘的 LMX2594 零件。

在相位同步後可測量並比較零件輸出的相位。EVM 還包含射頻 (RF) 功率合成器,可用於將兩個相位同步的輸出結合到單一輸出,同時降低相位雜訊。

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XMICR-3P-LMX2594 — LMX2594 X-MWblock 評估模組

X-MWblocks consist of RF and Microwave “Drop-In” components that can be used individually for prototyping or in production assemblies. X-MWblocks are easy to test, integrate, align, and configure to 60 GHz and beyond. No messy Sweat Soldering or Silver Epoxy processes are required. X-MWblocks are (...)

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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

德州儀器 (TI) 的時鐘及合成器 (TICS) 專業級軟體用於編程具有以下前置字元的產品編號的評估模組 (EVM):CDC、LMK 和 LMX。這些產品包括鎖相迴路及電壓控制振盪器 (PLL+VCO)、合成器和時鐘裝置。

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模擬型號

LMX2594 IBIS Model

SNAM206.ZIP (44 KB) - IBIS 模型
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設計工具

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

時鐘樹架構是一款時鐘樹合成工具,可根據您的系統需求產生時鐘樹解決方案,進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料,產生系統級多晶片計時解決方案。

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PLLATINUMSIM-SW — PLL 迴路濾波器、相位雜訊、鎖定時間與雜散模擬工具

PLLATINUMSIM-SW 為一模擬工具,可讓使用者建立 PLLatinum™ 積體電路的詳細設計和模擬,包括 LMX 系列的相位鎖定迴路 (PLL) 及合成器。

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許多 TI 參考設計包含 LMX2594

使用我們的參考設計選擇工具,以檢視並找出最適合您的應用和參數的設計。

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VQFN (RHA) 40 Ultra Librarian

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