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LMK5B12212

現行

具有整合式 2.5GHz BAW VCO 的超低抖動、12 輸出、一 DPLL、二 APLL 網路同步器

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產品規格表

LMK5B12212

現行
產品規格表 立即訂購

產品詳細資料

Function Clock network synchronizer Number of outputs 12 Output type CML, LVCMOS, LVDS, LVPECL RMS jitter (fs) 47 Features JESD204B Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 1250 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Operating temperature range (°C) -40 to 85 Number of input channels 2
Function Clock network synchronizer Number of outputs 12 Output type CML, LVCMOS, LVDS, LVPECL RMS jitter (fs) 47 Features JESD204B Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 1250 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Operating temperature range (°C) -40 to 85 Number of input channels 2
VQFN (RGC) 64 81 mm² (9 mm × 9 mm)
  • Ultra-low jitter BAW VCO based Ethernet clocks
    • 13fs typical RMS jitter at 625MHz with 4MHz 1st order high-pass filter (HPF)
    • 24fs typical RMS jitter at 312.5MHz with 4MHz 1st order HPF
    • 42fs typical/ 60fs maximum RMS jitter at 312.5MHz
    • 47fs typical/ 65fs maximum RMS jitter at 156.25MHz

  • 1 high-performance Digital Phase Locked Loop (DPLL) with 2 Analog Phase Locked Loops (APLLs)

    • Programmable DPLL loop filter bandwidth from 1mHz to 4kHz
    • < 1ppt DCO frequency adjustment step size
  • 2 differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital Holdover and Hitless Switching
  • 12 differential outputs with programmable HSDS, AC-LVPECL, LVDS and HSCL formats
    • Up to 16 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT0_P/N, OUT1_P/N, GPIO1 and GPIO2 and 10 differential outputs on OUT2_P/N to OUT11_P/N
    • 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 6 compliant
  • I2C or 3-wire/4-wire SPI
  • Ultra-low jitter BAW VCO based Ethernet clocks
    • 13fs typical RMS jitter at 625MHz with 4MHz 1st order high-pass filter (HPF)
    • 24fs typical RMS jitter at 312.5MHz with 4MHz 1st order HPF
    • 42fs typical/ 60fs maximum RMS jitter at 312.5MHz
    • 47fs typical/ 65fs maximum RMS jitter at 156.25MHz

  • 1 high-performance Digital Phase Locked Loop (DPLL) with 2 Analog Phase Locked Loops (APLLs)

    • Programmable DPLL loop filter bandwidth from 1mHz to 4kHz
    • < 1ppt DCO frequency adjustment step size
  • 2 differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital Holdover and Hitless Switching
  • 12 differential outputs with programmable HSDS, AC-LVPECL, LVDS and HSCL formats
    • Up to 16 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT0_P/N, OUT1_P/N, GPIO1 and GPIO2 and 10 differential outputs on OUT2_P/N to OUT11_P/N
    • 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 6 compliant
  • I2C or 3-wire/4-wire SPI

The LMK5B12212 is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of ethernet-based networking applications with < 5ns timing accuracy (class D).

The network synchronizer integrates a DPLL to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and no external loop filters, maximizing flexibility and ease of use. The DPLL phase locks an integrated APLL to the provided reference input.

APLL1 features an ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology (known as the BAW APLL) and can generate 312.5MHz output clocks with 42fs typical / 60fs maximum RMS jitter irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 provides for a second frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference clocks and performs a hitless switch between inputs upon detecting a switchover event. Zero-Delay Mode (ZDM) and phase cancellation can be enabled to control the phase relationship from input to outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.

The LMK5B12212 is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of ethernet-based networking applications with < 5ns timing accuracy (class D).

The network synchronizer integrates a DPLL to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and no external loop filters, maximizing flexibility and ease of use. The DPLL phase locks an integrated APLL to the provided reference input.

APLL1 features an ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology (known as the BAW APLL) and can generate 312.5MHz output clocks with 42fs typical / 60fs maximum RMS jitter irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 provides for a second frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference clocks and performs a hitless switch between inputs upon detecting a switchover event. Zero-Delay Mode (ZDM) and phase cancellation can be enabled to control the phase relationship from input to outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 LMK5B12212 1-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With BAW VCO for Ethernet-Based Networking Applications datasheet PDF | HTML 2024/11/21
應用說明 Termination Guidelines for Differential and Single-Ended Signals PDF | HTML 2025/12/10
使用指南 LMK5B12212 Programmer's Guide (Rev. A) PDF | HTML 2025/11/17
應用說明 Oscillator Power Considerations for PLL Devices PDF | HTML 2025/10/30
證書 LMK5B12212EVM EU Declaration of Conformity (DoC) PDF | HTML 2023/9/29

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開發板

LMK5B12212EVM — LMK5B12212 評估模組

LMK5B12212 評估模組 (EVM) 適用於開發 LMK5B12212 網路時鐘產生器和同步器。EVM 可用於裝置評估、合規測試和系統原型設計。  LMK5B12212 整合了三個類比 PLL (APLL)、三個數位 PLL (DPLL) 與可編程迴路頻寬。EVM 包括 SMA 連接器，用於時鐘輸入、振盪器輸入和時鐘輸出，以便與 50Ω 測試設備介接。板載 TCXO 可用來對 LMK5B12212 操作時的自由運轉、鎖定或維持模式進行評估。EVM 可透過板載 USB 微控制器 (MCU) 介面，使用配備 TICS Pro 軟體圖形使用者介面 (GUI) 的 PC 進行配置。TICS (...)

使用指南: PDF | HTML
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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

德州儀器 (TI) 的時鐘及合成器 (TICS) 專業級軟體用於編程具有以下前置字元的產品編號的評估模組 (EVM)：CDC、LMK 和 LMX。這些產品包括鎖相迴路及電壓控制振盪器 (PLL+VCO)、合成器和時鐘裝置。

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模擬型號

LMK5B33216 Family IBIS model

SNAM295.ZIP (239 KB) - IBIS 模型
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設計工具

CLOCK-PERFDATA-DESIGN — Clock performance data and register settings for clock generators, network synchronizers, jitter cleaners, and other clocking devices.

Configuration, raw phase noise data, noise plots, and register data for common use cases on clock generators, network synchronizers, jitter cleaners, and other clocking devices
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