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LMK04816

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產品規格表

LMK04816

現行
產品規格表 立即訂購

產品詳細資料

Number of input channels 3 Number of outputs 12 RMS jitter (fs) 100 Features 0 Delay Output frequency (min) (MHz) 0.22 Output frequency (max) (MHz) 2600 Output type LVCMOS, LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.15 Supply voltage (max) (V) 3.45 Operating temperature range (°C) -40 to 85
Number of input channels 3 Number of outputs 12 RMS jitter (fs) 100 Features 0 Delay Output frequency (min) (MHz) 0.22 Output frequency (max) (MHz) 2600 Output type LVCMOS, LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.15 Supply voltage (max) (V) 3.45 Operating temperature range (°C) -40 to 85
WQFN (NKD) 64 81 mm² 9 x 9
  • Ultralow RMS Jitter Performance
    • 100-fs RMS Jitter (12 kHz to 20 MHz)
    • 123-fs RMS Jitter (100 Hz to 20 MHz)
  • Dual-Loop PLLATINUM™ PLL Architecture
    • PLL1
      • Integrated Low-Noise Crystal Oscillator
        Circuit
      • Holdover Mode When Input Clocks are Lost
        • Automatic or Manual Triggering and
          Recovery
    • PLL2
      • Normalized 1-Hz PLL Noise Floor of
        –227 dBc/Hz
      • Phase Detector Rate Up to 155 MHz
      • OSCin Frequency-Doubler
      • Integrated Low-Noise VCO
      • VCO Frequency Ranges From 2370 MHz
        to 2600 MHz
  • Three Redundant Input Clocks With LOS
    • Automatic and Manual Switch-Over Modes
  • 50% Duty Cycle Output Divides, 1 to 1045 (Even
    and Odd)
  • LVPECL, LVDS, or LVCMOS Programmable
    Outputs
  • Precision Digital Delay, Fixed or Dynamically-
    Adjustable
  • 25-ps Step Analog Delay Control, Up to 575 ps
  • 1/2 Clock Distribution Period Step Digital Delay,
    up to 522 Steps
  • 13 Differential Outputs; up to 26 Single-Ended
    • Up to 5 VCXO and Crystal-Buffered Outputs
  • Clock Rates of Up to 2600 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-Mode: Dual PLL, Single PLL, and Clock
    Distribution
  • Industrial Temperature Range: –40°C to +85°C
  • 3.15-V to 3.45-V Operation
  • Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)
  • Ultralow RMS Jitter Performance
    • 100-fs RMS Jitter (12 kHz to 20 MHz)
    • 123-fs RMS Jitter (100 Hz to 20 MHz)
  • Dual-Loop PLLATINUM™ PLL Architecture
    • PLL1
      • Integrated Low-Noise Crystal Oscillator
        Circuit
      • Holdover Mode When Input Clocks are Lost
        • Automatic or Manual Triggering and
          Recovery
    • PLL2
      • Normalized 1-Hz PLL Noise Floor of
        –227 dBc/Hz
      • Phase Detector Rate Up to 155 MHz
      • OSCin Frequency-Doubler
      • Integrated Low-Noise VCO
      • VCO Frequency Ranges From 2370 MHz
        to 2600 MHz
  • Three Redundant Input Clocks With LOS
    • Automatic and Manual Switch-Over Modes
  • 50% Duty Cycle Output Divides, 1 to 1045 (Even
    and Odd)
  • LVPECL, LVDS, or LVCMOS Programmable
    Outputs
  • Precision Digital Delay, Fixed or Dynamically-
    Adjustable
  • 25-ps Step Analog Delay Control, Up to 575 ps
  • 1/2 Clock Distribution Period Step Digital Delay,
    up to 522 Steps
  • 13 Differential Outputs; up to 26 Single-Ended
    • Up to 5 VCXO and Crystal-Buffered Outputs
  • Clock Rates of Up to 2600 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-Mode: Dual PLL, Single PLL, and Clock
    Distribution
  • Industrial Temperature Range: –40°C to +85°C
  • 3.15-V to 3.45-V Operation
  • Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)

The LMK04816 device is the industry’s highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual-loop PLLATINUM architecture enables 111-fs RMS jitter (12 kHz to 20 MHz) using a low-noise VCXO module or sub-200-fs RMS jitter (12 kHz to 20 MHz) using a low-cost external crystal and varactor diode.

The dual-loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.

The LMK04816 device is the industry’s highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual-loop PLLATINUM architecture enables 111-fs RMS jitter (12 kHz to 20 MHz) using a low-noise VCXO module or sub-200-fs RMS jitter (12 kHz to 20 MHz) using a low-cost external crystal and varactor diode.

The dual-loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
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重要文件 類型 標題 格式選項 日期
* Data sheet LMK04816 Three Input Low-Noise Clock Jitter Cleaner With Dual Loop PLLs datasheet (Rev. C) PDF | HTML 2016年 1月 14日
Application note AN-1939 Crystal Based Oscillator Design with the LMK04000 Family (Rev. A) 2013年 4月 26日
User guide LMK04816 Low-Noise Clock Jitter Cleaner with Dual Loop PLLs 2012年 7月 2日
User guide TSW3085EVM ACPR and EVM Measurements (TIDA-00076 Reference Guide) 2011年 12月 29日
Design guide Clock Conditioner Owner's Manual 2006年 11月 10日

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LMK04816BEVAL — 具有雙路串接 PLL 和整合 2.5 GHz VC 的三路輸入、十三路輸出時鐘抖動清除器

The LMK04816 is the industry's highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum™ architecture enables 111 fs rms jitter (12 kHz to 20 MHz) using a low (...)

使用指南: PDF
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軟體程式設計工具

CODELOADER — CodeLoader Device Register Programming v4.19.0

The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.

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CLOCKDESIGNTOOL — Clock Design Tool Software

The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)

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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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LMK04816 IBIS Model (Rev. C)

SNAM103C.ZIP (120 KB) - IBIS Model
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PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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