首頁 時鐘與計時 時鐘緩衝器
首頁
時鐘與計時
時鐘緩衝器

CDCLVP111

現行

具可選輸入的 1:10 LVPECL 緩衝器

立即訂購
產品規格表

CDCLVP111

現行
產品規格表 立即訂購

產品詳細資料

Number of outputs 10 Additive RMS jitter (typ) (fs) 40 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 30 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type CML, LVDS, LVPECL, SSTL
Number of outputs 10 Additive RMS jitter (typ) (fs) 40 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 30 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type CML, LVDS, LVPECL, SSTL
LQFP (VF) 32 81 mm² 9 x 9 VQFN (RHB) 32 25 mm² 5 x 5
  • Distributes One Differential Clock Input Pair
    LVPECL to 10 Differential LVPECL
  • Fully Compatible With LVECL and LVPECL
  • Supports a Wide Supply Voltage Range from
    2.375 V to 3.8 V
  • Selectable Clock Input Through CLK_SEL
  • Low-Output Skew (Typical 15 ps) for Clock-
    Distribution Applications
    • Additive Jitter Less Than 1 ps
    • Propagation Delay Less Than 350 ps
    • Open Input Default State
    • LVDS, CML, SSTL Input Compatible
  • VBB Reference Voltage Output for Single-Ended
    Clocking
  • Available in a 32-Pin LQFP and QFN Package
  • Frequency Range From DC to 3.5 GHz
  • Pin-to-Pin Compatible With MC100 Series EP111,
    ES6111, LVEP111, PTN1111
  • APPLICATIONS
    • Designed for Driving 50-Ω Transmission Lines
    • High Performance Clock Distribution

All other trademarks are the property of their respective owners
  • Distributes One Differential Clock Input Pair
    LVPECL to 10 Differential LVPECL
  • Fully Compatible With LVECL and LVPECL
  • Supports a Wide Supply Voltage Range from
    2.375 V to 3.8 V
  • Selectable Clock Input Through CLK_SEL
  • Low-Output Skew (Typical 15 ps) for Clock-
    Distribution Applications
    • Additive Jitter Less Than 1 ps
    • Propagation Delay Less Than 350 ps
    • Open Input Default State
    • LVDS, CML, SSTL Input Compatible
  • VBB Reference Voltage Output for Single-Ended
    Clocking
  • Available in a 32-Pin LQFP and QFN Package
  • Frequency Range From DC to 3.5 GHz
  • Pin-to-Pin Compatible With MC100 Series EP111,
    ES6111, LVEP111, PTN1111
  • APPLICATIONS
    • Designed for Driving 50-Ω Transmission Lines
    • High Performance Clock Distribution

All other trademarks are the property of their respective owners

The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.

The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLK0 and bypassed to GND through a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP111 device is characterized for operation from –40°C to 85°C.

The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.

The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLK0 and bypassed to GND through a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP111 device is characterized for operation from –40°C to 85°C.
filter 尋找其它 時鐘緩衝器
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 1
重要文件 類型 標題 格式選項 日期
* Data sheet CDCLVP111 Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver datasheet (Rev. F) PDF | HTML 2015年 6月 30日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

CDCLVP111 IBIS Model Version 2.0 (Rev. B)

SLLM052B.ZIP (35 KB) - IBIS Model
下載
設計工具

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。
立即進行設計
設計工具

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

支援產品和硬體

支援產品和硬體
下載選項
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
要求
封裝 針腳 CAD 符號、佔位空間與 3D 模型
LQFP (VF) 32 Ultra Librarian
VQFN (RHB) 32 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片