CDCDB803
- 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
- 8 hardware output enable (OE#) controls
- Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)
- Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)
- Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)
- Supports Common Clock (CC) and Individual Reference (IR) architectures
- Spread spectrum-compatible
- Output-to-output skew: < 50 ps
- Input-to-output delay: < 3 ns
-
Fail-safe input
-
Programmable output slew rate control
- 9 selectable SMBus addresses
- 3.3-V core and IO supply voltages
- Hardware-controlled low power mode (PD#)
- Current consumption: 72 mA maximum
- 6-mm × 6-mm, 48-pin VQFN package
The CDCDB803 is a 8-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight output enable pins allow the configuration and control of all eight outputs individually. The CDCDB803 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. It also meets or exceeds the parameters in the DB2000Q specification. The CDCDB803 is packaged in a 6-mm × 6-mm, 48-pin VQFN package.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6 datasheet (Rev. A) | PDF | HTML | 2022/5/23 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RSL) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。