CDCLVP110
- Distributes One Differential Clock Input Pair
LVPECL/HSTL to 10 Differential LVPECL Clock Outputs - Fully Compatible With LVECL/LVPECL/HSTL
- Single Supply Voltage Required, ±3.3-V or ±2.5-V Supply
- Selectable Clock Input Through CLK_SEL
- Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
- VBB Reference Voltage Output for Single-Ended Clocking
- Available in a 32-Pin LQFP Package
- Frequency Range From DC to 3.5 GHz
- Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111
The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines.
The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
The CDCLVP110 is characterized for operation from –40°C to 85°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver datasheet (Rev. D) | 2011/1/11 | |||
| 應用說明 | Clocking Design Guidelines: Unused Pins | 2015/11/19 | ||||
| 應用說明 | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007/10/17 | ||||
| 應用說明 | Advantage of Using TI's Lowest Jitter Differential Clock Buffer | 2003/8/20 | ||||
| 應用說明 | DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML | 2003/2/19 | ||||
| 應用說明 | PCB Layout Guidelines for CDCLVP110 | 2002/6/12 |
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|---|---|---|
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