LMK05028

現行

低抖動雙通道網路同步器時脈

立即訂購

產品規格表

document-pdfAcrobat LMK05028 Low-Jitter Dual-Channel Network Synchronizer Clock With EEPROM datasheet (Rev. B) (英文) PDF | HTML

LMK05028

現行

產品規格表

立即訂購

產品詳細資料

Function

Clock network synchronizer

Number of outputs

8

Output type

CML, HCSL, LVCMOS, LVDS, LVPECL

RMS jitter (fs)

150

Features

I2C, Integrated EEPROM, Pin programmable, SPI

Output frequency (min) (MHz)

0.000000000001

Output frequency (max) (MHz)

750

Input type

LVCMOS, LVDS, LVPECL, XTAL

Operating temperature range (°C)

-40 to 85

Number of input channels

4

Function

Clock network synchronizer

Number of outputs

8

Output type

CML, HCSL, LVCMOS, LVDS, LVPECL

RMS jitter (fs)

150

Features

I2C, Integrated EEPROM, Pin programmable, SPI

Output frequency (min) (MHz)

0.000000000001

Output frequency (max) (MHz)

750

Input type

LVCMOS, LVDS, LVPECL, XTAL

Operating temperature range (°C)

-40 to 85

Number of input channels

4

VQFN (RGC)

64

81 mm² (9 mm × 9 mm)

Two Independent PLL Channels Featuring:
- Jitter: 150fs RMS for Outputs ≥ 100MHz
- Phase Noise: –112dBc/Hz at 100Hz Offset for 122.88MHz
- Hitless Switching: 50ps Phase Transient With Phase Cancellation
- Programmable Loop Bandwidth With Fastlock
- Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
- Any Input to Any Output Frequency Translation
Four Reference Clock Inputs
- Priority-Based Input Selection
- Digital Holdover on Loss of Reference
Eight Clock Outputs With Programmable Drivers
- Up to Six Different Output Frequencies
- AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8V or 2.5V LVCMOS Output Formats
EEPROM/ROM for Custom Clocks on Power-Up
Flexible Configuration Options
- Up to 750MHz on Input and Output
- XO: 10MHz to 100MHz, TCXO: 10MHz to 54MHz
- DCO Mode: < 1ppt/Step for Fine Frequency and Phase Steering (IEEE 1588 Slave)
- Zero Delay for Deterministic Phase Offset
- Robust Clock Monitoring and Status
- I2C or SPI Interface
Excellent Power Supply Noise Rejection (PSNR)
3.3V Supply With 1.8V, 2.5V, or 3.3V Outputs
Industrial Temperature Range: –40°C to +85°C

Two Independent PLL Channels Featuring:
- Jitter: 150fs RMS for Outputs ≥ 100MHz
- Phase Noise: –112dBc/Hz at 100Hz Offset for 122.88MHz
- Hitless Switching: 50ps Phase Transient With Phase Cancellation
- Programmable Loop Bandwidth With Fastlock
- Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
- Any Input to Any Output Frequency Translation
Four Reference Clock Inputs
- Priority-Based Input Selection
- Digital Holdover on Loss of Reference
Eight Clock Outputs With Programmable Drivers
- Up to Six Different Output Frequencies
- AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8V or 2.5V LVCMOS Output Formats
EEPROM/ROM for Custom Clocks on Power-Up
Flexible Configuration Options
- Up to 750MHz on Input and Output
- XO: 10MHz to 100MHz, TCXO: 10MHz to 54MHz
- DCO Mode: < 1ppt/Step for Fine Frequency and Phase Steering (IEEE 1588 Slave)
- Zero Delay for Deterministic Phase Offset
- Robust Clock Monitoring and Status
- I2C or SPI Interface
Excellent Power Supply Noise Rejection (PSNR)
3.3V Supply With 1.8V, 2.5V, or 3.3V Outputs
Industrial Temperature Range: –40°C to +85°C

The LMK05028 is a high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and good hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The low jitter and high PSNR of the device reduce bit error rates (BER) in high-speed serial links.

The device has two PLL channels and generates up to eight output clocks with 150-fs RMS jitter. Each PLL domain can select from any four reference inputs to synchronize the outputs.

The LMK05028 is a high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and good hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The low jitter and high PSNR of the device reduce bit error rates (BER) in high-speed serial links.

The device has two PLL channels and generates up to eight output clocks with 150-fs RMS jitter. Each PLL domain can select from any four reference inputs to synchronize the outputs.

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重要文件	類型	標題	格式選項	日期
*	資料表	LMK05028 Low-Jitter Dual-Channel Network Synchronizer Clock With EEPROM datasheet (Rev. B)	PDF \| HTML	2025/2/14
	Third party document	Intel® Stratix® 10 SX SoC Development Kit User Guide		2019/4/12
	技術文章	How to achieve network synchronization clocks with TI digital PLLs	PDF \| HTML	2018/6/21
	應用說明	TI Network Synchronizer Clock Value Adds in Communications and Industrial Applic		2018/4/12
	使用指南	LMK05028 Registers		2018/4/10
	應用說明	ITU-T G.8262 Compliance Test Results for the LMK05028 Digital PLL Network		2018/4/10

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開發板

LMK05028EVM — LMK05028 網路時鐘產生器和同步器評估模組

LMK05028EVM 是適用於 LMK05028 網路時鐘產生器和同步器的評估模組。EVM 可用於裝置評估、合規測試和系統原型設計。
LMK05028 整合了兩個數位 PLL (DPLL) 與可編程頻寬，可用於輸入漂移和抖動衰減。EVM 包括 SMA 連接器，用於時鐘輸入、振盪器輸入和時鐘輸出，以便與 50-Ω 測試設備介接。板載 XO 和 TCXO 選項可用來對 LMK05028 操作時的自由運轉、鎖定或維持模式進行評估。EVM 可透過板載 USB 微控制器 (MCU) 介面，使用配備 TI TICS Pro 軟體圖形使用者介面 (GUI) 的 PC 進行配置。TiCS Pro 可用於將 (...)

使用指南: PDF | HTML

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