產品詳細資料

Frequency (max) (MHz) 28000 Frequency (min) (MHz) 5 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129 Features Phase synchronization, Programmable output power, SYSREF support (Compliant to JESD204B standard), Space grade Current consumption (mA) 360 Integrated VCO Yes Operating temperature range (°C) 25 to 25 Rating Space Lock time (µs) (typ) (s) Loop BW dependent
Frequency (max) (MHz) 28000 Frequency (min) (MHz) 5 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129 Features Phase synchronization, Programmable output power, SYSREF support (Compliant to JESD204B standard), Space grade Current consumption (mA) 360 Integrated VCO Yes Operating temperature range (°C) 25 to 25 Rating Space Lock time (µs) (typ) (s) Loop BW dependent
HTQFP (PAP) 64 144 mm² (12 mm × 12 mm)
  • SMD 5962R2321001PXE
    • Total ionizing dose 100Krad (ELDRS-free)
    • Single event latch-up (SEL) immune up to 75MeV-cm2/mg
    • Single event functional interrupt (SEFI) immune up to 75MeV-cm2/mg
  • Wide band frequency synthesizer : 5MHz to 30GHz output frequency
  • –102dBc/Hz phase noise at 100kHz offset with 30GHz carrier
  • 62fs RMS jitter at 30GHz (1kHz to 100MHz)
  • Programmable output power
  • PLL key specifications:
    • Figure of merit: –236dBc/Hz
    • Normalized 1/f noise: –129dBc/Hz
    • Up to 200MHz phase detector frequency in fractional mode.
  • Synchronization of output phase across multiple devices
  • Independent mute pins for RFoutA and RFoutB outputs
  • Support for SYSREF with programmable delay
  • 3.3V single power supply operation
  • Pin-mode: Pin configurable N divider and output divider in Integer PLL mode
  • 10 × 10mm² 64 lead QFP package
  • Operating temperature range: –55°C to +125°C
  • Supported by PLLatinum™ Simulator design tool
  • SMD 5962R2321001PXE
    • Total ionizing dose 100Krad (ELDRS-free)
    • Single event latch-up (SEL) immune up to 75MeV-cm2/mg
    • Single event functional interrupt (SEFI) immune up to 75MeV-cm2/mg
  • Wide band frequency synthesizer : 5MHz to 30GHz output frequency
  • –102dBc/Hz phase noise at 100kHz offset with 30GHz carrier
  • 62fs RMS jitter at 30GHz (1kHz to 100MHz)
  • Programmable output power
  • PLL key specifications:
    • Figure of merit: –236dBc/Hz
    • Normalized 1/f noise: –129dBc/Hz
    • Up to 200MHz phase detector frequency in fractional mode.
  • Synchronization of output phase across multiple devices
  • Independent mute pins for RFoutA and RFoutB outputs
  • Support for SYSREF with programmable delay
  • 3.3V single power supply operation
  • Pin-mode: Pin configurable N divider and output divider in Integer PLL mode
  • 10 × 10mm² 64 lead QFP package
  • Operating temperature range: –55°C to +125°C
  • Supported by PLLatinum™ Simulator design tool

The LMX2624-SP is a high performance wideband phase-locked loop (PLL) with integrated voltage controlled oscillator (VCO) that can output any frequency from 5MHz and 30GHz. The VCO on this device covers an entire octave so the frequency coverage is complete down to 5MHz. The high performance PLL with a figure of merit of –236dBc/Hz and high phase detector frequency can attain very low in-band noise and integrated jitter.

The LMX2624-SP allows users to synchronize the output of multiple instances of the device. This means that deterministic phase can be obtained from a device in use cases including the one with fractional engine or output divider enabled. The device also adds support for either generating or repeating SYSREF (compliant to JESD204B/C standard), making the device designed for low-noise clock source for high-speed data converters.

This device is fabricated in Texas Instruments’ advanced BiCMOS process and is available in a 64-lead QFP plastic package.

The LMX2624-SP is a high performance wideband phase-locked loop (PLL) with integrated voltage controlled oscillator (VCO) that can output any frequency from 5MHz and 30GHz. The VCO on this device covers an entire octave so the frequency coverage is complete down to 5MHz. The high performance PLL with a figure of merit of –236dBc/Hz and high phase detector frequency can attain very low in-band noise and integrated jitter.

The LMX2624-SP allows users to synchronize the output of multiple instances of the device. This means that deterministic phase can be obtained from a device in use cases including the one with fractional engine or output divider enabled. The device also adds support for either generating or repeating SYSREF (compliant to JESD204B/C standard), making the device designed for low-noise clock source for high-speed data converters.

This device is fabricated in Texas Instruments’ advanced BiCMOS process and is available in a 64-lead QFP plastic package.

下載 觀看有字幕稿的影片 影片

您可能會感興趣的類似產品

open-in-new 比較替代產品
功能相似於所比較的產品。
LMK04832-SP 現行 Radiation-hardened, QML-V, ultra-low-noise, 3.2GHz, 15-output clock jitter cleaner Jitter cleaner to provide clock to the synthesizer.
LMX1906-SP 現行 Radiation-hardened, QML-P, 15GHz buffer, multiplier and divider with SYSREF and FPGA clock RF buffer to fan out the clock from the synthesizer.
LMX2615-SP 現行 Radiation-hardened, QML-V, 40MHz to 15GHz synthesizer with synchronization and JESD204B support New variant with 28GHz max output frequency.

技術文件

找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 4
重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 LMX2624-SP 5MHz to 30GHz Wideband Synthesizer With Phase Synchronization and JESD204B/C Support datasheet (Rev. A) PDF | HTML 2026/7/20
選擇指南 TI Space Products (Rev. L) 2026/3/27
Application brief Allan Deviation Measurement Data from LMX2615 2025/6/26
Application brief Full Assist Feature in LMX2624 2025/5/27

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

支援軟體

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

德州儀器 (TI) 的時鐘及合成器 (TICS) 專業級軟體用於編程具有以下前置字元的產品編號的評估模組 (EVM):CDC、LMK 和 LMX。這些產品包括鎖相迴路及電壓控制振盪器 (PLL+VCO)、合成器和時鐘裝置。

支援產品和硬體
設計工具

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

時鐘樹架構是一款時鐘樹合成工具,可根據您的系統需求產生時鐘樹解決方案,進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料,產生系統級多晶片計時解決方案。

支援產品和硬體
設計工具

PLLATINUMSIM-SW — PLL 迴路濾波器、相位雜訊、鎖定時間與雜散模擬工具

PLLATINUMSIM-SW 為一模擬工具,可讓使用者建立 PLLatinum™ 積體電路的詳細設計和模擬,包括 LMX 系列的相位鎖定迴路 (PLL) 及合成器。

支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
HTQFP (PAP) 64 Ultra Librarian

訂購與品質

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片