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時鐘緩衝器

LMK1D2108

現行

雙組 8 通道輸出 1.8-V、2.5-V 和 3.3-V LVDS 緩衝器

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產品規格表

LMK1D2108

現行
產品規格表 立即訂購

產品詳細資料

Number of outputs 16 Additive RMS jitter (typ) (fs) 45 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
Number of outputs 16 Additive RMS jitter (typ) (fs) 45 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
VQFN (RGZ) 48 49 mm² 7 x 7
  • High-performance LVDS clock buffer family: up to 2 GHz
    • Dual 1:6 differential buffer
    • Dual 1:8 differential buffer
  • Supply voltage: 1.71 V to 3.465 V
  • Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
    • Very low phase noise floor: -164 dBc/Hz (typical)
  • Very low propagation delay: < 575 ps maximum
  • Output skew: 20 ps maximum
  • High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
  • Bank enable/disable using the EN pin
  • Fail-safe input operation
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
  • LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packaged in

    • LMK1D2106: 6-mm × 6-mm, 40-pin VQFN (RHA)

    • LMK1D2108: 7-mm × 7-mm, 48-pin VQFN (RGZ)
  • High-performance LVDS clock buffer family: up to 2 GHz
    • Dual 1:6 differential buffer
    • Dual 1:8 differential buffer
  • Supply voltage: 1.71 V to 3.465 V
  • Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
    • Very low phase noise floor: -164 dBc/Hz (typical)
  • Very low propagation delay: < 575 ps maximum
  • Output skew: 20 ps maximum
  • High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
  • Bank enable/disable using the EN pin
  • Fail-safe input operation
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
  • LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packaged in

    • LMK1D2106: 6-mm × 6-mm, 40-pin VQFN (RHA)

    • LMK1D2108: 7-mm × 7-mm, 48-pin VQFN (RGZ)

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0 to OUT15) in the LMK1D2108 and 12 pairs of clock outputs (OUT0 to OUT11) in the LMK1D2106 with minimum skew for clock distribution. Each buffer block consists of one input and a maximum of 6 (LMK1D2106) or 8 (LMK1D2108) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6).

Using the control pin (EN), output banks can either be enable or disabled. If this pin is left open, both bank outputs are enabled. If the control pin is switched to a logic "0", both bank outputs are disabled (static logic "0"). If the control pin is switched to a logic "1", the outputs of one bank are disabled while the outputs of the other bank are enabled. The part also supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0 to OUT15) in the LMK1D2108 and 12 pairs of clock outputs (OUT0 to OUT11) in the LMK1D2106 with minimum skew for clock distribution. Each buffer block consists of one input and a maximum of 6 (LMK1D2106) or 8 (LMK1D2108) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6).

Using the control pin (EN), output banks can either be enable or disabled. If this pin is left open, both bank outputs are enabled. If the control pin is switched to a logic "0", both bank outputs are disabled (static logic "0"). If the control pin is switched to a logic "1", the outputs of one bank are disabled while the outputs of the other bank are enabled. The part also supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).
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* Data sheet LMK1D210x Low Additive Jitter LVDS Buffer datasheet (Rev. A) PDF | HTML 2022年 1月 28日

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