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射頻 (RF) 與微波
RF PLL 與合成器

LMX1860-SEP

現行

具有 SYSREF (支援 JESD204B/C) 和 FPGA 時脈的耐輻射 15GHz RF 緩衝器、倍頻器、分頻器

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產品規格表

LMX1860-SEP

現行
產品規格表 立即訂購

產品詳細資料

Frequency (max) (MHz) 12800 Frequency (min) (MHz) 300 Features Integrated multiplier and divider modes, JESD204B/C SYSREF support, Phase synchronization, RF clock distribution, Radiation hardened, Ultra-low additive jitter Current consumption (mA) 405 Integrated VCO No Operating temperature range (°C) -55 to 125 Rating Space Lock time (µs) (typ) (s) Loop BW dependent
Frequency (max) (MHz) 12800 Frequency (min) (MHz) 300 Features Integrated multiplier and divider modes, JESD204B/C SYSREF support, Phase synchronization, RF clock distribution, Radiation hardened, Ultra-low additive jitter Current consumption (mA) 405 Integrated VCO No Operating temperature range (°C) -55 to 125 Rating Space Lock time (µs) (typ) (s) Loop BW dependent
HTQFP (PAP) 64 144 mm² 12 x 12
  • VID #V62/24630
    • Total ionizing dose 30krad (ELDRS-free)
    • Single event latch-up (SEL) immune up to 43MeV - cm2 /mg
    • Single event functional interrupt (SEFI) immune up to 43MeV - cm2 /mg
  • Clock buffer for 300MHz to 15GHz frequency
  • Ultra-Low Noise
    • Noise floor of –159dBc/Hz at 6GHz output
    • 36-fs additive jitter (100Hz to fCLK) at 6GHz output
    • 5fs additive jitter (100Hz - 100MHz)
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divide by 1 (Buffer), 2, 3, 4, 5, and 7
    • Shared programmable multiplier x2, x3, and x4
  • Support pin mode options to configure the device without SPI
  • LOGICLK output with corresponding SYSREF output
    • On separate divide bank
    • 1, 2, 4 pre-divider
    • 1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5ps each at 12.8GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5V operating voltage
  • –55ºC to 125ºC operating temperature
  • High Reliability
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Extended Product Life Cycle
    • Product Traceability
  • VID #V62/24630
    • Total ionizing dose 30krad (ELDRS-free)
    • Single event latch-up (SEL) immune up to 43MeV - cm2 /mg
    • Single event functional interrupt (SEFI) immune up to 43MeV - cm2 /mg
  • Clock buffer for 300MHz to 15GHz frequency
  • Ultra-Low Noise
    • Noise floor of –159dBc/Hz at 6GHz output
    • 36-fs additive jitter (100Hz to fCLK) at 6GHz output
    • 5fs additive jitter (100Hz - 100MHz)
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divide by 1 (Buffer), 2, 3, 4, 5, and 7
    • Shared programmable multiplier x2, x3, and x4
  • Support pin mode options to configure the device without SPI
  • LOGICLK output with corresponding SYSREF output
    • On separate divide bank
    • 1, 2, 4 pre-divider
    • 1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5ps each at 12.8GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5V operating voltage
  • –55ºC to 125ºC operating temperature
  • High Reliability
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Extended Product Life Cycle
    • Product Traceability

The LMX1860-SEP is an buffer, divider and multiplier that features high frequency, ultra-low jitter, and SYSREF outputs. This device combined with an ultra-low noise reference clock source is an exemplary design for clocking data converters, especially when sampling above 3GHz. Each of the 4 high frequency clock outputs and additional LOGICLK output is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. This device can distribute the multichannel, low skew, ultra-low noise local oscillator signals to multiple mixers by disabling the SYSREF outputs.

The LMX1860-SEP is an buffer, divider and multiplier that features high frequency, ultra-low jitter, and SYSREF outputs. This device combined with an ultra-low noise reference clock source is an exemplary design for clocking data converters, especially when sampling above 3GHz. Each of the 4 high frequency clock outputs and additional LOGICLK output is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. This device can distribute the multichannel, low skew, ultra-low noise local oscillator signals to multiple mixers by disabling the SYSREF outputs.
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技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet LMX1860-SEP Space Grade Low-Noise, High-Frequency JESD204B/C Buffer, Multiplier and Divider datasheet (Rev. A) PDF | HTML 2025年 5月 20日
* Radiation & reliability report LMX1860-SEP Process Flow and Reliability Report (Rev. A) PDF | HTML 2024年 8月 5日
* Radiation & reliability report LMX1860-SEP Single-Event Effects Report PDF | HTML 2024年 4月 3日
* Radiation & reliability report LMX1860-SEP Total Ionizing Dose (TID) Radiation Report 2024年 4月 3日
Application note Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 2025年 4月 11日

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開發板

LMX1860SEPEVM — LMX1860-SEP 評估模組

LMX1860-SEP 評估模組 (EVM) 設計旨在評估 LMX1860-SEP 的性能，其為四路輸出、超低附加抖動無線電頻率 (RF) 緩衝器、分頻器和倍頻器。此 EVM 可緩衝最多 18GHz 的 RF 時鐘輸入，在 3.2GHz 至 6.4GHz 的輸出範圍內乘以二、三或四，並將輸入除以最多八。包括適用於現場可編程邏輯閘陣列 (FPGA) 和邏輯時鐘的獨立輔助時鐘分頻器。每個輸出均包含具有皮秒精度和延遲微調功能的系統參考 (SYSREF) 補數。多個裝置可針對廣泛的時鐘分配樹狀結構進行同步化。

使用指南: PDF | HTML
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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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