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CDCLVP111-SEP

現行

具可選輸入時脈驅動器的耐輻射 1:10 LVPECL 高速時脈緩衝器

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產品規格表

CDCLVP111-SEP

現行
產品規格表 立即訂購

產品詳細資料

Number of outputs 10 Additive RMS jitter (typ) (fs) 40 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 50 Operating temperature range (°C) -55 to 125 Rating Space Output type LVPECL Input type CML, LVDS, LVPECL, SSTL
Number of outputs 10 Additive RMS jitter (typ) (fs) 40 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 50 Operating temperature range (°C) -55 to 125 Rating Space Output type LVPECL Input type CML, LVDS, LVPECL, SSTL
HLQFP (VFP) 32 81 mm² 9 x 9
  • Vendor item drawing (VID#): V62/12624-02YE
  • Radiation tolerance:
    • Total ionizing dose (TID): 50krad
    • Single-event latch-up (SEL): 43MeV × cm2/mg
  • Junction temperature range: –55°C to 125°C
  • Distributes One Differential Clock Input Pair (LVDS, CML, SSTL, LVPECL, LVECL) to 10 Differential LVPECL or LVECL outputs
  • Supports a Wide Supply Voltage Range From 2.375V to 3.8V
  • Selectable Clock Input Through CLK_SEL
  • Low-Output Skew (Typical 15ps) for Clock-Distribution Applications
    • Additive Jitter Less Than 1ps
    • Propagation Delay Less Than 355ps
    • Open Input Default State
    • LVDS, CML, SSTL Input Compatible
  • VBB Reference Voltage Output for Single-Ended Clocking
  • Frequency Range From DC to 3.5GHz
  • Space-enhanced plastic (space EP):
    • SUPPORTS DEFENSE, AND AEROSPACE APPLICATIONS
    • Controlled baseline
    • One assembly and test Site
    • One fabrication site
    • Extended product life cycle
    • Product traceability
    • Outgassing test performed per ASTM E595
  • Vendor item drawing (VID#): V62/12624-02YE
  • Radiation tolerance:
    • Total ionizing dose (TID): 50krad
    • Single-event latch-up (SEL): 43MeV × cm2/mg
  • Junction temperature range: –55°C to 125°C
  • Distributes One Differential Clock Input Pair (LVDS, CML, SSTL, LVPECL, LVECL) to 10 Differential LVPECL or LVECL outputs
  • Supports a Wide Supply Voltage Range From 2.375V to 3.8V
  • Selectable Clock Input Through CLK_SEL
  • Low-Output Skew (Typical 15ps) for Clock-Distribution Applications
    • Additive Jitter Less Than 1ps
    • Propagation Delay Less Than 355ps
    • Open Input Default State
    • LVDS, CML, SSTL Input Compatible
  • VBB Reference Voltage Output for Single-Ended Clocking
  • Frequency Range From DC to 3.5GHz
  • Space-enhanced plastic (space EP):
    • SUPPORTS DEFENSE, AND AEROSPACE APPLICATIONS
    • Controlled baseline
    • One assembly and test Site
    • One fabrication site
    • Extended product life cycle
    • Product traceability
    • Outgassing test performed per ASTM E595

The CDCLVP111-SEP clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111-SEP can accept two clock sources into an input multiplexer. The CDCLVP111-SEP is specifically designed for driving 50Ω transmission lines. When an output pin is not used, leaving the pin open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50Ω.

The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin must be connected to CLK0 and bypassed to GND using a 10nF capacitor.

For high-speed performance, the differential mode is strongly recommended.

The CDCLVP111-SEP is characterized for operation from –55°C to 125°C.

The CDCLVP111-SEP clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111-SEP can accept two clock sources into an input multiplexer. The CDCLVP111-SEP is specifically designed for driving 50Ω transmission lines. When an output pin is not used, leaving the pin open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50Ω.

The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin must be connected to CLK0 and bypassed to GND using a 10nF capacitor.

For high-speed performance, the differential mode is strongly recommended.

The CDCLVP111-SEP is characterized for operation from –55°C to 125°C.
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重要文件 類型 標題 格式選項 日期
* Data sheet CDCLVP111-SEP Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver datasheet PDF | HTML 2025年 9月 18日
* Radiation & reliability report CDCLVP111-SEP Single-Event Effects (SEE) Radiation Report PDF | HTML 2025年 9月 24日
* Radiation & reliability report CDCLVP111-SEP Production Flow and Reliability Report 2025年 8月 22日
Certificate CDCLVP111SEPEVM EU Declaration of Conformity (DoC) 2025年 8月 22日
Selection guide TI Space Products (Rev. K) 2025年 4月 4日

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CDCLVP111SEPEVM — CDCLVP111-SEP 評估模組

CDCLVP111-SEP 評估模組 (EVM) 提供一個平台，用於在各種電壓和偏置配置下評估時鐘緩衝器。
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