產品詳細資料

Frequency (max) (MHz) 18000 Frequency (min) (MHz) 300 Features Multi-device sync, RF clock distribution, SYNC Pin, Ultra-low additive jitter Current consumption (mA) 500 Integrated VCO No Operating temperature range (°C) -40 to 85 Rating Catalog
Frequency (max) (MHz) 18000 Frequency (min) (MHz) 300 Features Multi-device sync, RF clock distribution, SYNC Pin, Ultra-low additive jitter Current consumption (mA) 500 Integrated VCO No Operating temperature range (°C) -40 to 85 Rating Catalog
VQFN (RHA) 40 36 mm² 6 x 6
  • Clock buffer for 300MHz to 18GHz frequency
  • Divider output frequency supported up to 8GHz
  • Ultra-Low Noise
    • Noise floor of –161dBc/Hz at 6GHz output
    • 36fs additive jitter (100Hz to fCLK) at 6GHz output
    • 5fs additive jitter (100Hz - 100MHz)
  • 4 high-frequency clocks output
    • with shared divider by 1 (Bypass), 2, 3, 4, 5, 6, 7, and 8
  • 1ps typical output to output skew
  • Support pin mode options for outputs enable and divider /2, /3 and /4 values set
  • AUXCLK output
    • On separate divide bank
    • 1, 2, 4 pre-divider
    • 1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • SYNC feature to all divides
  • 2.5V operating voltage
  • –40ºC to +85ºC operating temperature
  • Clock buffer for 300MHz to 18GHz frequency
  • Divider output frequency supported up to 8GHz
  • Ultra-Low Noise
    • Noise floor of –161dBc/Hz at 6GHz output
    • 36fs additive jitter (100Hz to fCLK) at 6GHz output
    • 5fs additive jitter (100Hz - 100MHz)
  • 4 high-frequency clocks output
    • with shared divider by 1 (Bypass), 2, 3, 4, 5, 6, 7, and 8
  • 1ps typical output to output skew
  • Support pin mode options for outputs enable and divider /2, /3 and /4 values set
  • AUXCLK output
    • On separate divide bank
    • 1, 2, 4 pre-divider
    • 1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • SYNC feature to all divides
  • 2.5V operating voltage
  • –40ºC to +85ºC operating temperature

The LMX1214 features high output frequency, ultra-low noise floor, and very low skew clocks distribution. The device has four high-frequency output clocks and a lower frequency auxiliary clock output. The device supports both buffer and divide mode for the high-frequency clocks. This device can distribute the mutlichannel, low skew, ultra-low noise local oscillator signals to multiple mixers.

The LMX1214 features high output frequency, ultra-low noise floor, and very low skew clocks distribution. The device has four high-frequency output clocks and a lower frequency auxiliary clock output. The device supports both buffer and divide mode for the high-frequency clocks. This device can distribute the mutlichannel, low skew, ultra-low noise local oscillator signals to multiple mixers.

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重要文件 類型 標題 格式選項 日期
* Data sheet LMX1214 Low-Noise, High-Frequency Buffer and Divider datasheet (Rev. A) PDF | HTML 2024年 9月 17日
Certificate LMX1214EVM EU Declaration of Conformity (DoC) 2023年 12月 18日

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開發板

LMX1214EVM — LMX1214 評估模組

LMX1214 評估模組 (EVM) 設計旨在評估 LMX1214 的性能,其為一款四路輸出、超低附加抖動射頻 (RF) 緩衝器和分頻器。本裝置可緩衝高達 16GHz 的無線電頻率,並將輸出除以高達 6.4GHz。此基板由 LMX1214 裝置和整合式 USB2ANY 程式設計工具組成。

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TICSPRO-SW TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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LMX1214 IBIS Model

SNAM294.ZIP (53 KB) - IBIS Model
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PLLATINUMSIM-SW PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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VQFN (RHA) 40 Ultra Librarian

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