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射頻 (RF) 與微波
RF PLL 與合成器

LMX1204

現行

具 JESD204B/C SYSREF 支援和相位同步的 12.8 GHz RF 緩衝器、倍頻器和分頻器

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產品規格表

LMX1204

現行
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產品詳細資料

Frequency (max) (MHz) 12800 Frequency (min) (MHz) 300 Features Integrated multiplier and divider modes, JESD204B/C SYSREF support, Phase synchronization, RF clock distribution, Ultra-low additive jitter Current consumption (mA) 405 Integrated VCO No Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
Frequency (max) (MHz) 12800 Frequency (min) (MHz) 300 Features Integrated multiplier and divider modes, JESD204B/C SYSREF support, Phase synchronization, RF clock distribution, Ultra-low additive jitter Current consumption (mA) 405 Integrated VCO No Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
VQFN (RHA) 40 36 mm² 6 x 6
  • 300MHz to 12.8GHz output frequency
  • Ultra-low noise
    • Noise floor of –161dBc/Hz at 6GHz output
    • 1/f Noise of –154dBc/Hz at 6GHz output, 10kHz offset
    • 5fs jitter (12kHz to 20MHz)
    • <30fs additive jitter (DC to fCLK )
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divider that supports ÷1 (buffer mode), ÷2, 3, 4, 5, 6, 7, and 8
    • Shared PLL-based multiplier that supports x1 (filter mode), x2, x3, and x4
  • LOGICLK and corresponding SYSREF outputs
    • On separate divide bank
    • ÷1, 2, 4 pre-divider
    • ÷1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5ps each at 12.8GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5V operating voltage
  • –40ºC to 85ºC operating temperature
  • 300MHz to 12.8GHz output frequency
  • Ultra-low noise
    • Noise floor of –161dBc/Hz at 6GHz output
    • 1/f Noise of –154dBc/Hz at 6GHz output, 10kHz offset
    • 5fs jitter (12kHz to 20MHz)
    • <30fs additive jitter (DC to fCLK )
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divider that supports ÷1 (buffer mode), ÷2, 3, 4, 5, 6, 7, and 8
    • Shared PLL-based multiplier that supports x1 (filter mode), x2, x3, and x4
  • LOGICLK and corresponding SYSREF outputs
    • On separate divide bank
    • ÷1, 2, 4 pre-divider
    • ÷1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5ps each at 12.8GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5V operating voltage
  • –40ºC to 85ºC operating temperature

The high-frequency capability and extremely low jitter of this device, makes a great approach to clock precision, high-frequency data converters without degradation to the signal-to-noise ratio. Each of the four high-frequency clock outputs, and additional LOGICLK output with larger divider range, is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. For data converter clocking applications, having the jitter of the clock be less than the aperture jitter of the data converter is critical. In applications where more than four data converters must be clocked, a variety of cascading architectures can be developed using multiple devices to distribute all the high-frequency clocks and SYSREF signals required. With low jitter and noise floor, this device combined with an ultra-low noise reference clock source is an exemplary selection for clocking data converters, especially when sampling above 3GHz.

The high-frequency capability and extremely low jitter of this device, makes a great approach to clock precision, high-frequency data converters without degradation to the signal-to-noise ratio. Each of the four high-frequency clock outputs, and additional LOGICLK output with larger divider range, is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. For data converter clocking applications, having the jitter of the clock be less than the aperture jitter of the data converter is critical. In applications where more than four data converters must be clocked, a variety of cascading architectures can be developed using multiple devices to distribute all the high-frequency clocks and SYSREF signals required. With low jitter and noise floor, this device combined with an ultra-low noise reference clock source is an exemplary selection for clocking data converters, especially when sampling above 3GHz.
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重要文件 類型 標題 格式選項 日期
* Data sheet LMX1204 Low-Noise, High-Frequency JESD Buffer/Multiplier/Divider datasheet (Rev. B) PDF | HTML 2024年 2月 20日
Application note Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 2025年 4月 11日
Design guide Cascaded Clock Distribution Reference Design Supports 16 High Frequency Outputs PDF | HTML 2024年 3月 4日
Application note Cascaded LMX1204 Phase-Error Analysis PDF | HTML 2023年 1月 12日
Application note LMX1204 Multiplier Clock Distribution Drives Large Phased-Array Systems PDF | HTML 2022年 10月 31日
User guide LMX1204 Register Map (Rev. A) PDF | HTML 2022年 9月 28日
Application note Getting the Most of Your Data Converter Clocking System Using LMX1204 PDF | HTML 2022年 6月 23日

設計與開發

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開發板

LMX1204EVM — 適用於具 JESD204B/C SYSREF 支援的 RF 緩衝器、倍頻器和分頻器的 LMX1204 的評估模組

LMX1204 評估模組 (EVM) 設計旨在評估 LMX1204 的性能，其為四路輸出、超低附加抖動無線電頻率 (RF) 緩衝器、分頻器和倍頻器。此 EVM 可緩衝最多 12.8GHz 的射頻時鐘輸入，在 3.2GHz 至 6.4GHz 的輸出範圍內乘以 x2、x3 或 x4，並將輸入除最多八。

可程式設計邏輯閘陣列 (FPGA) 和邏輯時鐘中隨附獨立的輔助時鐘分頻器，而每個輸出均包含具皮秒精度及延遲微調功能的系統參考 (SYSREF) 補數。多個裝置可針對廣泛的時鐘分配樹狀結構進行同步化。

使用指南: PDF | HTML
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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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模擬型號

LMX1204 IBIS Model

SNAM255.ZIP (44 KB) - IBIS Model
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設計工具

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。
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設計工具

PLLATINUMSIM-SW — PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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參考設計

TIDA-010259 — 串連 LMX1204 參考設計

串連 LMX1204 參考設計可將單一時鐘輸入分配至 16 時鐘輸出。  適合高達 12.8 GHz 的高頻作業，對時脈訊號幾乎沒有相位雜訊影響。  非常適用於大型相位陣列系統中的時脈高速資料轉換器。
Design guide: PDF
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