LMK6B
- Industry’s lowest jitter:
- 9.3fs typical differential RMS jitter at 625MHz HS-LVDS with 4MHz 1st order high-pass filter (12kHz to 20MHz)
- 19.7fs typical differential RMS jitter at 312.5MHz AC-LVPECL with 4MHz 1st order high-pass filter (12kHz to 20MHz)
- 16fs typical RMS jitter at 2500MHz AC-LVPECL output (12kHz to 20MHz)
- 18fs typical, 35fs max RMS jitter at 625MHz AC-LVPECL output (12kHz to 20MHz)
- 28fs typical RMS jitter at 312.5MHz AC-LVPECL output (12kHz to 20MHz)
- Exceptional PSRR performance
(ripple frequencies > 10kHz, 50mV supply ripple, 0.1µF decoupling
capacitor):
- < -95dBc spurs for 156.25MHz LP-HCSL
- < -80dBc spurs for 312.5MHz LVDS
- Output frequency:
- Initial frequency offerings: 100, 125, 156.25, 312.5, 625, 1250, 2500MHz, and others
- Preview, contact TI: 322.265625, 390.625, 425, 496,
603.2291, 804.305467, 2343.75, 2400, 2412.91636, 2457.6, 2480, 2550,
2578.125MHz
- Other fixed frequencies on request
- Supports PCIe Gen 1 to Gen 7
- Output formats:
- LVDS, HS-LVDS, AC-LVPECL, Custom Swing: 50MHz to 2500MHz
- LP-HCSL: 50MHz to 625MHz
- ±25ppm total frequency stability
(inclusive of all factors with 10-year aging at 25°C board temperature)
- ±7ppm temperature variation (-40°C to 105°C)
- Preview, contact TI: ±20ppm total frequency stability (inclusive of all factors with 10-year aging at 85°C board temperature)
- 91mA maximum current consumption (AC-LVPECL, Custom Swing, LVDS, HS-LVDS)
- 85mA maximum current consumption (LP-HCSL)
- 2.5V / 3.3V power supply (2.375V through 3.465V)
- Industry standard 6-pin package:
- 2.0mm × 1.6mm (wettable flank)
- Preview, contact TI: 2.5mm × 2.0mm, 3.2mm × 2.5mm
- -40°C to 105°C PCB temperature
The LMK6Bx device is an ultra-low jitter, fixed frequency oscillator achieving 9.3fs at 625MHz. This device incorporates the BAW as the resonator source. The device is factory programmed per specific operation mode, including frequency, output type, function pin, and frequency stability.
The high-performance clocking, mechanical stability, flexibility, and small package options for this device are designed for reference and core clocks in high-speed SerDes used in telecommunications, data and enterprise network, and industrial applications.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LMK6B 9.3fs Ultra-Low Jitter, High-performance Differential Oscillator datasheet | PDF | HTML | 2026/3/10 | ||
| 應用說明 | Clocking LMK6Bx with TI Clock Buffers (Rev. A) | PDF | HTML | 2026/5/19 | |||
| 應用說明 | The LMK6B: Revolutionizing Optical Module Performance with Industry-Leading Ultra-Low Jitter BAW Oscillators (Rev. A) | PDF | HTML | 2026/5/5 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
PLLATINUMSIM-SW — PLL 迴路濾波器、相位雜訊、鎖定時間與雜散模擬工具
PLLATINUMSIM-SW 為一模擬工具，可讓使用者建立 PLLatinum™ 積體電路的詳細設計和模擬，包括 LMX 系列的相位鎖定迴路 (PLL) 及合成器。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VSON (DLR) | 6 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。