開發模組 (EVM) 的 GUI
LMK6B-GUI — Prerelease GUI for LMK6B test chip
LMK6B test chip does not include e-fuse for frequency configuration. TICS Pro 2 profile for LMK6B test chip allows programming the test chip to arbitrary frequencies.
LMK6B
- Industry’s lowest jitter:
- 9.3fs typical differential RMS jitter at 625MHz HS-LVDS with 4MHz 1st order high-pass filter (12kHz to 20MHz)
- 19.7fs typical differential RMS jitter at 312.5MHz AC-LVPECL with 4MHz 1st order high-pass filter (12kHz to 20MHz)
- 16fs typical RMS jitter at 2500MHz AC-LVPECL output (12kHz to 20MHz)
- 18fs typical, 35fs max RMS jitter at 625MHz AC-LVPECL output (12kHz to 20MHz)
- 28fs typical RMS jitter at 312.5MHz AC-LVPECL output (12kHz to 20MHz)
- Exceptional PSRR performance (ripple frequencies > 10kHz, 50mV supply ripple, 0.1µF decoupling capacitor):
- < -95dBc spurs for 156.25MHz LP-HCSL
- < -80dBc spurs for 312.5MHz LVDS
- Output frequency:
- Initial frequency offerings: 100, 125, 156.25, 312.5, 625, 1250, 2500MHz, and others
- Preview, contact TI: 322.265625, 390.625, 425, 496, 603.2291, 804.305467, 2343.75, 2400, 2412.91636, 2457.6, 2480, 2550, 2578.125MHz
- Other fixed frequencies on request
- Supports PCIe Gen 1 to Gen 7
- Output formats:
- LVDS, HS-LVDS, AC-LVPECL, Custom Swing: 50MHz to 2500MHz
- LP-HCSL: 50MHz to 625MHz
- ±25ppm total frequency stability (inclusive of all factors with 10-year aging at 25°C board temperature)
- ±7ppm temperature variation (-40°C to 105°C)
- Preview, contact TI: ±20ppm total frequency stability (inclusive of all factors with 10-year aging at 85°C board temperature)
- 91mA maximum current consumption (AC-LVPECL, Custom Swing, LVDS, HS-LVDS)
- 85mA maximum current consumption (LP-HCSL)
- 2.5V / 3.3V power supply (2.375V through 3.465V)
- Industry standard 6-pin package:
- 2.0mm × 1.6mm (wettable flank)
- Preview, contact TI: 2.5mm × 2.0mm, 3.2mm × 2.5mm
- -40°C to 105°C PCB temperature
The LMK6Bx device is an ultra-low jitter, fixed frequency oscillator achieving 9.3fs at 625MHz. This device incorporates the BAW as the resonator source. The device is factory programmed per specific operation mode, including frequency, output type, function pin, and frequency stability.
The high-performance clocking, mechanical stability, flexibility, and small package options for this device are designed for reference and core clocks in high-speed SerDes used in telecommunications, data and enterprise network, and industrial applications.
技術文件
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檢視所有 4 | 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | LMK6Bx Ultra Low Jitter, High-Performance BAW Oscillator datasheet | PDF | HTML | 2026年 3月 10日 |
| Application note | Clocking LMK6Bx with TI Clock Buffers | PDF | HTML | 2026年 3月 11日 | |
| Application note | The LMK6B: Revolutionizing Optical Module Performance with Industry-Leading Ultra-Low Jitter BAW Oscillators | PDF | HTML | 2026年 3月 11日 | |
| EVM User's guide | LMK6B Evaluation Module | PDF | HTML | 2026年 3月 9日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
設計工具
PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
支援產品和硬體
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。
PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。
在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。
在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VSON (DLR) | 6 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點