LMK1D1208P
- High-performance LVDS clock buffer family with 2 inputs and 8 outputs (2:8)
- Output frequency up to 2 GHz
- Hardware pins for individual output enable/disable
- Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5%
- Low additive jitter: < 60 fs rms maximum in 12 kHz to 20 MHz at 156.25 MHz
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Very low phase noise floor: -164 dBc/Hz (typical)
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Very low propagation delay: < 575 ps maximum
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Output skew: 20 ps maximum
- Fail-safe inputs
- Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
- LVDS reference voltage, V AC_REF, available for capacitive-coupled inputs
- Industrial temperature range: –40°C to 105°C
- Packages available:
- 6-mm × 6-mm, 40-pin VQFN (RHA)
The LMK1D1208P clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The inputs can be either LVDS, LVPECL, LVCMOS, HCSL, or CML.
The LMK1D1208P is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. The part supports a fail-safe input function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
Each LVDS differential output is enabled by setting the corresponding OEx pin to a logic high 1. If this pin is set to a logic low 0, the output is disabled in a Hi-Z state resulting in reduced power consumption.
The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LMK1D1208P Pin-Controlled OE Low Additive Jitter LVDS Buffer datasheet (Rev. A) | PDF | HTML | 2023/6/2 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RHA) | 40 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。