LMK04806
- Ultra-Low RMS Jitter Performance
- 111 fs RMS Jitter (12 kHz to 20 MHz)
- 123 fs RMS Jitter (100 Hz to 20 MHz)
- Dual Loop PLLatinum™ PLL Architecture
- PLL1
- Integrated Low-Noise Crystal Oscillator
Circuit - Holdover Mode when Input Clocks are Lost
- Automatic or Manual Triggering/Recovery
- Integrated Low-Noise Crystal Oscillator
- PLL2
- Normalized PLL Noise Floor of –227 dBc/Hz
- Phase Detector Rate up to 155 MHz
- OSCin Frequency-Doubler
- Integrated Low-Noise VCO
- 2 Redundant Input Clocks with LOS
- Automatic and Manual Switch-Over Modes
- 50 % Duty Cycle Output Divides, 1 to 1045 (Even
and Odd) - 12 LVPECL, LVDS, or LVCMOS Programmable
Outputs - Digital Delay: Fixed or Dynamically Adjustable
- 25 ps Step Analog Delay Control.
- 14 Differential Outputs. Up to 26 Single Ended.
- Up to 6 VCXO/Crystal Buffered Outputs
- Clock Rates of up to 1536 MHz
- 0-Delay Mode
- Three Default Clock Outputs at Power Up
- Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution - Industrial Temperature Range: –40 to 85°C
- 3.15-V to 3.45-V Operation
- 2 Dedicated Buffered/Divided OSCin Clocks
- Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)
The LMK0480x family is the industry’s highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum architecture is capable of 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.
The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs datasheet (Rev. K) | PDF | HTML | 2014/12/24 | ||
| 設計指南 | TSW308x Wideband Digital to RF Transmit Solution Design Guide | 2013/9/3 | ||||
| 設計指南 | TSW1265 Dual-Wideband RF-to-Digital Receiver Design Guide | 2013/9/3 | ||||
| 應用說明 | Using the LMK0480x/LMK04906 for Hitless Switching and Holdover | 2013/7/12 | ||||
| 使用指南 | TSW3085EVM ACPR and EVM Measurements (TIDA-00076 Reference Guide) | 2011/12/29 | ||||
| 設計指南 | Clock Conditioner Owner's Manual | 2006/11/10 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
LMK04806BEVAL — 具有雙串接 PLL 和整合式 2.5 GHz VCO 的時鐘抖動清除器
The LMK04800 family is the industry's highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum? architecture enables 111 fs rms jitter (12 kHz to 20 MHz) using (...)
TSW1265EVM — 寬頻雙路接收器參考設計和評估平台
The TSW1265EVM is a wideband dual receiver reference design and evaluation platform. The signal chain allows conversion from RF to bits using a dual-channel downconverter mixer, the LMH6521 dual-channel DVGA, and the ADS4249 14-bit 250-MSPS ADC. The TSW1265EVM also includes the LMK04800 dual-PLL (...)
TSW3084EVM — 寬頻發射訊號鏈評估板和參考設計
The TSW3084EVM Evaluation Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit solution the TSW3084EVM includes (...)
TSW30H84EVM — 寬頻發射訊號鏈評估板和參考設計
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SLAC507 — TSW308x EVM Software
SLAC532 — TSW4806 Installer GUI
CODELOADER — CodeLoader Device Register Programming v4.19.0
The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
Product | (...) |
CLOCKDESIGNTOOL — Clock Design Tool Software
時脈設計工具軟體可協助進行零件選擇、迴路濾波器設計，以及計時裝置解決方案模擬。當您輸入所需的輸出頻率和參考頻率 (選用) 時，此工具可提供符合指定需求、分頻器值和建議迴路濾波器的 TI 裝置，以將抖動降到最低。
CLOCKDESIGNTOOL 教學影片
我應該使用哪個軟體？
產品 | 迴路濾波器和裝置配置 + 模擬 | 模擬工具 | 裝置暫存器程式化 |
LMX24xx PLL 系列 | EasyPLL | ||
LMX25xx PLL+VCO 系列 | 時脈設計工具 | ||
LMK 抖動清除器及分配器 |
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。
PLLATINUMSIM-SW — PLL 迴路濾波器、相位雜訊、鎖定時間與雜散模擬工具
PLLATINUMSIM-SW 為一模擬工具，可讓使用者建立 PLLatinum™ 積體電路的詳細設計和模擬，包括 LMX 系列的相位鎖定迴路 (PLL) 及合成器。
TIDA-00072 — 寬頻數位至射頻發送解決方案
TSW308x 是寬頻數位至 RF 傳輸解決方案的設計範例，可產生 600MHz 連續 RF 頻譜。 系統示範了如何使用 DAC34x8x、TRF3705 IQ 調變器和 LMK0480x 來達成此目標。 此參考 EVM 結合模式發生器（例如 TSW1400EVM），可在 RF 下任意產生窄頻和寬頻訊號。 其中提供了產生符合標準 WCDMA 測試訊號的配置範例。
TIDA-00076 — 相鄰通道功率比 (ACPR) 和誤差向量幅度 (%EVM) 量測
此參考設計討論如何將 TSW3085EVM 搭配 TSW3100 模式產生器使用，以測試 LTE 基頻訊號的相鄰頻道功率比 (ACPR) 和誤差向量幅度 (EVM) 量測。使用 TSW3100 LTE GUI 將模式載入到 TSW3085EVM 中，該 EVM 由 DAC3482、TRF3705 和 LMK04806 組成。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (NKD) | 64 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。