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LMK3H2104

現行

4 輸出、相容於 PCIe Gen 1 至 Gen 7、BAW 無參考時鐘產生器、時鐘多工器與緩衝器

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產品規格表

LMK3H2104

現行
產品規格表 立即訂購

產品詳細資料

Number of outputs 4 Output type LP-HCSL, LVCMOS, LVDS Output frequency (max) (MHz) 400 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Operating temperature range (°C) -40 to 105 Features I2C, One-Time Programmable (OTP) memory, PCIe Gen 1 - 7 compliant, Pin programmable, Serial interface Rating Catalog
Number of outputs 4 Output type LP-HCSL, LVCMOS, LVDS Output frequency (max) (MHz) 400 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Operating temperature range (°C) -40 to 105 Features I2C, One-Time Programmable (OTP) memory, PCIe Gen 1 - 7 compliant, Pin programmable, Serial interface Rating Catalog
VQFN (RGE) 24 16 mm² 4 x 4
  • Integrated BAW resonator
    • No need for external XTAL/XO
  • Flexible output frequency
    • 2 fraction output dividers (FOD), individual channel dividers
    • Up to 400MHz output frequency
  • Flexible output format
    • 1.2/1.8/2.5/3.3V LVCMOS
    • DC- or AC-coupled LVDS
    • LP-HCSL with programmable swing. LVPECL, CML and other formats can be derived from LP-HCSL
  • Very low jitter
    • 61fs max PCIe Gen 5 CC with SSC jitter
    • 36.4fs max PCIe Gen 6 CC with SSC jitter
    • 25.5fs max PCIe Gen 7 CC with SSC jitter
  • PCIe Gen 1 to Gen 7 compliant
  • Configurable SSC
    • Programmable -0.05% to -3% down spread and ±0.025% to ±1.5% center spread, or preset -0.1%, -0.25%, -0.3% and -0.5% down spread
  • 3 inputs (LMK3H2108) or 1 input (LMK3H2104) that can be bypassed to any output
  • 5ms max startup time
  • Fail-safe input pins can be pulled high when device power is off
  • Flexible power supply
    • Each VDD pin can be independently connected to = 1.8, 2.5 or 3.3V
    • Each VDDO pin can be independently connected set to 1.8, 2.5 or 3.3V
  • -40 to 105°C ambient temperature
  • Integrated BAW resonator
    • No need for external XTAL/XO
  • Flexible output frequency
    • 2 fraction output dividers (FOD), individual channel dividers
    • Up to 400MHz output frequency
  • Flexible output format
    • 1.2/1.8/2.5/3.3V LVCMOS
    • DC- or AC-coupled LVDS
    • LP-HCSL with programmable swing. LVPECL, CML and other formats can be derived from LP-HCSL
  • Very low jitter
    • 61fs max PCIe Gen 5 CC with SSC jitter
    • 36.4fs max PCIe Gen 6 CC with SSC jitter
    • 25.5fs max PCIe Gen 7 CC with SSC jitter
  • PCIe Gen 1 to Gen 7 compliant
  • Configurable SSC
    • Programmable -0.05% to -3% down spread and ±0.025% to ±1.5% center spread, or preset -0.1%, -0.25%, -0.3% and -0.5% down spread
  • 3 inputs (LMK3H2108) or 1 input (LMK3H2104) that can be bypassed to any output
  • 5ms max startup time
  • Fail-safe input pins can be pulled high when device power is off
  • Flexible power supply
    • Each VDD pin can be independently connected to = 1.8, 2.5 or 3.3V
    • Each VDDO pin can be independently connected set to 1.8, 2.5 or 3.3V
  • -40 to 105°C ambient temperature

LMK3H2104 and LMK3H2108 are BAW-based clock generators that do not require any external XTAL or XO. The devices can be used as PCIe clock generators or general purpose clock generators. The 2 FODs (Fractional Output Divider) provide frequency flexibility, low power and low jitter at the same time.

LMK3H2104 has up to 4 differential outputs plus 2 LVCMOS outputs or up to 10 LVCMOS outputs. LMK3H2108 has up to 8 differential outputs or 16 LVCMOS outputs.

LMK3H2104 has one clock input and LMK3H2108 has three clock inputs. The clock inputs provide clock multiplexing and buffering ability. Each output bank can independently select any clock source.

The GPI and GPIO pins provide additional control flexibility. These pins can be configured as individual OE, grouped OE, I2C address selection, OTP page selection, PWRGD/PWRDN#, status output and other functions.

The device supports one-time programmable (OTP) non-volatile memory which can be customized and factory preprogrammed.

LMK3H2104 and LMK3H2108 are BAW-based clock generators that do not require any external XTAL or XO. The devices can be used as PCIe clock generators or general purpose clock generators. The 2 FODs (Fractional Output Divider) provide frequency flexibility, low power and low jitter at the same time.

LMK3H2104 has up to 4 differential outputs plus 2 LVCMOS outputs or up to 10 LVCMOS outputs. LMK3H2108 has up to 8 differential outputs or 16 LVCMOS outputs.

LMK3H2104 has one clock input and LMK3H2108 has three clock inputs. The clock inputs provide clock multiplexing and buffering ability. Each output bank can independently select any clock source.

The GPI and GPIO pins provide additional control flexibility. These pins can be configured as individual OE, grouped OE, I2C address selection, OTP page selection, PWRGD/PWRDN#, status output and other functions.

The device supports one-time programmable (OTP) non-volatile memory which can be customized and factory preprogrammed.
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技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet LMK3H2104 and LMK3H2108 4- or 8-Output PCIe Gen 1-6 Compliant Low jitter General Purpose BAW Clock Generator datasheet (Rev. A) 2025年 10月 30日
User guide LMK3H2104(L) Configuration Addendum PDF | HTML 2026年 1月 22日
User guide LMK3H2104A01 Configuration Guide PDF | HTML 2026年 1月 22日
User guide LMK3H2104A01 Register Map PDF | HTML 2026年 1月 22日
User guide LMK3H2104A09 Configuration Guide PDF | HTML 2026年 1月 22日
User guide LMK3H2104A09 Register Map PDF | HTML 2026年 1月 22日
User guide LMK3H2104A0D Register Map PDF | HTML 2026年 1月 22日
User guide LMK3H2104A0E Configuration Guide PDF | HTML 2026年 1月 22日
User guide LMK3H2104A0E Register Map PDF | HTML 2026年 1月 22日
User guide LMK3H2104x02 Register Map PDF | HTML 2026年 1月 22日
User guide LMK3H2104A10 Register Map PDF | HTML 2026年 1月 21日
User guide LMK3H2104 Register Map PDF | HTML 2025年 8月 21日
Certificate LMK3H2104EVM EU Declaration of Conformity (DoC) 2025年 7月 22日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

應用軟體及架構

LMK3H2108-DESIGN — LMK3H210x configuration GUI software

Software provides configuration support for LMK3H2104 and LMK3H2108 devices
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應用軟體及架構

LMK3H2108-GUI — Programming GUI for the public release of the LMK3H2108 devices.

The TICS Pro 2 software is required for interfacing with the LMK3H210x family of devices. This allows for handling of the register paging functionality automatically.
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模擬型號

LMK3H210X IBIS Model

SNAM304.ZIP (291 KB) - IBIS Model
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設計工具

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN (RGE) 24 Ultra Librarian
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