LMK00301
- 3:1 input multiplexer
- Two universal inputs operate up to 3.1GHz and accept lvpecl, lvds, cml, sstl, hstl, hcsl, or single-ended clocks
- One crystal input accepts 10MHz to 40Mhz crystal or single-ended clock
- Two banks with five differential outputs each
- LVPECL, LVDS, HCSL, or Hi-Z (selectable per bank)
- LVPECL additive jitter with LMK03806 clock source
at 156.25MHz:
- 20 fs RMS (10kHz to 1MHz)
- 51 fs RMS (12kHz to 20MHz)
- Frequency range:
- LVPECL (DC to 3100MHz)
- LVDS (DC to 2100MHz)
- HCSL (DC to 800MHz)
- LVCMOS (DC to 250MHz)
- Additive RMS Jitter after PCIe Filters:
- Gen 7: 9.38fs (LVPECL), 10.1fs (HCSL), 12.6fs (LVDS) (maxima)
- Gen 6: 13.4fs (LVPECL), 14.3fs (HCSL), 18.0fs (LVDS) (maxima)
- Gen 5: 21.8fs (LVPECL), 23.6fs (HCSL), 30.3fs (LVDS) (maxima)
- High PSRR: –65dBc (LVPECL) and –76dBc (LVDS) at 156.25MHz
- LVCMOS output with synchronous enable input
- Pin-controlled configuration
- VCC core supply: 3.3V ± 5%
- Three independent VCCO output supplies: 3.3V or 2.5V ± 5%
- Industrial temperature range: –40°C to +85°C
The LMK00301 is a 3GHz, 10-output differential fanout buffer intended for high-frequency, low-jitter clock and data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of five differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00301 operates from a 3.3V core supply and three independent 3.3V or 2.5V output supplies.
The LMK00301 provides high performance, versatility, and power efficiency, making the device designed for replacing fixed-output buffer devices while increasing timing margin in the system. The LMK00301 offers a design spin, the LMK00301A, that does not have power supply sequencing requirements between the core and output supply domains.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LMK00301 3GHz 10-Output Ultra-Low Additive Jitter Differential Clock Buffer and Level Translator datasheet (Rev. L) | PDF | HTML | 2026/4/15 | ||
| 應用說明 | Sine to Square Wave Conversion Using Clock Buffers | PDF | HTML | 2024/9/3 | |||
| 應用說明 | Clocking for PCIe Applications | PDF | HTML | 2023/11/28 | |||
| 應用說明 | Clocking for Medical Ultrasound Systems (Rev. A) | PDF | HTML | 2020/9/30 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
LMK00301EVAL — LMK00301 評估板
The LMK00301 Evaluation Board allows functional and performance verification of the LMK00301 high-performance 1:10 differential fanout buffer device.
CLOCKDESIGNTOOL — Clock Design Tool Software
時脈設計工具軟體可協助進行零件選擇、迴路濾波器設計，以及計時裝置解決方案模擬。當您輸入所需的輸出頻率和參考頻率 (選用) 時，此工具可提供符合指定需求、分頻器值和建議迴路濾波器的 TI 裝置，以將抖動降到最低。
CLOCKDESIGNTOOL 教學影片
我應該使用哪個軟體？
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CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。
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PLLATINUMSIM-SW 為一模擬工具，可讓使用者建立 PLLatinum™ 積體電路的詳細設計和模擬，包括 LMX 系列的相位鎖定迴路 (PLL) 及合成器。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
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