開發模組 (EVM) 的 GUI
TRF3765
- Output Frequencies: 300 MHz to 4.8 GHz
- Low-Noise VCO: –133 dBc/Hz
(1-MHz Offset, fOUT = 2.65 GHz) - 13-/16-Bit Reference/Feedback Divider
- 25-Bit Fractional-N and Integer-N PLL
- Low RMS Jitter: 0.35 ps
- Input Reference Frequency Range:
0.5 MHz to 350 MHz - Programmable Output Divide-by-1/-2/-4/-8
- Four Differential LO Outputs
- External VCO Input with Programmable VCO
On/Off Control
The TRF3765 is a wideband Integer-N/Fractional-N frequency synthesizer with an integrated, wideband voltage-controlled oscillator (VCO). Programmable output dividers enable continuous frequency coverage from 300 MHz to 4.8 GHz. Four separate differential, open-collector RF outputs allow multiple devices to be driven in parallel without the need of external splitters.
The TRF3765 also accepts external VCO input signals and allows on/off control through a programmable control output. For maximum flexibility and wide reference frequency range, wide-range divide ratio settings are programmable and an off-chip loop filter can be used.
The TRF3765 is available in an RHB-32 QFN package.
技術文件
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檢視所有 9 | 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | TRF3765 Integer-N/Fractional-N PLL With Integrated VCO datasheet (Rev. E) | PDF | HTML | 2016年 1月 7日 |
| Analog Design Journal | Analog Applications Journal 2Q 2015 | 2015年 4月 28日 | ||
| Analog Design Journal | JESD204B multi-device synchronization: Breaking down the requirements | 2015年 4月 28日 | ||
| Application note | Characterization Report for FMC30RF | 2014年 9月 18日 | ||
| Application note | TRF3765 Synthesizer Lock Time | 2012年 2月 6日 | ||
| Application note | TRF3765 REF_IN Impedance Application Note | 2012年 1月 11日 | ||
| Application note | Low supply TRF3765 performance evaluation | 2012年 1月 4日 | ||
| Application note | TRF3765 Output Terminations | 2012年 1月 4日 | ||
| Application note | Supply Noise Effect on Oscillator Phase Noise | 2011年 11月 22日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
TRF3765EVM — TRF3765 評估模組
The TRF3765EVM evaluation module is intended to enable the evaluation of the TRF3765 Integer-N/Fractional-N PLL with Integrated VCO for wideband frequency synthesis. Applications include Wireless Infrastructure, Wireless Local Loop, Point-to-Point Wireless Access, and Wireless MAN Wideband (...)
使用指南: PDF
開發板
TSW3065EVM — TSW3065 獨立本地振盪器來源評估模組
The TSW3065EVM is based on Texas Instruments integer-N / Fractional –N frequency synthesizer with integrated wideband VCO TRF3765. Its frequency ranges from 300 MHz to 4.8 GHz. It provides programmable output power with a combination of amplifier and programmable attenuator. TSW3065EVM has an (...)
使用指南: PDF
開發模組 (EVM) 的 GUI
SLWC108 — TRF3765 GUI
支援產品和硬體
外掛程式
ABACO-3P-FMC30RFFPGA — Abaco Systems® FMC30RF FPGA 夾層介面卡
The FMC30RF is an FMC daughter card which is fully compliant with the VITA 57.1 FMC standard. The FMC30RF offers in a small footprint, a low power and fully featured Rx/Tx signal path for the development of advanced RF solutions. With a frequency range coverage from 400 MHz to 3.0 GHz and up to 30 (...)
設計工具
PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
支援產品和硬體
參考設計
TIDA-00431 — 採用 8 GHz DC 耦合差動放大器的射頻取樣 4 GSPS ADC 參考設計
Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies.
This reference design describes a wideband RF (...)
參考設計
TIDA-01015 — 適用於數位示波器和無線測試器中的 12 位元高速 ADC 的 4 GHz 時鐘參考設計
TIDA-01015 是一款針對高速直接射頻取樣 GSPS ADC 的時鐘解決方案參考設計。此設計展現了取樣時鐘對於實現第二奈奎斯特區輸入訊號頻率之高 SNR 的重要性。ADC12J4000 是一款 12 位元、4GSPS 的射頻取樣 ADC，具有 3.2GHz 的 3dB 輸入頻寬，可擷取高達 4GHz 的訊號。此設計重點展示採用 TRF3765 的時鐘解決方案，用於 ADC12J4000，可在高輸入頻率下實現優異的 SNR 性能，適用於數位儲存示波器 (DSO) 和無線測試儀等應用。
參考設計
TIDA-00826 — 50 Ohm 2 GHz 示波器前端參考設計
This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
參考設計
TIDA-00359 — 適用於 GSPS ADC 的時鐘解決方案參考設計
Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RHB) | 32 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。