SPRUJ53 User guide | 德州仪器 TI.com.cn

SPRUJ53 April 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

1
Read This First
1. About This Manual
2. Notational Conventions
3. Glossary
4. Related Documentation From Texas Instruments
5. Support Resources
6. Trademarks
1 C2000™ Microcontrollers Software Support
1. 1.1 Introduction
2. 1.2 C2000Ware Structure
3. 1.3 Documentation
4. 1.4 Devices
5. 1.5 Libraries
6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
7. 1.7 SysConfig and PinMUX Tool
2 C28x Processor
1. 2.1 Introduction
2. 2.2 C28X Related Collateral
3. 2.3 Features
4. 2.4 Floating-Point Unit
5. 2.5 Trigonometric Math Unit (TMU)
6. 2.6 VCRC Unit
3 System Control and Interrupts
1. 3.1 Introduction
2. 3.2 Power Management
3. 3.3 Device Identification and Configuration Registers
4. 3.4 Resets
5. 3.5 Peripheral Interrupts
6. 3.6 Exceptions and Non-Maskable Interrupts
7. 3.7 Clocking
8. 3.8 32-Bit CPU Timers 0/1/2
9. 3.9 Watchdog Timer
10. 3.10 Low-Power Modes
11. 3.11 Memory Controller Module
  1. 3.11.1 Functional Description
12. 3.12 JTAG
  1. 3.12.1 JTAG Noise and TAP_STATUS
13. 3.13 Live Firmware Update
14. 3.14 System Control Register Configuration Restrictions
15. 3.15 Software
16. 3.16 SYSCTRL Registers
4 ROM Code and Peripheral Booting
1. 4.1 Introduction
  1. 4.1.1 ROM Related Collateral
2. 4.2 Device Boot Sequence
3. 4.3 Device Boot Modes
  1. 4.3.1 Default Boot Modes
  2. 4.3.2 Custom Boot Modes
4. 4.4 Device Boot Configurations
5. 4.5 Device Boot Flow Diagrams
6. 4.6 Device Reset and Exception Handling
  1. 4.6.1 Reset Causes and Handling
  2. 4.6.2 Exceptions and Interrupts Handling
7. 4.7 Boot ROM Description
8. 4.8 Application Notes for Using the Bootloaders
  1. 4.8.1 Bootloader Data Stream Structure
    1. 4.8.1.1 Data Stream Structure 8-bit
  2. 4.8.2 The C2000 Hex Utility
    1. 4.8.2.1 HEX2000.exe Command Syntax
9. 4.9 Software
  1. 4.9.1 BOOT Examples
5 Dual Code Security Module (DCSM)
1. 5.1 Introduction
  1. 5.1.1 DCSM Related Collateral
2. 5.2 Functional Description
3. 5.3 Flash and OTP Erase/Program
4. 5.4 Secure Copy Code
5. 5.5 SecureCRC
6. 5.6 CSM Impact on Other On-Chip Resources
7. 5.7 Incorporating Code Security in User Applications
8. 5.8 Software
  1. 5.8.1 DCSM Registers to Driverlib Functions
  2. 5.8.2 DCSM Examples
    1. 5.8.2.1 Empty DCSM Tool Example
9. 5.9 DCSM Registers
6 Flash Module
1. 6.1 Introduction to Flash and OTP Memory
2. 6.2 Flash Bank, OTP, and Pump
3. 6.3 Flash Wrapper
4. 6.4 Flash and OTP Memory Performance
5. 6.5 Flash Read Interface
  1. 6.5.1 C28x-Flash Read Interface
6. 6.6 Flash Erase and Program
7. 6.7 Error Correction Code (ECC) Protection
8. 6.8 Reserved Locations Within Flash and OTP
9. 6.9 Migrating an Application from RAM to Flash
10. 6.10 Procedure to Change the Flash Control Registers
11. 6.11 Software
  1. 6.11.1 FLASH Registers to Driverlib Functions
  2. 6.11.2 FLASH Examples
    1. 6.11.2.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
    2. 6.11.2.2 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
12. 6.12 FLASH Registers
7 Control Law Accelerator (CLA)
1. 7.1 Introduction
2. 7.2 CLA Interface
3. 7.3 CLA, DMA, and CPU Arbitration
4. 7.4 CLA Configuration and Debug
5. 7.5 Pipeline
6. 7.6 Software
  1. 7.6.1 CLA Registers to Driverlib Functions
  2. 7.6.2 CLA Examples
7. 7.7 Instruction Set
  1. 7.7.1 Instruction Descriptions
  2. 7.7.2 Addressing Modes and Encoding
  3. 7.7.3 Instructions
    1. MABSF32 MRa, MRb
    2. MADD32 MRa, MRb, MRc
    3. MADDF32 MRa, #16FHi, MRb
    4. MADDF32 MRa, MRb, #16FHi
    5. MADDF32 MRa, MRb, MRc
    6. MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
    7. MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
    8. MAND32 MRa, MRb, MRc
    9. MASR32 MRa, #SHIFT
    10. MBCNDD 16BitDest {, CNDF}
    11. MCCNDD 16BitDest {, CNDF}
    12. MCMP32 MRa, MRb
    13. MCMPF32 MRa, MRb
    14. MCMPF32 MRa, #16FHi
    15. MDEBUGSTOP
    16. MEALLOW
    17. MEDIS
    18. MEINVF32 MRa, MRb
    19. MEISQRTF32 MRa, MRb
    20. MF32TOI16 MRa, MRb
    21. MF32TOI16R MRa, MRb
    22. MF32TOI32 MRa, MRb
    23. MF32TOUI16 MRa, MRb
    24. MF32TOUI16R MRa, MRb
    25. MF32TOUI32 MRa, MRb
    26. MFRACF32 MRa, MRb
    27. MI16TOF32 MRa, MRb
    28. MI16TOF32 MRa, mem16
    29. MI32TOF32 MRa, mem32
    30. MI32TOF32 MRa, MRb
    31. MLSL32 MRa, #SHIFT
    32. MLSR32 MRa, #SHIFT
    33. MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
    34. MMAXF32 MRa, MRb
    35. MMAXF32 MRa, #16FHi
    36. MMINF32 MRa, MRb
    37. MMINF32 MRa, #16FHi
    38. MMOV16 MARx, MRa, #16I
    39. MMOV16 MARx, mem16
    40. MMOV16 mem16, MARx
    41. MMOV16 mem16, MRa
    42. MMOV32 mem32, MRa
    43. MMOV32 mem32, MSTF
    44. MMOV32 MRa, mem32 {, CNDF}
    45. MMOV32 MRa, MRb {, CNDF}
    46. MMOV32 MSTF, mem32
    47. MMOVD32 MRa, mem32
    48. MMOVF32 MRa, #32F
    49. MMOVI16 MARx, #16I
    50. MMOVI32 MRa, #32FHex
    51. MMOVIZ MRa, #16FHi
    52. MMOVZ16 MRa, mem16
    53. MMOVXI MRa, #16FLoHex
    54. MMPYF32 MRa, MRb, MRc
    55. MMPYF32 MRa, #16FHi, MRb
    56. MMPYF32 MRa, MRb, #16FHi
    57. MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
    58. MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
    59. MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
    60. MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
    61. MNEGF32 MRa, MRb{, CNDF}
    62. MNOP
    63. MOR32 MRa, MRb, MRc
    64. MRCNDD {CNDF}
    65. MSETFLG FLAG, VALUE
    66. MSTOP
    67. MSUB32 MRa, MRb, MRc
    68. MSUBF32 MRa, MRb, MRc
    69. MSUBF32 MRa, #16FHi, MRb
    70. MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
    71. MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
    72. MSWAPF MRa, MRb {, CNDF}
    73. MTESTTF CNDF
    74. MUI16TOF32 MRa, mem16
    75. MUI16TOF32 MRa, MRb
    76. MUI32TOF32 MRa, mem32
    77. MUI32TOF32 MRa, MRb
    78. MXOR32 MRa, MRb, MRc
8. 7.8 CLA Registers
8 Dual-Clock Comparator (DCC)
1. 8.1 Introduction
  1. 8.1.1 Features
  2. 8.1.2 Block Diagram
2. 8.2 Module Operation
3. 8.3 Interrupts
4. 8.4 Software
  1. 8.4.1 DCC Registers to Driverlib Functions
  2. 8.4.2 DCC Examples
5. 8.5 DCC Registers
  1. 8.5.1 DCC Base Address Table
  2. 8.5.2 DCC_REGS Registers
9 General-Purpose Input/Output (GPIO)
1. 9.1 Introduction
  1. 9.1.1 GPIO Related Collateral
2. 9.2 Configuration Overview
3. 9.3 Digital Inputs on ADC Pins (AIOs)
4. 9.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
5. 9.5 Digital General-Purpose I/O Control
6. 9.6 Input Qualification
7. 9.7 USB Signals
8. 9.8 PMBUS and I2C Signals
9. 9.9 GPIO and Peripheral Muxing
  1. 9.9.1 GPIO Muxing
  2. 9.9.2 Peripheral Muxing
10. 9.10 Internal Pullup Configuration Requirements
11. 9.11 Software
12. 9.12 GPIO Registers
10Crossbar (X-BAR)
1. 10.1 Input X-BAR and CLB Input X-BAR
  1. 10.1.1 CLB Input X-BAR
2. 10.2 ePWM, CLB, and GPIO Output X-BAR
3. 10.3 Software
4. 10.4 XBAR Registers
11Direct Memory Access (DMA)
1. 11.1 Introduction
  1. 11.1.1 Features
  2. 11.1.2 Block Diagram
2. 11.2 Architecture
  1. 11.2.1 Peripheral Interrupt Event Trigger Sources
  2. 11.2.2 DMA Bus
3. 11.3 Address Pointer and Transfer Control
4. 11.4 Pipeline Timing and Throughput
5. 11.5 CPU and CLA Arbitration
6. 11.6 Channel Priority
  1. 11.6.1 Round-Robin Mode
  2. 11.6.2 Channel 1 High-Priority Mode
7. 11.7 Overrun Detection Feature
8. 11.8 Software
  1. 11.8.1 DMA Registers to Driverlib Functions
  2. 11.8.2 DMA Examples
    1. 11.8.2.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
    2. 11.8.2.2 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
9. 11.9 DMA Registers
12Embedded Real-time Analysis and Diagnostic (ERAD)
1. 12.1 Introduction
  1. 12.1.1 ERAD Related Collateral
2. 12.2 Enhanced Bus Comparator Unit
  1. 12.2.1 Enhanced Bus Comparator Unit Operations
  2. 12.2.2 Event Masking and Exporting
3. 12.3 System Event Counter Unit
4. 12.4 ERAD Ownership, Initialization and Reset
5. 12.5 ERAD Programming Sequence
  1. 12.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
  2. 12.5.2 Timer and Counter Programming Sequence
6. 12.6 Cyclic Redundancy Check Unit
  1. 12.6.1 CRC Unit Qualifier
  2. 12.6.2 CRC Unit Programming Sequence
7. 12.7 Program Counter Trace
8. 12.8 Software
  1. 12.8.1 ERAD Registers to Driverlib Functions
  2. 12.8.2 ERAD Examples
9. 12.9 ERAD Registers
13Analog Subsystem
1. 13.1 Introduction
  1. 13.1.1 Features
  2. 13.1.2 Block Diagram
2. 13.2 Optimizing Power-Up Time
3. 13.3 Digital Inputs on ADC Pins (AIOs)
4. 13.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
5. 13.5 Analog Pins and Internal Connections
6. 13.6 Software
  1. 13.6.1 ASYSCTL Registers to Driverlib Functions
7. 13.7 ASBSYS Registers
  1. 13.7.1 ASBSYS Base Address Table
  2. 13.7.2 ANALOG_SUBSYS_REGS Registers
14Analog-to-Digital Converter (ADC)
1. 14.1 Introduction
2. 14.2 ADC Configurability
3. 14.3 SOC Principle of Operation
4. 14.4 SOC Configuration Examples
5. 14.5 ADC Conversion Priority
6. 14.6 Burst Mode
  1. 14.6.1 Burst Mode Example
  2. 14.6.2 Burst Mode Priority Example
7. 14.7 EOC and Interrupt Operation
8. 14.8 Post-Processing Blocks
9. 14.9 Power-Up Sequence
10. 14.10 ADC Calibration
  1. 14.10.1 ADC Zero Offset Calibration
11. 14.11 ADC Timings
  1. 14.11.1 ADC Timing Diagrams
  2. 14.11.2 Post-Processing Block Timings
12. 14.12 Additional Information
13. 14.13 Software
  1. 14.13.1 ADC Registers to Driverlib Functions
  2. 14.13.2 ADC Examples
14. 14.14 ADC Registers
15Buffered Digital-to-Analog Converter (DAC)
1. 15.1 Introduction
2. 15.2 Using the DAC
3. 15.3 Lock Registers
4. 15.4 Software
  1. 15.4.1 DAC Registers to Driverlib Functions
  2. 15.4.2 DAC Examples
5. 15.5 DAC Registers
  1. 15.5.1 DAC Base Address Table
  2. 15.5.2 DAC_REGS Registers
16Comparator Subsystem (CMPSS)
1. 16.1 Introduction
2. 16.2 Comparator
3. 16.3 Reference DAC
4. 16.4 Ramp Generator
5. 16.5 Digital Filter
  1. 16.5.1 Filter Initialization Sequence
6. 16.6 Using the CMPSS
7. 16.7 CMPSS DAC Output
8. 16.8 Software
  1. 16.8.1 CMPSS Registers to Driverlib Functions
  2. 16.8.2 CMPSS Examples
    1. 16.8.2.1 CMPSS Asynchronous Trip
    2. 16.8.2.2 CMPSS Digital Filter Configuration
9. 16.9 CMPSS Registers
  1. 16.9.1 CMPSS Base Address Table
  2. 16.9.2 CMPSS_REGS Registers
17Programmable Gain Amplifier (PGA)
1. 17.1 Programmable Gain Amplifier (PGA) Overview
  1. 17.1.1 Features
  2. 17.1.2 Block Diagram
2. 17.2 Linear Output Range
3. 17.3 Gain Values
4. 17.4 Modes of Operation
5. 17.5 External Filtering
  1. 17.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
  2. 17.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
6. 17.6 Error Calibration
  1. 17.6.1 Offset Error
  2. 17.6.2 Gain Error
7. 17.7 Chopping Feature
8. 17.8 Enabling and Disabling the PGA Clock
9. 17.9 Lock Register
10. 17.10 Analog Front-End Integration
11. 17.11 Examples
12. 17.12 Software
  1. 17.12.1 PGA Registers to Driverlib Functions
  2. 17.12.2 PGA Examples
    1. 17.12.2.1 PGA DAC-ADC External Loopback Example
13. 17.13 PGA Registers
  1. 17.13.1 PGA Base Address Table
  2. 17.13.2 PGA_REGS Registers
18Enhanced Pulse Width Modulator (ePWM)
1. 18.1 Introduction
  1. 18.1.1 EPWM Related Collateral
  2. 18.1.2 Submodule Overview
2. 18.2 Configuring Device Pins
3. 18.3 ePWM Modules Overview
4. 18.4 Time-Base (TB) Submodule
5. 18.5 Counter-Compare (CC) Submodule
6. 18.6 Action-Qualifier (AQ) Submodule
7. 18.7 Dead-Band Generator (DB) Submodule
8. 18.8 PWM Chopper (PC) Submodule
9. 18.9 Trip-Zone (TZ) Submodule
10. 18.10 Event-Trigger (ET) Submodule
  1. 18.10.1 Operational Overview of the ePWM Event-Trigger Submodule
11. 18.11 Digital Compare (DC) Submodule
12. 18.12 ePWM Crossbar (X-BAR)
13. 18.13 Applications to Power Topologies
14. 18.14 Register Lock Protection
15. 18.15 High-Resolution Pulse Width Modulator (HRPWM)
  1. 18.15.1 Operational Description of HRPWM
  2. 18.15.2 SFO Library Software - SFO_TI_Build_V8.lib
    1. 18.15.2.1 Scale Factor Optimizer Function - int SFO()
    2. 18.15.2.2 Software Usage
      1. 18.15.2.2.1 A Sample of How to Add "Include" Files
      2. 912
      3. 18.15.2.2.2 Declaring an Element
      4. 914
      5. 18.15.2.2.3 Initializing With a Scale Factor Value
      6. 916
      7. 18.15.2.2.4 SFO Function Calls
16. 18.16 Software
17. 18.17 EPWM Registers
  1. 18.17.1 EPWM Base Address Table
  2. 18.17.2 EPWM_REGS Registers
19Enhanced Capture (eCAP)
1. 19.1 Introduction
  1. 19.1.1 Features
  2. 19.1.2 ECAP Related Collateral
2. 19.2 Description
3. 19.3 Configuring Device Pins for the eCAP
4. 19.4 Capture and APWM Operating Mode
5. 19.5 Capture Mode Description
6. 19.6 Application of the eCAP Module
7. 19.7 Application of the APWM Mode
  1. 19.7.1 Example 1 - Simple PWM Generation (Independent Channels)
8. 19.8 Software
  1. 19.8.1 ECAP Registers to Driverlib Functions
  2. 19.8.2 ECAP Examples
9. 19.9 ECAP Registers
  1. 19.9.1 ECAP Base Address Table
  2. 19.9.2 ECAP_REGS Registers
20Enhanced Quadrature Encoder Pulse (eQEP)
1. 20.1 Introduction
  1. 20.1.1 EQEP Related Collateral
2. 20.2 Configuring Device Pins
3. 20.3 Description
4. 20.4 Quadrature Decoder Unit (QDU)
5. 20.5 Position Counter and Control Unit (PCCU)
6. 20.6 eQEP Edge Capture Unit
7. 20.7 eQEP Watchdog
8. 20.8 eQEP Unit Timer Base
9. 20.9 QMA Module
  1. 20.9.1 Modes of Operation
    1. 20.9.1.1 QMA Mode-1 (QMACTRL[MODE]=1)
    2. 20.9.1.2 QMA Mode-2 (QMACTRL[MODE]=2)
  2. 20.9.2 Interrupt and Error Generation
10. 20.10 eQEP Interrupt Structure
11. 20.11 Software
  1. 20.11.1 EQEP Registers to Driverlib Functions
  2. 20.11.2 EQEP Examples
12. 20.12 EQEP Registers
  1. 20.12.1 EQEP Base Address Table
  2. 20.12.2 EQEP_REGS Registers
21Serial Peripheral Interface (SPI)
1. 21.1 Introduction
2. 21.2 System-Level Integration
3. 21.3 SPI Operation
4. 21.4 Programming Procedure
5. 21.5 Software
  1. 21.5.1 SPI Registers to Driverlib Functions
  2. 21.5.2 SPI Examples
6. 21.6 SPI Registers
  1. 21.6.1 SPI Base Address Table
  2. 21.6.2 SPI_REGS Registers
22Serial Communications Interface (SCI)
1. 22.1 Introduction
2. 22.2 Architecture
3. 22.3 SCI Module Signal Summary
4. 22.4 Configuring Device Pins
5. 22.5 Multiprocessor and Asynchronous Communication Modes
6. 22.6 SCI Programmable Data Format
7. 22.7 SCI Multiprocessor Communication
8. 22.8 Idle-Line Multiprocessor Mode
9. 22.9 Address-Bit Multiprocessor Mode
  1. 22.9.1 Sending an Address
10. 22.10 SCI Communication Format
  1. 22.10.1 Receiver Signals in Communication Modes
  2. 22.10.2 Transmitter Signals in Communication Modes
11. 22.11 SCI Port Interrupts
  1. 22.11.1 Break Detect
12. 22.12 SCI Baud Rate Calculations
13. 22.13 SCI Enhanced Features
14. 22.14 Software
  1. 22.14.1 SCI Registers to Driverlib Functions
  2. 22.14.2 SCI Examples
15. 22.15 SCI Registers
  1. 22.15.1 SCI Base Address Table
  2. 22.15.2 SCI_REGS Registers
23Universal Serial Bus (USB) Controller
1. 23.1 Introduction
2. 23.2 Functional Description
3. 23.3 Initialization and Configuration
  1. 23.3.1 Pin Configuration
  2. 23.3.2 Endpoint Configuration
4. 23.4 USB Global Interrupts
5. 23.5 Software
  1. 23.5.1 USB Examples
6. 23.6 USB Registers
  1. 23.6.1 USB Base Address Table
  2. 23.6.2 USB_REGS Registers
24Fast Serial Interface (FSI)
1. 24.1 Introduction
  1. 24.1.1 FSI Related Collateral
  2. 24.1.2 FSI Features
2. 24.2 System-level Integration
3. 24.3 FSI Functional Description
4. 24.4 FSI Programing Guide
5. 24.5 Software
  1. 24.5.1 FSI Registers to Driverlib Functions
  2. 24.5.2 FSI Examples
6. 24.6 FSI Registers
25Inter-Integrated Circuit Module (I2C)
1. 25.1 Introduction
2. 25.2 Configuring Device Pins
3. 25.3 I2C Module Operational Details
4. 25.4 Interrupt Requests Generated by the I2C Module
  1. 25.4.1 Basic I2C Interrupt Requests
  2. 25.4.2 I2C FIFO Interrupts
5. 25.5 Resetting or Disabling the I2C Module
6. 25.6 Software
  1. 25.6.1 I2C Registers to Driverlib Functions
  2. 25.6.2 I2C Examples
7. 25.7 I2C Registers
  1. 25.7.1 I2C Base Address Table
  2. 25.7.2 I2C_REGS Registers
26Power Management Bus Module (PMBus)
1. 26.1 Introduction
2. 26.2 Configuring Device Pins
3. 26.3 Target Mode Operation
  1. 26.3.1 Configuration
  2. 26.3.2 Message Handling
4. 26.4 Controller Mode Operation
  1. 26.4.1 Configuration
  2. 26.4.2 Message Handling
5. 26.5 Software
  1. 26.5.1 PMBUS Registers to Driverlib Functions
6. 26.6 PMBUS Registers
  1. 26.6.1 PMBUS Base Address Table
  2. 26.6.2 PMBUS_REGS Registers
27Modular Controller Area Network (MCAN)
1. 27.1 MCAN Introduction
  1. 27.1.1 MCAN Related Collateral
  2. 27.1.2 MCAN Features
2. 27.2 MCAN Environment
3. 27.3 CAN Network Basics
4. 27.4 MCAN Integration
5. 27.5 MCAN Functional Description
6. 27.6 Software
  1. 27.6.1 MCAN Registers to Driverlib Functions
  2. 27.6.2 MCAN Examples
7. 27.7 MCAN Registers
28Local Interconnect Network (LIN)
1. 28.1 Introduction
2. 28.2 Serial Communications Interface Module
3. 28.3 Local Interconnect Network Module
4. 28.4 Low-Power Mode
5. 28.5 Emulation Mode
6. 28.6 Software
  1. 28.6.1 LIN Registers to Driverlib Functions
  2. 28.6.2 LIN Examples
7. 28.7 LIN Registers
  1. 28.7.1 LIN Base Address Table
  2. 28.7.2 LIN_REGS Registers
29Configurable Logic Block (CLB)
1. 29.1 Introduction
  1. 29.1.1 CLB Related Collateral
2. 29.2 Description
  1. 29.2.1 CLB Clock
3. 29.3 CLB Input/Output Connection
4. 29.4 CLB Tile
5. 29.5 CPU Interface
  1. 29.5.1 Register Description
  2. 29.5.2 Non-Memory Mapped Registers
6. 29.6 DMA Access
7. 29.7 CLB Data Export Through SPI RX Buffer
8. 29.8 Software
9. 29.9 CLB Registers
30Advanced Encryption Standard (AES) Accelerator
1. 30.1 Introduction
  1. 30.1.1 AES Block Diagram
  2. 30.1.2 AES Algorithm
2. 30.2 AES Operating Modes
3. 30.3 Extended and Combined Modes of Operations
4. 30.4 AES Module Programming Guide
  1. 30.4.1 AES Low-Level Programming Models
5. 30.5 Software
6. 30.6 AES Registers
31Embedded Pattern Generator (EPG)
1. 31.1 Introduction
2. 31.2 Clock Generator Modules
  1. 31.2.1 DCLK (50% duty cycle clock)
  2. 31.2.2 Clock Stop
3. 31.3 Signal Generator Module
4. 31.4 EPG Peripheral Signal Mux Selection
5. 31.5 Application Software Notes
6. 31.6 EPG Example Use Cases
7. 31.7 EPG Interrupt
8. 31.8 Software
  1. 31.8.1 EPG Registers to Driverlib Functions
  2. 31.8.2 EPG Examples
9. 31.9 EPG Registers
32Revision History

14.14.3 ADC_REGS Registers

Table 14-60 lists the memory-mapped registers for the ADC_REGS registers. All register offset addresses not listed in Table 14-60 should be considered as reserved locations and the register contents should not be modified.

Table 14-60 ADC_REGS Registers

Offset	Acronym	Register Name	Write Protection	Section
0h	ADCCTL1	ADC Control 1 Register	EALLOW	Go
1h	ADCCTL2	ADC Control 2 Register	EALLOW	Go
6h	ADCBURSTCTL	ADC Burst Control Register	EALLOW	Go
7h	ADCINTFLG	ADC Interrupt Flag Register		Go
8h	ADCINTFLGCLR	ADC Interrupt Flag Clear Register		Go
9h	ADCINTOVF	ADC Interrupt Overflow Register		Go
Ah	ADCINTOVFCLR	ADC Interrupt Overflow Clear Register		Go
Bh	ADCINTSEL1N2	ADC Interrupt 1 and 2 Selection Register	EALLOW	Go
Ch	ADCINTSEL3N4	ADC Interrupt 3 and 4 Selection Register	EALLOW	Go
Dh	ADCSOCPRICTL	ADC SOC Priority Control Register	EALLOW	Go
Eh	ADCINTSOCSEL1	ADC Interrupt SOC Selection 1 Register	EALLOW	Go
12h	ADCSOCFLG1	ADC SOC Flag 1 Register		Go
14h	ADCSOCFRC1	ADC SOC Force 1 Register		Go
16h	ADCSOCOVF1	ADC SOC Overflow 1 Register		Go
18h	ADCSOCOVFCLR1	ADC SOC Overflow Clear 1 Register		Go
1Ah	ADCSOC0CTL	ADC SOC0 Control Register	EALLOW	Go
1Ch	ADCSOC1CTL	ADC SOC1 Control Register	EALLOW	Go
1Eh	ADCSOC2CTL	ADC SOC2 Control Register	EALLOW	Go
20h	ADCSOC3CTL	ADC SOC3 Control Register	EALLOW	Go
22h	ADCSOC4CTL	ADC SOC4 Control Register	EALLOW	Go
24h	ADCSOC5CTL	ADC SOC5 Control Register	EALLOW	Go
26h	ADCSOC6CTL	ADC SOC6 Control Register	EALLOW	Go
28h	ADCSOC7CTL	ADC SOC7 Control Register	EALLOW	Go
2Ah	ADCSOC8CTL	ADC SOC8 Control Register	EALLOW	Go
2Ch	ADCSOC9CTL	ADC SOC9 Control Register	EALLOW	Go
2Eh	ADCSOC10CTL	ADC SOC10 Control Register	EALLOW	Go
30h	ADCSOC11CTL	ADC SOC11 Control Register	EALLOW	Go
32h	ADCSOC12CTL	ADC SOC12 Control Register	EALLOW	Go
34h	ADCSOC13CTL	ADC SOC13 Control Register	EALLOW	Go
36h	ADCSOC14CTL	ADC SOC14 Control Register	EALLOW	Go
38h	ADCSOC15CTL	ADC SOC15 Control Register	EALLOW	Go
5Ah	ADCEVTSTAT	ADC Event Status Register		Go
5Ch	ADCEVTCLR	ADC Event Clear Register		Go
5Eh	ADCEVTSEL	ADC Event Selection Register	EALLOW	Go
60h	ADCEVTINTSEL	ADC Event Interrupt Selection Register	EALLOW	Go
63h	ADCCOUNTER	ADC Counter Register		Go
64h	ADCREV	ADC Revision Register		Go
65h	ADCOFFTRIM	ADC Offset Trim Register	EALLOW	Go
66h	ADCCONFIG2	ADC Config Register Upper 32 bits	EALLOW	Go
6Ah	ADCPPB1CONFIG	ADC PPB{#} Config Register	EALLOW	Go
6Bh	ADCPPB1STAMP	ADC PPB1 Sample Delay Time Stamp Register		Go
6Ch	ADCPPB1OFFCAL	ADC PPB1 Offset Calibration Register	EALLOW	Go
6Dh	ADCPPB1OFFREF	ADC PPB1 Offset Reference Register		Go
6Eh	ADCPPB1TRIPHI	ADC PPB1 Trip High Register	EALLOW	Go
70h	ADCPPB1TRIPLO	ADC PPB1 Trip Low/Trigger Time Stamp Register	EALLOW	Go
72h	ADCPPBTRIP1FILCTL	ADCEVT1 Trip High Filter Control Register	EALLOW	Go
74h	ADCPPBTRIP1FILCLKCTL	ADCEVT1 Trip High Filter Prescale Control Register	EALLOW	Go
7Ah	ADCPPB2CONFIG	ADC PPB{#} Config Register	EALLOW	Go
7Bh	ADCPPB2STAMP	ADC PPB2 Sample Delay Time Stamp Register		Go
7Ch	ADCPPB2OFFCAL	ADC PPB2 Offset Calibration Register	EALLOW	Go
7Dh	ADCPPB2OFFREF	ADC PPB2 Offset Reference Register		Go
7Eh	ADCPPB2TRIPHI	ADC PPB2 Trip High Register	EALLOW	Go
80h	ADCPPB2TRIPLO	ADC PPB2 Trip Low/Trigger Time Stamp Register	EALLOW	Go
82h	ADCPPBTRIP2FILCTL	ADCEVT2 Trip High Filter Control Register	EALLOW	Go
84h	ADCPPBTRIP2FILCLKCTL	ADCEVT2 Trip High Filter Prescale Control Register	EALLOW	Go
8Ah	ADCPPB3CONFIG	ADC PPB{#} Config Register	EALLOW	Go
8Bh	ADCPPB3STAMP	ADC PPB3 Sample Delay Time Stamp Register		Go
8Ch	ADCPPB3OFFCAL	ADC PPB3 Offset Calibration Register	EALLOW	Go
8Dh	ADCPPB3OFFREF	ADC PPB3 Offset Reference Register		Go
8Eh	ADCPPB3TRIPHI	ADC PPB3 Trip High Register	EALLOW	Go
90h	ADCPPB3TRIPLO	ADC PPB3 Trip Low/Trigger Time Stamp Register	EALLOW	Go
92h	ADCPPBTRIP3FILCTL	ADCEVT3 Trip High Filter Control Register	EALLOW	Go
94h	ADCPPBTRIP3FILCLKCTL	ADCEVT3 Trip High Filter Prescale Control Register	EALLOW	Go
9Ah	ADCPPB4CONFIG	ADC PPB{#} Config Register	EALLOW	Go
9Bh	ADCPPB4STAMP	ADC PPB4 Sample Delay Time Stamp Register		Go
9Ch	ADCPPB4OFFCAL	ADC PPB4 Offset Calibration Register	EALLOW	Go
9Dh	ADCPPB4OFFREF	ADC PPB4 Offset Reference Register		Go
9Eh	ADCPPB4TRIPHI	ADC PPB4 Trip High Register	EALLOW	Go
A0h	ADCPPB4TRIPLO	ADC PPB4 Trip Low/Trigger Time Stamp Register	EALLOW	Go
A2h	ADCPPBTRIP4FILCTL	ADCEVT4 Trip High Filter Control Register	EALLOW	Go
A4h	ADCPPBTRIP4FILCLKCTL	ADCEVT4 Trip High Filter Prescale Control Register	EALLOW	Go
B9h	ADCINTCYCLE	ADC Early Interrupt Generation Cycle	EALLOW	Go
BAh	ADCINLTRIM1	ADC Linearity Trim 1 Register	EALLOW	Go
BCh	ADCINLTRIM2	ADC Linearity Trim 2 Register	EALLOW	Go
BEh	ADCINLTRIM3	ADC Linearity Trim 3 Register	EALLOW	Go
C0h	ADCINLTRIM4	ADC Linearity Trim 4 Register	EALLOW	Go
C2h	ADCINLTRIM5	ADC Linearity Trim 5 Register	EALLOW	Go
C4h	ADCINLTRIM6	ADC Linearity Trim 6 Register	EALLOW	Go
C7h	ADCREV2	ADC Wrapper Revision Register		Go
CAh	REP1CTL	ADC Trigger Repeater 1 Control Register	EALLOW	Go
CCh	REP1N	ADC Trigger Repeater 1 N Select Register	EALLOW	Go
CEh	REP1PHASE	ADC Trigger Repeater 1 Phase Select Register	EALLOW	Go
D0h	REP1SPREAD	ADC Trigger Repeater 1 Spread Select Register	EALLOW	Go
D2h	REP1FRC	ADC Trigger Repeater 1 Software Force Register	EALLOW	Go
DAh	REP2CTL	ADC Trigger Repeater 2 Control Register	EALLOW	Go
DCh	REP2N	ADC Trigger Repeater 2 N Select Register	EALLOW	Go
DEh	REP2PHASE	ADC Trigger Repeater 2 Phase Select Register	EALLOW	Go
E0h	REP2SPREAD	ADC Trigger Repeater 2 Spread Select Register	EALLOW	Go
E2h	REP2FRC	ADC Trigger Repeater 2 Software Force Register	EALLOW	Go
EAh	ADCPPB1LIMIT	ADC PPB1Conversion Count Limit Register	EALLOW	Go
ECh	ADCPPBP1PCOUNT	ADC PPB1 Partial Conversion Count Register		Go
EEh	ADCPPB1CONFIG2	ADC PPB1 Sum Shift Register		Go
F0h	ADCPPB1PSUM	ADC PPB1 Partial Sum Register		Go
F2h	ADCPPB1PMAX	ADC PPB1 Partial Max Register		Go
F4h	ADCPPB1PMAXI	ADC PPB1 Partial Max Index Register		Go
F6h	ADCPPB1PMIN	ADC PPB1 Partial MIN Register		Go
F8h	ADCPPB1PMINI	ADC PPB1 Partial Min Index Register		Go
FAh	ADCPPB1TRIPLO2	ADC PPB1 Extended Trip Low Register		Go
104h	ADCPPB2LIMIT	ADC PPB2Conversion Count Limit Register	EALLOW	Go
106h	ADCPPBP2PCOUNT	ADC PPB2 Partial Conversion Count Register		Go
108h	ADCPPB2CONFIG2	ADC PPB2 Sum Shift Register		Go
10Ah	ADCPPB2PSUM	ADC PPB2 Partial Sum Register		Go
10Ch	ADCPPB2PMAX	ADC PPB2 Partial Max Register		Go
10Eh	ADCPPB2PMAXI	ADC PPB2 Partial Max Index Register		Go
110h	ADCPPB2PMIN	ADC PPB2 Partial MIN Register		Go
112h	ADCPPB2PMINI	ADC PPB2 Partial Min Index Register		Go
114h	ADCPPB2TRIPLO2	ADC PPB2 Extended Trip Low Register		Go
11Eh	ADCPPB3LIMIT	ADC PPB3Conversion Count Limit Register	EALLOW	Go
120h	ADCPPBP3PCOUNT	ADC PPB3 Partial Conversion Count Register		Go
122h	ADCPPB3CONFIG2	ADC PPB3 Sum Shift Register		Go
124h	ADCPPB3PSUM	ADC PPB3 Partial Sum Register		Go
126h	ADCPPB3PMAX	ADC PPB3 Partial Max Register		Go
128h	ADCPPB3PMAXI	ADC PPB3 Partial Max Index Register		Go
12Ah	ADCPPB3PMIN	ADC PPB3 Partial MIN Register		Go
12Ch	ADCPPB3PMINI	ADC PPB3 Partial Min Index Register		Go
12Eh	ADCPPB3TRIPLO2	ADC PPB3 Extended Trip Low Register		Go
138h	ADCPPB4LIMIT	ADC PPB4Conversion Count Limit Register	EALLOW	Go
13Ah	ADCPPBP4PCOUNT	ADC PPB4 Partial Conversion Count Register		Go
13Ch	ADCPPB4CONFIG2	ADC PPB4 Sum Shift Register		Go
13Eh	ADCPPB4PSUM	ADC PPB4 Partial Sum Register		Go
140h	ADCPPB4PMAX	ADC PPB4 Partial Max Register		Go
142h	ADCPPB4PMAXI	ADC PPB4 Partial Max Index Register		Go
144h	ADCPPB4PMIN	ADC PPB4 Partial MIN Register		Go
146h	ADCPPB4PMINI	ADC PPB4 Partial Min Index Register		Go
148h	ADCPPB4TRIPLO2	ADC PPB4 Extended Trip Low Register		Go

Complex bit access types are encoded to fit into small table cells. Table 14-61 shows the codes that are used for access types in this section.

Table 14-61 ADC_REGS Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
R-0	R -0	Read Returns 0s
Write Type
W	W	Write
W1C	W 1C	Write 1 to clear
W1S	W 1S	Write 1 to set
Reset or Default Value
-n		Value after reset or the default value
Register Array Variables
i,j,k,l,m,n		When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
y		When this variable is used in a register name, an offset, or an address it refers to the value of a register array.

14.14.3.1 ADCCTL1 Register (Offset = 0h) [Reset = 0000h]

ADCCTL1 is shown in Figure 14-79 and described in Table 14-62.

Return to the Summary Table.

ADC Control 1 Register

Figure 14-79 ADCCTL1 Register

15	14	13	12	11	10	9	8
TDMAEN	EXTMUXPRESELECTEN	ADCBSY	RESERVED	ADCBSYCHN
R/W-0h	R/W-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
ADCPWDNZ	RESERVED				INTPULSEPOS	RESERVED
R/W-0h	R-0h				R/W-0h	R-0h

Table 14-62 ADCCTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	TDMAEN	R/W	0h	Enable Alternate DMA Timings. This bit controls when the DMA is triggered. 0 DMA is triggered at the same time as the CPU interrupt 1 DMA is always triggered at tDMA regardless or whether the ADC is in early interrupt mode or late interrupt mode Reset type: SYSRSn
14	EXTMUXPRESELECTEN	R/W	0h	If th the ADC SOC sequence is deterministic, the ADCEXTMUX pins can be set earlier: at the end of the S+H window of the previous conversion instead of the beginning of the S+H window of the current conversion. This allows some of the external mux settling time to be pipelined with the previous conversion's conversion time. However, this will not work in the case where high-priority SOCs can arrive asynchronously. 0 ADCEXTMUX pins only change at beginning of S+H window 1 ADCEXTMUX pins are set after the end of S+H window based on pending SOCs Reset type: SYSRSn
13	ADCBSY	R	0h	ADC Busy. Set when ADC SOC is generated, cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy and cannot sample another channel Reset type: SYSRSn
12	RESERVED	R	0h	Reserved
11-8	ADCBSYCHN	R	0h	ADC Busy Channel. Set when an ADC Start of Conversion (SOC) is generated. When ADCBSY=0: holds the value of the last converted SOC When ADCBSY=1: reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC converted 1h SOC1 is currently processing or was last SOC converted 2h SOC2 is currently processing or was last SOC converted 3h SOC3 is currently processing or was last SOC converted 4h SOC4 is currently processing or was last SOC converted 5h SOC5 is currently processing or was last SOC converted 6h SOC6 is currently processing or was last SOC converted 7h SOC7 is currently processing or was last SOC converted 8h SOC8 is currently processing or was last SOC converted 9h SOC9 is currently processing or was last SOC converted Ah SOC10 is currently processing or was last SOC converted Bh SOC11 is currently processing or was last SOC converted Ch SOC12 is currently processing or was last SOC converted Dh SOC13 is currently processing or was last SOC converted Eh SOC14 is currently processing or was last SOC converted Fh SOC15 is currently processing or was last SOC converted Reset type: SYSRSn
7	ADCPWDNZ	R/W	0h	ADC Power Down (active low). This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up Reset type: SYSRSn
6-3	RESERVED	R	0h	Reserved
2	INTPULSEPOS	R/W	0h	ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion (at the end of the acquisition window) plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse generation occurs at the end of the conversion, 1 cycle prior to the ADC result latching into its result register Reset type: SYSRSn
1-0	RESERVED	R	0h	Reserved

14.14.3.2 ADCCTL2 Register (Offset = 1h) [Reset = 0000h]

ADCCTL2 is shown in Figure 14-80 and described in Table 14-63.

Return to the Summary Table.

ADC Control 2 Register

Figure 14-80 ADCCTL2 Register

15	14	13	12	11	10	9	8
RESERVED			RESERVED				RESERVED
R-0h			R/W-0h				R-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED		PRESCALE
R/W-0h	R/W-0h	R-0h		R/W-0h

Table 14-63 ADCCTL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12-9	RESERVED	R/W	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5-4	RESERVED	R	0h	Reserved
3-0	PRESCALE	R/W	0h	ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 ADCCLK = Input Clock / 1.5 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock / 4.0 0111 ADCCLK = Input Clock / 4.5 1000 ADCCLK = Input Clock / 5.0 1001 ADCCLK = Input Clock / 5.5 1010 ADCCLK = Input Clock / 6.0 1011 ADCCLK = Input Clock / 6.5 1100 ADCCLK = Input Clock / 7.0 1101 ADCCLK = Input Clock / 7.5 1110 ADCCLK = Input Clock / 8.0 1111 ADCCLK = Input Clock / 8.5 Reset type: SYSRSn

14.14.3.3 ADCBURSTCTL Register (Offset = 6h) [Reset = 0000h]

ADCBURSTCTL is shown in Figure 14-81 and described in Table 14-64.

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ADC Burst Control Register

Figure 14-81 ADCBURSTCTL Register

15	14	13	12	11	10	9	8
BURSTEN	RESERVED			BURSTSIZE
R/W-0h	R-0h			R/W-0h

7	6	5	4	3	2	1	0
RESERVED	BURSTTRIGSEL
R-0h	R/W-0h

Table 14-64 ADCBURSTCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	BURSTEN	R/W	0h	SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled. Reset type: SYSRSn
14-12	RESERVED	R	0h	Reserved
11-8	BURSTSIZE	R/W	0h	SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer, which is advanced as each SOC is converted. 0h 1 SOC converted 1h 2 SOCs converted 2h 3 SOCs converted 3h 4 SOCs converted 4h 5 SOCs converted 5h 6 SOCs converted 6h 7 SOCs converted 7h 8 SOCs converted 8h 9 SOCs converted 9h 10 SOCs converted Ah 11 SOCs converted Bh 12 SOCs converted Ch 13 SOCs converted Dh 14 SOCs converted Eh 15 SOCs converted Fh 16 SOCs converted Note: If the burst causes SOCs to be set for conversion that were already pending, the corresponding bits in the ADCSOCOVF register will be set. Reset type: SYSRSn
7	RESERVED	R	0h	Reserved
6-0	BURSTTRIGSEL	R/W	0h	SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h BURSTTRIG0 - Software only 01h BURSTTRIG1 - CPU1 Timer 0, TINT0n 02h BURSTTRIG2 - CPU1 Timer 1, TINT1n 03h BURSTTRIG3 - CPU1 Timer 2, TINT2n 04h BURSTTRIG4 - GPIO, Input X-Bar INPUT5 05h BURSTTRIG5 - ePWM1, ADCSOCA 06h BURSTTRIG6 - ePWM1, ADCSOCB 07h BURSTTRIG7 - ePWM2, ADCSOCA 08h BURSTTRIG8 - ePWM2, ADCSOCB 09h BURSTTRIG9 - ePWM3, ADCSOCA 0Ah BURSTTRIG10 - ePWM3, ADCSOCB 0Bh BURSTTRIG11 - ePWM4, ADCSOCA 0Ch BURSTTRIG12 - ePWM4, ADCSOCB 0Dh BURSTTRIG13 - ePWM5, ADCSOCA 0Eh BURSTTRIG14 - ePWM5, ADCSOCB 0Fh BURSTTRIG15 - ePWM6, ADCSOCA 10h BURSTTRIG16 - ePWM6, ADCSOCB 11h BURSTTRIG17 - ePWM7, ADCSOCA 12h BURSTTRIG18 - ePWM7, ADCSOCB 13h BURSTTRIG19 - ePWM8, ADCSOCA 14h BURSTTRIG20 - ePWM8, ADCSOCB 15h BURSTTRIG21 - ePWM9, ADCSOCA 16h BURSTTRIG22 - ePWM9, ADCSOCB 17h BURSTTRIG23 - ePWM10, ADCSOCA 18h BURSTTRIG24 - ePWM10, ADCSOCB 19h BURSTTRIG25 - ePWM11, ADCSOCA 1Ah BURSTTRIG26 - ePWM11, ADCSOCB 1Bh BURSTTRIG27 - ePWM12, ADCSOCA 1Ch BURSTTRIG28 - ePWM12, ADCSOCB 1Dh BURSTTRIG29 - CPU2 Timer 0, TINT0n 1Eh BURSTTRIG30 - CPU2 Timer 1, TINT1n 1Fh BURSTTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h BURSTTRIG40 - REP1TRIG 29h BURSTTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h BURSTTRIG80 eCAP1 51h BURSTTRIG81 eCAP2 52h BURSTTRIG82 eCAP3 53h BURSTTRIG83 eCAP4 54h BURSTTRIG84 eCAP5 55h BURSTTRIG85 eCAP6 56h BURSTTRIG86 eCAP7 57h BURSTTRIG87 eCAP8 58h BURSTTRIG88 - ePWM13, ADCSOCA 59h BURSTTRIG89 - ePWM13, ADCSOCB 5Ah BURSTTRIG90 - ePWM14, ADCSOCA 5Bh BURSTTRIG91 - ePWM14, ADCSOCB 5Ch BURSTTRIG92 - ePWM15, ADCSOCA 5Dh BURSTTRIG93 - ePWM15, ADCSOCB 5Eh BURSTTRIG94 - ePWM16, ADCSOCA 5Fh BURSTTRIG95 - ePWM16, ADCSOCB 60h BURSTTRIG96 - ePWM17, ADCSOCA 61h BURSTTRIG97 - ePWM17, ADCSOCB 62h BURSTTRIG98 - ePWM18, ADCSOCA 63h BURSTTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn

14.14.3.4 ADCINTFLG Register (Offset = 7h) [Reset = 0000h]

ADCINTFLG is shown in Figure 14-82 and described in Table 14-65.

Return to the Summary Table.

ADC Interrupt Flag Register

Figure 14-82 ADCINTFLG Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
ADCINT4RESULT	ADCINT3RESULT	ADCINT2RESULT	ADCINT1RESULT	ADCINT4	ADCINT3	ADCINT2	ADCINT1
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 14-65 ADCINTFLG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7	ADCINT4RESULT	R	0h	ADC Interrupt 4 Results Ready Flag. This flag is set when the conversions results associated with ADCINT4 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register. This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT4 flag. In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the PIE. In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch. Reset type: SYSRSn
6	ADCINT3RESULT	R	0h	ADC Interrupt 3 Results Ready Flag. This flag is set when the conversions results associated with ADCINT3 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register. This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT3 flag. In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the PIE. In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch. Reset type: SYSRSn
5	ADCINT2RESULT	R	0h	ADC Interrupt 2 Results Ready Flag. This flag is set when the conversions results associated with ADCINT2 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register. This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT2 flag. In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the PIE. In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch. Reset type: SYSRSn
4	ADCINT1RESULT	R	0h	ADC Interrupt 1 Results Ready Flag. This flag is set when the conversions results associated with ADCINT1 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register. This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT1 flag. In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the PIE. In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch. Reset type: SYSRSn
3	ADCINT4	R	0h	ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (INTSELxNy register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn
2	ADCINT3	R	0h	ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (INTSELxNy register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn
1	ADCINT2	R	0h	ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (INTSELxNy register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn
0	ADCINT1	R	0h	ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (INTSELxNy register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn

14.14.3.5 ADCINTFLGCLR Register (Offset = 8h) [Reset = 0000h]

ADCINTFLGCLR is shown in Figure 14-83 and described in Table 14-66.

Return to the Summary Table.

ADC Interrupt Flag Clear Register

Figure 14-83 ADCINTFLGCLR Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				ADCINT4	ADCINT3	ADCINT2	ADCINT1
R-0h				R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h

Table 14-66 ADCINTFLGCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	RESERVED	R	0h	Reserved
3	ADCINT4	R-0/W1C	0h	ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT4 and ADCINT4RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn
2	ADCINT3	R-0/W1C	0h	ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT3 and ADCINT3RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn
1	ADCINT2	R-0/W1C	0h	ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT2 and ADCINT2RESULT flags in the ADCINTFLG register. . If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn
0	ADCINT1	R-0/W1C	0h	ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT1 and ADCINT1RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn

14.14.3.6 ADCINTOVF Register (Offset = 9h) [Reset = 0000h]

ADCINTOVF is shown in Figure 14-84 and described in Table 14-67.

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ADC Interrupt Overflow Register

Figure 14-84 ADCINTOVF Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				ADCINT4	ADCINT3	ADCINT2	ADCINT1
R-0h				R-0h	R-0h	R-0h	R-0h

Table 14-67 ADCINTOVF Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	RESERVED	R	0h	Reserved
3	ADCINT4	R	0h	ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn
2	ADCINT3	R	0h	ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn
1	ADCINT2	R	0h	ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn
0	ADCINT1	R	0h	ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn

14.14.3.7 ADCINTOVFCLR Register (Offset = Ah) [Reset = 0000h]

ADCINTOVFCLR is shown in Figure 14-85 and described in Table 14-68.

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ADC Interrupt Overflow Clear Register

Figure 14-85 ADCINTOVFCLR Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				ADCINT4	ADCINT3	ADCINT2	ADCINT1
R-0h				R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h	R-0/W1C-0h

Table 14-68 ADCINTOVFCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	RESERVED	R	0h	Reserved
3	ADCINT4	R-0/W1C	0h	ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn
2	ADCINT3	R-0/W1C	0h	ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn
1	ADCINT2	R-0/W1C	0h	ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn
0	ADCINT1	R-0/W1C	0h	ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn

14.14.3.8 ADCINTSEL1N2 Register (Offset = Bh) [Reset = 0000h]

ADCINTSEL1N2 is shown in Figure 14-86 and described in Table 14-69.

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ADC Interrupt 1 and 2 Selection Register

Figure 14-86 ADCINTSEL1N2 Register

15	14	13	12	11	10	9	8
INT2E	INT2CONT	INT2SEL
R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
INT1E	INT1CONT	INT1SEL
R/W-0h	R/W-0h	R/W-0h

Table 14-69 ADCINTSEL1N2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	INT2E	R/W	0h	ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled Reset type: SYSRSn
14	INT2CONT	R/W	0h	ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn
13-8	INT2SEL	R/W	0h	ADCINT2 EOC Source Select 00h EOC0 is trigger for ADCINT2 01h EOC1 is trigger for ADCINT2 02h EOC2 is trigger for ADCINT2 03h EOC3 is trigger for ADCINT2 04h EOC4 is trigger for ADCINT2 05h EOC5 is trigger for ADCINT2 06h EOC6 is trigger for ADCINT2 07h EOC7 is trigger for ADCINT2 08h EOC8 is trigger for ADCINT2 09h EOC9 is trigger for ADCINT2 0Ah EOC10 is trigger for ADCINT2 0Bh EOC11 is trigger for ADCINT2 0Ch EOC12 is trigger for ADCINT2 0Dh EOC13 is trigger for ADCINT2 0Eh EOC14 is trigger for ADCINT2 0Fh EOC15 is trigger for ADCINT2 10h - 1Fh Reserved 20h OSINT1 is trigger for ADCINT2 21h OSINT2 is trigger for ADCINT2 22h OSINT3 is trigger for ADCINT2 23h OSINT4 is trigger for ADCINT2 Reset type: SYSRSn
7	INT1E	R/W	0h	ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled Reset type: SYSRSn
6	INT1CONT	R/W	0h	ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn
5-0	INT1SEL	R/W	0h	ADCINT1 EOC Source Select 00h EOC0 is trigger for ADCINT1 01h EOC1 is trigger for ADCINT1 02h EOC2 is trigger for ADCINT1 03h EOC3 is trigger for ADCINT1 04h EOC4 is trigger for ADCINT1 05h EOC5 is trigger for ADCINT1 06h EOC6 is trigger for ADCINT1 07h EOC7 is trigger for ADCINT1 08h EOC8 is trigger for ADCINT1 09h EOC9 is trigger for ADCINT1 0Ah EOC10 is trigger for ADCINT1 0Bh EOC11 is trigger for ADCINT1 0Ch EOC12 is trigger for ADCINT1 0Dh EOC13 is trigger for ADCINT1 0Eh EOC14 is trigger for ADCINT1 0Fh EOC15 is trigger for ADCINT1 10h - 1Fh Reserved 20h OSINT1 is trigger for ADCINT1 21h OSINT2 is trigger for ADCINT1 22h OSINT3 is trigger for ADCINT1 23h OSINT4 is trigger for ADCINT1 Reset type: SYSRSn

14.14.3.9 ADCINTSEL3N4 Register (Offset = Ch) [Reset = 0000h]

ADCINTSEL3N4 is shown in Figure 14-87 and described in Table 14-70.

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ADC Interrupt 3 and 4 Selection Register

Figure 14-87 ADCINTSEL3N4 Register

15	14	13	12	11	10	9	8
INT4E	INT4CONT	INT4SEL
R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
INT3E	INT3CONT	INT3SEL
R/W-0h	R/W-0h	R/W-0h

Table 14-70 ADCINTSEL3N4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	INT4E	R/W	0h	ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled Reset type: SYSRSn
14	INT4CONT	R/W	0h	ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn
13-8	INT4SEL	R/W	0h	ADCINT4 EOC Source Select 00h EOC0 is trigger for ADCINT4 01h EOC1 is trigger for ADCINT4 02h EOC2 is trigger for ADCINT4 03h EOC3 is trigger for ADCINT4 04h EOC4 is trigger for ADCINT4 05h EOC5 is trigger for ADCINT4 06h EOC6 is trigger for ADCINT4 07h EOC7 is trigger for ADCINT4 08h EOC8 is trigger for ADCINT4 09h EOC9 is trigger for ADCINT4 0Ah EOC10 is trigger for ADCINT4 0Bh EOC11 is trigger for ADCINT4 0Ch EOC12 is trigger for ADCINT4 0Dh EOC13 is trigger for ADCINT4 0Eh EOC14 is trigger for ADCINT4 0Fh EOC15 is trigger for ADCINT4 10h - 1Fh Reserved 20h OSINT1 is trigger for ADCINT4 21h OSINT2 is trigger for ADCINT4 22h OSINT3 is trigger for ADCINT4 23h OSINT4 is trigger for ADCINT4 Reset type: SYSRSn
7	INT3E	R/W	0h	ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled Reset type: SYSRSn
6	INT3CONT	R/W	0h	ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn
5-0	INT3SEL	R/W	0h	ADCINT3 EOC Source Select 00h EOC0 is trigger for ADCINT3 01h EOC1 is trigger for ADCINT3 02h EOC2 is trigger for ADCINT3 03h EOC3 is trigger for ADCINT3 04h EOC4 is trigger for ADCINT3 05h EOC5 is trigger for ADCINT3 06h EOC6 is trigger for ADCINT3 07h EOC7 is trigger for ADCINT3 08h EOC8 is trigger for ADCINT3 09h EOC9 is trigger for ADCINT3 0Ah EOC10 is trigger for ADCINT3 0Bh EOC11 is trigger for ADCINT3 0Ch EOC12 is trigger for ADCINT3 0Dh EOC13 is trigger for ADCINT3 0Eh EOC14 is trigger for ADCINT3 0Fh EOC15 is trigger for ADCINT3 10h -1Fh Reserved 20h OSINT1 is trigger for ADCINT3 21h OSINT2 is trigger for ADCINT3 22h OSINT3 is trigger for ADCINT3 23h OSINT4 is trigger for ADCINT3 Reset type: SYSRSn

14.14.3.10 ADCSOCPRICTL Register (Offset = Dh) [Reset = 0400h]

ADCSOCPRICTL is shown in Figure 14-88 and described in Table 14-71.

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ADC SOC Priority Control Register

Figure 14-88 ADCSOCPRICTL Register

15	14	13	12	11	10	9	8
RESERVED					RRPOINTER
R-0h					R-10h

7	6	5	4	3	2	1	0
RRPOINTER		RESERVED	SOCPRIORITY
R-10h		R-0h	R/W-0h

Table 14-71 ADCSOCPRICTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10-6	RRPOINTER	R	10h	Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. 00h SOC0 was last round robin SOC to convert, SOC1 is highest round robin priority. 01h SOC1 was last round robin SOC to convert, SOC2 is highest round robin priority. 02h SOC2 was last round robin SOC to convert, SOC3 is highest round robin priority. 03h SOC3 was last round robin SOC to convert, SOC4 is highest round robin priority. 04h SOC4 was last round robin SOC to convert, SOC5 is highest round robin priority. 05h SOC5 was last round robin SOC to convert, SOC6 is highest round robin priority. 06h SOC6 was last round robin SOC to convert, SOC7 is highest round robin priority. 07h SOC7 was last round robin SOC to convert, SOC8 is highest round robin priority. 08h SOC8 was last round robin SOC to convert, SOC9 is highest round robin priority. 09h SOC9 was last round robin SOC to convert, SOC10 is highest round robin priority. 0Ah SOC10 was last round robin SOC to convert, SOC11 is highest round robin priority. 0Bh SOC11 was last round robin SOC to convert, SOC12 is highest round robin priority. 0Ch SOC12 was last round robin SOC to convert, SOC13 is highest round robin priority. 0Dh SOC13 was last round robin SOC to convert, SOC14 is highest round robin priority. 0Eh SOC14 was last round robin SOC to convert, SOC15 is highest round robin priority. 0Fh SOC15 was last round robin SOC to convert, SOC0 is highest round robin priority. 10h Reset value to indicate no SOC has been converted. SOC0 is highest round robin priority. Set to this value when the ADC module is reset by SOFTPRES or when the ADCSOCPRICTL register is written. In the latter case, if a conversion is currently in progress, it will complete and then the new priority will take effect. Others Invalid value. Reset type: SYSRSn
5	RESERVED	R	0h	Reserved
4-0	SOCPRIORITY	R/W	0h	SOC Priority Determines the cutoff point for priority mode and round robin arbitration for SOCx 00h SOC priority is handled in round robin mode for all channels. 01h SOC0 is high priority, rest of channels are in round robin mode. 02h SOC0-SOC1 are high priority, SOC2-SOC15 are in round robin mode. 03h SOC0-SOC2 are high priority, SOC3-SOC15 are in round robin mode. 04h SOC0-SOC3 are high priority, SOC4-SOC15 are in round robin mode. 05h SOC0-SOC4 are high priority, SOC5-SOC15 are in round robin mode. 06h SOC0-SOC5 are high priority, SOC6-SOC15 are in round robin mode. 07h SOC0-SOC6 are high priority, SOC7-SOC15 are in round robin mode. 08h SOC0-SOC7 are high priority, SOC8-SOC15 are in round robin mode. 09h SOC0-SOC8 are high priority, SOC9-SOC15 are in round robin mode. 0Ah SOC0-SOC9 are high priority, SOC10-SOC15 are in round robin mode. 0Bh SOC0-SOC10 are high priority, SOC11-SOC15 are in round robin mode. 0Ch SOC0-SOC11 are high priority, SOC12-SOC15 are in round robin mode. 0Dh SOC0-SOC12 are high priority, SOC13-SOC15 are in round robin mode. 0Eh SOC0-SOC13 are high priority, SOC14-SOC15 are in round robin mode. 0Fh SOC0-SOC14 are high priority, SOC15 is in round robin mode. 10h All SOCs are in high priority mode, arbitrated by SOC number. Others Invalid selection. Reset type: SYSRSn

14.14.3.11 ADCINTSOCSEL1 Register (Offset = Eh) [Reset = 00000000h]

ADCINTSOCSEL1 is shown in Figure 14-89 and described in Table 14-72.

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ADC Interrupt SOC Selection 1 Register

Figure 14-89 ADCINTSOCSEL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SOC15		SOC14		SOC13		SOC12		SOC11		SOC10		SOC9		SOC8
R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SOC7		SOC6		SOC5		SOC4		SOC3		SOC2		SOC1		SOC0
R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h

Table 14-72 ADCINTSOCSEL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SOC15	R/W	0h	SOC15 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC15. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC15. 10 ADCINT2 will trigger SOC15. 11 Invalid selection. Reset type: SYSRSn
29-28	SOC14	R/W	0h	SOC14 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC14. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC14. 10 ADCINT2 will trigger SOC14. 11 Invalid selection. Reset type: SYSRSn
27-26	SOC13	R/W	0h	SOC13 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC13. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC13. 10 ADCINT2 will trigger SOC13. 11 Invalid selection. Reset type: SYSRSn
25-24	SOC12	R/W	0h	SOC12 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC12. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC12. 10 ADCINT2 will trigger SOC12. 11 Invalid selection. Reset type: SYSRSn
23-22	SOC11	R/W	0h	SOC11 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC11. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC11. 10 ADCINT2 will trigger SOC11. 11 Invalid selection. Reset type: SYSRSn
21-20	SOC10	R/W	0h	SOC10 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC10. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC10. 10 ADCINT2 will trigger SOC10. 11 Invalid selection. Reset type: SYSRSn
19-18	SOC9	R/W	0h	SOC9 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC9. 10 ADCINT2 will trigger SOC9. 11 Invalid selection. Reset type: SYSRSn
17-16	SOC8	R/W	0h	SOC8 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC8. 10 ADCINT2 will trigger SOC8. 11 Invalid selection. Reset type: SYSRSn
15-14	SOC7	R/W	0h	SOC7 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC7. 10 ADCINT2 will trigger SOC7. 11 Invalid selection. Reset type: SYSRSn
13-12	SOC6	R/W	0h	SOC6 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC6. 10 ADCINT2 will trigger SOC6. 11 Invalid selection. Reset type: SYSRSn
11-10	SOC5	R/W	0h	SOC5 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC5. 10 ADCINT2 will trigger SOC5. 11 Invalid selection. Reset type: SYSRSn
9-8	SOC4	R/W	0h	SOC4 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC4. 10 ADCINT2 will trigger SOC4. 11 Invalid selection. Reset type: SYSRSn
7-6	SOC3	R/W	0h	SOC3 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC3. 10 ADCINT2 will trigger SOC3. 11 Invalid selection. Reset type: SYSRSn
5-4	SOC2	R/W	0h	SOC2 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC2. 10 ADCINT2 will trigger SOC2. 11 Invalid selection. Reset type: SYSRSn
3-2	SOC1	R/W	0h	SOC1 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC1. 10 ADCINT2 will trigger SOC1. 11 Invalid selection. Reset type: SYSRSn
1-0	SOC0	R/W	0h	SOC0 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC0. 10 ADCINT2 will trigger SOC0. 11 Invalid selection. Reset type: SYSRSn

14.14.3.12 ADCSOCFLG1 Register (Offset = 12h) [Reset = 0000h]

ADCSOCFLG1 is shown in Figure 14-90 and described in Table 14-73.

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ADC SOC Flag 1 Register

Figure 14-90 ADCSOCFLG1 Register

15	14	13	12	11	10	9	8
SOC15	SOC14	SOC13	SOC12	SOC11	SOC10	SOC9	SOC8
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
SOC7	SOC6	SOC5	SOC4	SOC3	SOC2	SOC1	SOC0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 14-73 ADCSOCFLG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	SOC15	R	0h	SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
14	SOC14	R	0h	SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
13	SOC13	R	0h	SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
12	SOC12	R	0h	SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
11	SOC11	R	0h	SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
10	SOC10	R	0h	SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
9	SOC9	R	0h	SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
8	SOC8	R	0h	SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
7	SOC7	R	0h	SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
6	SOC6	R	0h	SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
5	SOC5	R	0h	SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
4	SOC4	R	0h	SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
3	SOC3	R	0h	SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
2	SOC2	R	0h	SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
1	SOC1	R	0h	SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn
0	SOC0	R	0h	SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn

14.14.3.13 ADCSOCFRC1 Register (Offset = 14h) [Reset = 0000h]

ADCSOCFRC1 is shown in Figure 14-91 and described in Table 14-74.

Return to the Summary Table.

ADC SOC Force 1 Register

Figure 14-91 ADCSOCFRC1 Register

15	14	13	12	11	10	9	8
SOC15	SOC14	SOC13	SOC12	SOC11	SOC10	SOC9	SOC8
R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h

7	6	5	4	3	2	1	0
SOC7	SOC6	SOC5	SOC4	SOC3	SOC2	SOC1	SOC0
R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h

Table 14-74 ADCSOCFRC1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	SOC15	R-0/W1S	0h	SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC15 flag bit to 1. This will cause a conversion to start once priority is given to SOC15. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC15 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
14	SOC14	R-0/W1S	0h	SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC14 flag bit to 1. This will cause a conversion to start once priority is given to SOC14. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC14 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
13	SOC13	R-0/W1S	0h	SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC13 flag bit to 1. This will cause a conversion to start once priority is given to SOC13. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC13 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
12	SOC12	R-0/W1S	0h	SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC12 flag bit to 1. This will cause a conversion to start once priority is given to SOC12. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC12 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
11	SOC11	R-0/W1S	0h	SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC11 flag bit to 1. This will cause a conversion to start once priority is given to SOC11. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC11 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
10	SOC10	R-0/W1S	0h	SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC10 flag bit to 1. This will cause a conversion to start once priority is given to SOC10. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC10 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
9	SOC9	R-0/W1S	0h	SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC9 flag bit to 1. This will cause a conversion to start once priority is given to SOC9. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC9 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
8	SOC8	R-0/W1S	0h	SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC8 flag bit to 1. This will cause a conversion to start once priority is given to SOC8. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC8 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
7	SOC7	R-0/W1S	0h	SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC7 flag bit to 1. This will cause a conversion to start once priority is given to SOC7. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC7 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
6	SOC6	R-0/W1S	0h	SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC6 flag bit to 1. This will cause a conversion to start once priority is given to SOC6. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC6 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
5	SOC5	R-0/W1S	0h	SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC5 flag bit to 1. This will cause a conversion to start once priority is given to SOC5. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC5 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
4	SOC4	R-0/W1S	0h	SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC4 flag bit to 1. This will cause a conversion to start once priority is given to SOC4. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC4 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
3	SOC3	R-0/W1S	0h	SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC3 flag bit to 1. This will cause a conversion to start once priority is given to SOC3. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC3 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
2	SOC2	R-0/W1S	0h	SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC2 flag bit to 1. This will cause a conversion to start once priority is given to SOC2. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC2 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
1	SOC1	R-0/W1S	0h	SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC1 flag bit to 1. This will cause a conversion to start once priority is given to SOC1. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC1 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn
0	SOC0	R-0/W1S	0h	SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC0 flag bit to 1. This will cause a conversion to start once priority is given to SOC0. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC0 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn

14.14.3.14 ADCSOCOVF1 Register (Offset = 16h) [Reset = 0000h]

ADCSOCOVF1 is shown in Figure 14-92 and described in Table 14-75.

Return to the Summary Table.

ADC SOC Overflow 1 Register

Figure 14-92 ADCSOCOVF1 Register

15	14	13	12	11	10	9	8
SOC15	SOC14	SOC13	SOC12	SOC11	SOC10	SOC9	SOC8
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
SOC7	SOC6	SOC5	SOC4	SOC3	SOC2	SOC1	SOC0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 14-75 ADCSOCOVF1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	SOC15	R	0h	SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
14	SOC14	R	0h	SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
13	SOC13	R	0h	SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
12	SOC12	R	0h	SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
11	SOC11	R	0h	SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
10	SOC10	R	0h	SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
9	SOC9	R	0h	SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
8	SOC8	R	0h	SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
7	SOC7	R	0h	SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
6	SOC6	R	0h	SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
5	SOC5	R	0h	SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
4	SOC4	R	0h	SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
3	SOC3	R	0h	SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
2	SOC2	R	0h	SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
1	SOC1	R	0h	SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn
0	SOC0	R	0h	SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn

14.14.3.15 ADCSOCOVFCLR1 Register (Offset = 18h) [Reset = 0000h]

ADCSOCOVFCLR1 is shown in Figure 14-93 and described in Table 14-76.

Return to the Summary Table.

ADC SOC Overflow Clear 1 Register

Figure 14-93 ADCSOCOVFCLR1 Register

15	14	13	12	11	10	9	8
SOC15	SOC14	SOC13	SOC12	SOC11	SOC10	SOC9	SOC8
R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h

7	6	5	4	3	2	1	0
SOC7	SOC6	SOC5	SOC4	SOC3	SOC2	SOC1	SOC0
R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h

Table 14-76 ADCSOCOVFCLR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	SOC15	R-0/W1S	0h	SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
14	SOC14	R-0/W1S	0h	SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
13	SOC13	R-0/W1S	0h	SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
12	SOC12	R-0/W1S	0h	SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
11	SOC11	R-0/W1S	0h	SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
10	SOC10	R-0/W1S	0h	SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
9	SOC9	R-0/W1S	0h	SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
8	SOC8	R-0/W1S	0h	SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
7	SOC7	R-0/W1S	0h	SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
6	SOC6	R-0/W1S	0h	SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
5	SOC5	R-0/W1S	0h	SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
4	SOC4	R-0/W1S	0h	SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
3	SOC3	R-0/W1S	0h	SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
2	SOC2	R-0/W1S	0h	SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
1	SOC1	R-0/W1S	0h	SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn
0	SOC0	R-0/W1S	0h	SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn

14.14.3.16 ADCSOC0CTL Register (Offset = 1Ah) [Reset = 00000200h]

ADCSOC0CTL is shown in Figure 14-94 and described in Table 14-77.

Return to the Summary Table.

ADC SOC0 Control Register

Figure 14-94 ADCSOC0CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-77 ADCSOC0CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC0 External Channel Mux Select. Selects the external mux combination to output when SOC0 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC0 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.17 ADCSOC1CTL Register (Offset = 1Ch) [Reset = 00000200h]

ADCSOC1CTL is shown in Figure 14-95 and described in Table 14-78.

Return to the Summary Table.

ADC SOC1 Control Register

Figure 14-95 ADCSOC1CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-78 ADCSOC1CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC1 External Channel Mux Select. Selects the external mux combination to output when SOC1 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC1 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.18 ADCSOC2CTL Register (Offset = 1Eh) [Reset = 00000200h]

ADCSOC2CTL is shown in Figure 14-96 and described in Table 14-79.

Return to the Summary Table.

ADC SOC2 Control Register

Figure 14-96 ADCSOC2CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-79 ADCSOC2CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC2 External Channel Mux Select. Selects the external mux combination to output when SOC2 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC2 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.19 ADCSOC3CTL Register (Offset = 20h) [Reset = 00000200h]

ADCSOC3CTL is shown in Figure 14-97 and described in Table 14-80.

Return to the Summary Table.

ADC SOC3 Control Register

Figure 14-97 ADCSOC3CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-80 ADCSOC3CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC3 External Channel Mux Select. Selects the external mux combination to output when SOC3 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC3 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.20 ADCSOC4CTL Register (Offset = 22h) [Reset = 00000200h]

ADCSOC4CTL is shown in Figure 14-98 and described in Table 14-81.

Return to the Summary Table.

ADC SOC4 Control Register

Figure 14-98 ADCSOC4CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-81 ADCSOC4CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC4 External Channel Mux Select. Selects the external mux combination to output when SOC4 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC4 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.21 ADCSOC5CTL Register (Offset = 24h) [Reset = 00000200h]

ADCSOC5CTL is shown in Figure 14-99 and described in Table 14-82.

Return to the Summary Table.

ADC SOC5 Control Register

Figure 14-99 ADCSOC5CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-82 ADCSOC5CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC5 External Channel Mux Select. Selects the external mux combination to output when SOC5 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC5 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.22 ADCSOC6CTL Register (Offset = 26h) [Reset = 00000200h]

ADCSOC6CTL is shown in Figure 14-100 and described in Table 14-83.

Return to the Summary Table.

ADC SOC6 Control Register

Figure 14-100 ADCSOC6CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-83 ADCSOC6CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC6 External Channel Mux Select. Selects the external mux combination to output when SOC6 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC6 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.23 ADCSOC7CTL Register (Offset = 28h) [Reset = 00000200h]

ADCSOC7CTL is shown in Figure 14-101 and described in Table 14-84.

Return to the Summary Table.

ADC SOC7 Control Register

Figure 14-101 ADCSOC7CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-84 ADCSOC7CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC7 External Channel Mux Select. Selects the external mux combination to output when SOC7 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC7 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.24 ADCSOC8CTL Register (Offset = 2Ah) [Reset = 00000200h]

ADCSOC8CTL is shown in Figure 14-102 and described in Table 14-85.

Return to the Summary Table.

ADC SOC8 Control Register

Figure 14-102 ADCSOC8CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-85 ADCSOC8CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC8 External Channel Mux Select. Selects the external mux combination to output when SOC8 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC8 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.25 ADCSOC9CTL Register (Offset = 2Ch) [Reset = 00000200h]

ADCSOC9CTL is shown in Figure 14-103 and described in Table 14-86.

Return to the Summary Table.

ADC SOC9 Control Register

Figure 14-103 ADCSOC9CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-86 ADCSOC9CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC9 External Channel Mux Select. Selects the external mux combination to output when SOC9 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC9 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.26 ADCSOC10CTL Register (Offset = 2Eh) [Reset = 00000200h]

ADCSOC10CTL is shown in Figure 14-104 and described in Table 14-87.

Return to the Summary Table.

ADC SOC10 Control Register

Figure 14-104 ADCSOC10CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-87 ADCSOC10CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC10 External Channel Mux Select. Selects the external mux combination to output when SOC10 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC10 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.27 ADCSOC11CTL Register (Offset = 30h) [Reset = 00000200h]

ADCSOC11CTL is shown in Figure 14-105 and described in Table 14-88.

Return to the Summary Table.

ADC SOC11 Control Register

Figure 14-105 ADCSOC11CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-88 ADCSOC11CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC11 External Channel Mux Select. Selects the external mux combination to output when SOC11 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC11 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.28 ADCSOC12CTL Register (Offset = 32h) [Reset = 00000200h]

ADCSOC12CTL is shown in Figure 14-106 and described in Table 14-89.

Return to the Summary Table.

ADC SOC12 Control Register

Figure 14-106 ADCSOC12CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-89 ADCSOC12CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC12 External Channel Mux Select. Selects the external mux combination to output when SOC12 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC12 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.29 ADCSOC13CTL Register (Offset = 34h) [Reset = 00000200h]

ADCSOC13CTL is shown in Figure 14-107 and described in Table 14-90.

Return to the Summary Table.

ADC SOC13 Control Register

Figure 14-107 ADCSOC13CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-90 ADCSOC13CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC13 External Channel Mux Select. Selects the external mux combination to output when SOC13 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC13 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.30 ADCSOC14CTL Register (Offset = 36h) [Reset = 00000200h]

ADCSOC14CTL is shown in Figure 14-108 and described in Table 14-91.

Return to the Summary Table.

ADC SOC14 Control Register

Figure 14-108 ADCSOC14CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-91 ADCSOC14CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC14 External Channel Mux Select. Selects the external mux combination to output when SOC14 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC14 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.31 ADCSOC15CTL Register (Offset = 38h) [Reset = 00000200h]

ADCSOC15CTL is shown in Figure 14-109 and described in Table 14-92.

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ADC SOC15 Control Register

Figure 14-109 ADCSOC15CTL Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED	TRIGSEL
R/W-0h				R-0h	R/W-0h

23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
CHSEL	RESERVED			RESERVED		SAMPCAPRESETDISABLE	ACQPS
R/W-0h	R/W-0h			R/W-0h		R/W-1h	R/W-0h

7	6	5	4	3	2	1	0
ACQPS
R/W-0h

Table 14-92 ADCSOC15CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	EXTCHSEL	R/W	0h	SOC15 External Channel Mux Select. Selects the external mux combination to output when SOC15 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn
27	RESERVED	R	0h	Reserved
26-20	TRIGSEL	R/W	0h	SOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh - 1Fh - Reserved 20h ADCTRIG32 - ePWM13, ADCSOCA 21h ADCTRIG33 - ePWM13, ADCSOCB 22h ADCTRIG34 - ePWM14, ADCSOCA 23h ADCTRIG35 - ePWM14, ADCSOCB 24h ADCTRIG36 - ePWM15, ADCSOCA 25h ADCTRIG37 - ePWM15, ADCSOCB 26h ADCTRIG38 - ePWM16, ADCSOCA 27h ADCTRIG39 - ePWM16, ADCSOCB 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 2Fh - Reserved 30h ADCTRIG48 - ePWM17, ADCSOCA 31h ADCTRIG49 - ePWM17, ADCSOCB 32h ADCTRIG50 - ePWM18, ADCSOCA 33h ADCTRIG51 - ePWM18, ADCSOCB 34h ADCTRIG52 - ePWM19, ADCSOCA 35h ADCTRIG53 - ePWM19, ADCSOCB 36h ADCTRIG54 - ePWM20, ADCSOCA 37h ADCTRIG55 - ePWM20, ADCSOCB 38h ADCTRIG56 - ePWM21, ADCSOCA 39h ADCTRIG57 - ePWM21, ADCSOCB 3Ah ADCTRIG58 - ePWM22, ADCSOCA 3Bh ADCTRIG59 - ePWM22, ADCSOCB 3Ch ADCTRIG60 - ePWM23, ADCSOCA 3Dh ADCTRIG61 - ePWM23, ADCSOCB 3Eh ADCTRIG62 - ePWM24, ADCSOCA 3Fh ADCTRIG63 - ePWM24, ADCSOCB 40h ADCTRIG64 - ePWM25, ADCSOCA 41h ADCTRIG65 - ePWM25, ADCSOCB 42h ADCTRIG66 - ePWM26, ADCSOCA 43h ADCTRIG67 - ePWM26, ADCSOCB 44h ADCTRIG68 - ePWM27, ADCSOCA 45h ADCTRIG69 - ePWM27, ADCSOCB 46h ADCTRIG70 - ePWM28, ADCSOCA 47h ADCTRIG71 - ePWM28, ADCSOCB 48h ADCTRIG72 - ePWM29, ADCSOCA 49h ADCTRIG73 - ePWM29, ADCSOCB 4Ah ADCTRIG74 - ePWM30, ADCSOCA 4Bh ADCTRIG75 - ePWM30, ADCSOCB 4Ch ADCTRIG76 - ePWM31, ADCSOCA 4Dh ADCTRIG77 - ePWM31, ADCSOCB 4Eh ADCTRIG78 - ePWM32, ADCSOCA 4Fh ADCTRIG79 - ePWM32, ADCSOCB 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h - 7Fh - Reserved Reset type: SYSRSn
19-15	CHSEL	R/W	0h	SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn
14-12	RESERVED	R/W	0h	Reserved
11-10	RESERVED	R/W	0h	Reserved
9	SAMPCAPRESETDISABLE	R/W	1h	SOC15 Sample Cap Reset Select : Resets sample cap after conversion. 0 - The sample cap is reset after each conversion 1 - The sample cap is not reset after each conversion Reset type: SYSRSn
8-0	ACQPS	R/W	0h	SOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration. 000h Sample window is 1 system clock cycle wide 001h Sample window is 2 system clock cycles wide 002h Sample window is 3 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide Reset type: SYSRSn

14.14.3.32 ADCEVTSTAT Register (Offset = 5Ah) [Reset = 0000h]

ADCEVTSTAT is shown in Figure 14-110 and described in Table 14-93.

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ADC Event Status Register

Figure 14-110 ADCEVTSTAT Register

15	14	13	12	11	10	9	8
RESERVED	PPB4ZERO	PPB4TRIPLO	PPB4TRIPHI	RESERVED	PPB3ZERO	PPB3TRIPLO	PPB3TRIPHI
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED	PPB2ZERO	PPB2TRIPLO	PPB2TRIPHI	RESERVED	PPB1ZERO	PPB1TRIPLO	PPB1TRIPHI
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 14-93 ADCEVTSTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	PPB4ZERO	R	0h	Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
13	PPB4TRIPLO	R	0h	Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
12	PPB4TRIPHI	R	0h	Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
11	RESERVED	R	0h	Reserved
10	PPB3ZERO	R	0h	Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
9	PPB3TRIPLO	R	0h	Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
8	PPB3TRIPHI	R	0h	Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
7	RESERVED	R	0h	Reserved
6	PPB2ZERO	R	0h	Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
5	PPB2TRIPLO	R	0h	Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
4	PPB2TRIPHI	R	0h	Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
3	RESERVED	R	0h	Reserved
2	PPB1ZERO	R	0h	Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
1	PPB1TRIPLO	R	0h	Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
0	PPB1TRIPHI	R	0h	Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn

14.14.3.33 ADCEVTCLR Register (Offset = 5Ch) [Reset = 0000h]

ADCEVTCLR is shown in Figure 14-111 and described in Table 14-94.

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ADC Event Clear Register

Figure 14-111 ADCEVTCLR Register

15	14	13	12	11	10	9	8
RESERVED	PPB4ZERO	PPB4TRIPLO	PPB4TRIPHI	RESERVED	PPB3ZERO	PPB3TRIPLO	PPB3TRIPHI
R-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h

7	6	5	4	3	2	1	0
RESERVED	PPB2ZERO	PPB2TRIPLO	PPB2TRIPHI	RESERVED	PPB1ZERO	PPB1TRIPLO	PPB1TRIPHI
R-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h	R-0h	R-0/W1S-0h	R-0/W1S-0h	R-0/W1S-0h

Table 14-94 ADCEVTCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	PPB4ZERO	R-0/W1S	0h	Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
13	PPB4TRIPLO	R-0/W1S	0h	Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
12	PPB4TRIPHI	R-0/W1S	0h	Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
11	RESERVED	R	0h	Reserved
10	PPB3ZERO	R-0/W1S	0h	Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
9	PPB3TRIPLO	R-0/W1S	0h	Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
8	PPB3TRIPHI	R-0/W1S	0h	Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
7	RESERVED	R	0h	Reserved
6	PPB2ZERO	R-0/W1S	0h	Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
5	PPB2TRIPLO	R-0/W1S	0h	Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
4	PPB2TRIPHI	R-0/W1S	0h	Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
3	RESERVED	R	0h	Reserved
2	PPB1ZERO	R-0/W1S	0h	Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
1	PPB1TRIPLO	R-0/W1S	0h	Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn
0	PPB1TRIPHI	R-0/W1S	0h	Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn

14.14.3.34 ADCEVTSEL Register (Offset = 5Eh) [Reset = 0000h]

ADCEVTSEL is shown in Figure 14-112 and described in Table 14-95.

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ADC Event Selection Register

Figure 14-112 ADCEVTSEL Register

15	14	13	12	11	10	9	8
RESERVED	PPB4ZERO	PPB4TRIPLO	PPB4TRIPHI	RESERVED	PPB3ZERO	PPB3TRIPLO	PPB3TRIPHI
R-0h	R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED	PPB2ZERO	PPB2TRIPLO	PPB2TRIPHI	RESERVED	PPB1ZERO	PPB1TRIPLO	PPB1TRIPHI
R-0h	R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-0h	R/W-0h	R/W-0h

Table 14-95 ADCEVTSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	PPB4ZERO	R/W	0h	Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
13	PPB4TRIPLO	R/W	0h	Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
12	PPB4TRIPHI	R/W	0h	Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
11	RESERVED	R	0h	Reserved
10	PPB3ZERO	R/W	0h	Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
9	PPB3TRIPLO	R/W	0h	Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
8	PPB3TRIPHI	R/W	0h	Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
7	RESERVED	R	0h	Reserved
6	PPB2ZERO	R/W	0h	Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
5	PPB2TRIPLO	R/W	0h	Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
4	PPB2TRIPHI	R/W	0h	Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
3	RESERVED	R	0h	Reserved
2	PPB1ZERO	R/W	0h	Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
1	PPB1TRIPLO	R/W	0h	Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn
0	PPB1TRIPHI	R/W	0h	Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn

14.14.3.35 ADCEVTINTSEL Register (Offset = 60h) [Reset = 0000h]

ADCEVTINTSEL is shown in Figure 14-113 and described in Table 14-96.

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ADC Event Interrupt Selection Register

Figure 14-113 ADCEVTINTSEL Register

15	14	13	12	11	10	9	8
RESERVED	PPB4ZERO	PPB4TRIPLO	PPB4TRIPHI	RESERVED	PPB3ZERO	PPB3TRIPLO	PPB3TRIPHI
R-0h	R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED	PPB2ZERO	PPB2TRIPLO	PPB2TRIPHI	RESERVED	PPB1ZERO	PPB1TRIPLO	PPB1TRIPHI
R-0h	R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-0h	R/W-0h	R/W-0h

Table 14-96 ADCEVTINTSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	PPB4ZERO	R/W	0h	Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn
13	PPB4TRIPLO	R/W	0h	Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn
12	PPB4TRIPHI	R/W	0h	Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn
11	RESERVED	R	0h	Reserved
10	PPB3ZERO	R/W	0h	Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn
9	PPB3TRIPLO	R/W	0h	Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn
8	PPB3TRIPHI	R/W	0h	Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn
7	RESERVED	R	0h	Reserved
6	PPB2ZERO	R/W	0h	Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn
5	PPB2TRIPLO	R/W	0h	Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn
4	PPB2TRIPHI	R/W	0h	Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn
3	RESERVED	R	0h	Reserved
2	PPB1ZERO	R/W	0h	Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn
1	PPB1TRIPLO	R/W	0h	Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn
0	PPB1TRIPHI	R/W	0h	Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn

14.14.3.36 ADCCOUNTER Register (Offset = 63h) [Reset = 0000h]

ADCCOUNTER is shown in Figure 14-114 and described in Table 14-97.

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ADC Counter Register

Figure 14-114 ADCCOUNTER Register

15	14	13	12	11	10	9	8
RESERVED				FREECOUNT
R-0h				R-0h

7	6	5	4	3	2	1	0
FREECOUNT
R-0h

Table 14-97 ADCCOUNTER Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11-0	FREECOUNT	R	0h	ADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter. Reset type: SYSRSn

14.14.3.37 ADCREV Register (Offset = 64h) [Reset = 0105h]

ADCREV is shown in Figure 14-115 and described in Table 14-98.

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ADC Revision Register

Figure 14-115 ADCREV Register

15	14	13	12	11	10	9	8
REV
R-1h

7	6	5	4	3	2	1	0
TYPE
R-5h

Table 14-98 ADCREV Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	REV	R	1h	ADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h. Reset type: SYSRSn
7-0	TYPE	R	5h	ADC Type. Always set to 5 for this ADC. Reset type: SYSRSn

14.14.3.38 ADCOFFTRIM Register (Offset = 65h) [Reset = 0000h]

ADCOFFTRIM is shown in Figure 14-116 and described in Table 14-99.

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ADC Offset Trim Register

Figure 14-116 ADCOFFTRIM Register

15	14	13	12	11	10	9	8
RESERVED				OFFTRIM
R-0h				R/W-0h

7	6	5	4	3	2	1	0
OFFTRIM
R/W-0h

Table 14-99 ADCOFFTRIM Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11-0	OFFTRIM	R/W	0h	ADC Offset Trim. Adjusts the conversion results of the converter up or down to account for offset error in the ADC. Range is +2047 steps to -2048 steps (2's compliment format). Reset type: XRSn

14.14.3.39 ADCCONFIG2 Register (Offset = 66h) [Reset = 00000000h]

ADCCONFIG2 is shown in Figure 14-117 and described in Table 14-100.

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ADC Config Register Upper 32 bits

Figure 14-117 ADCCONFIG2 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-0h

23	22	21	20	19	18	17	16
RESERVED
R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
RESERVED						TESTANA1_CONFIG
R/W-0h						R/W-0h

Table 14-100 ADCCONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R/W	0h	Reserved
1-0	TESTANA1_CONFIG	R/W	0h	ADC Configuration. This bit field is used for selecting Internal nodes on TESTANA1 00: VREFN 10: Input Mux output x1: Invalid Reset type: SYSRSn

14.14.3.40 ADCPPB1CONFIG Register (Offset = 6Ah) [Reset = 0000h]

ADCPPB1CONFIG is shown in Figure 14-118 and described in Table 14-101.

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ADC PPB{#} Config Register

Figure 14-118 ADCPPB1CONFIG Register

15	14	13	12	11	10	9	8
RESERVED							DELTAEN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
TWOSCOMPEN	ABSEN	CBCEN	RESERVED	CONFIG
R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-0h

Table 14-101 ADCPPB1CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8	DELTAEN	R/W	0h	ADC Post Processing Block 1 enable delta (difference) from last sample calcualtion. When set, the ADCPPB1RESULT register will contain the difference between the most recent conversion result and the last value that would have been loaded into the ADCPPB1RESULT (if the delta calculation wasn't enabled). The delta calculation occurs after OFFREF, TWOSCOMPEN, and ABSEN calculations are applied. 0 Delta calculation disabled: no modification to ADCPPB1RESULT 1 ADCPPB1RESULT = ADCPPB1RESULT'[t] - ADCPPB1RESULT'[t - 1] Where ADCPPB1RESULT' is the value that would have been loaded into ADCPPB1RESULT without delta calculation Reset type: SYSRSn
7	TWOSCOMPEN	R/W	0h	ADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB1RESULT register. 0 ADCPPB1RESULT = ADCRESULTx - ADCPPB1OFFREF 1 ADCPPB1RESULT = ADCPPB1OFFREF - ADCRESULTx Reset type: SYSRSn
6	ABSEN	R/W	0h	ADC Post Processing Block 1 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB1. This occurs before the TWOSCOMPEN logic is evaluated (so enabling both TWOSCOMPEN and ABSEN will always result in a negative value stored in ADCPPBxRESULT) 0 ADCPPB1RESULT = ADCRESULTx - ADCPPB1OFFREF 1 ADCPPB1RESULT = abs(ADCRESULTx - ADCPPB1OFFREF) Reset type: SYSRSn
5	CBCEN	R/W	0h	ADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present. Reset type: SYSRSn
4	RESERVED	R	0h	Reserved
3-0	CONFIG	R/W	0h	ADC Post Processing Block {#} Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block {#} 0001 SOC1/EOC1/RESULT1 is associated with post processing block {#} 0010 SOC2/EOC2/RESULT2 is associated with post processing block {#} 0011 SOC3/EOC3/RESULT3 is associated with post processing block {#} 0100 SOC4/EOC4/RESULT4 is associated with post processing block {#} 0101 SOC5/EOC5/RESULT5 is associated with post processing block {#} 0110 SOC6/EOC6/RESULT6 is associated with post processing block {#} 0111 SOC7/EOC7/RESULT7 is associated with post processing block {#} 1000 SOC8/EOC8/RESULT8 is associated with post processing block {#} 1001 SOC9/EOC9/RESULT9 is associated with post processing block {#} 1010 SOC10/EOC10/RESULT10 is associated with post processing block {#} 1011 SOC11/EOC11/RESULT11 is associated with post processing block {#} 1100 SOC12/EOC12/RESULT12 is associated with post processing block {#} 1101 SOC13/EOC13/RESULT13 is associated with post processing block {#} 1110 SOC14/EOC14/RESULT14 is associated with post processing block {#} 1111 SOC15/EOC15/RESULT15 is associated with post processing block {#} Reset type: SYSRSn

14.14.3.41 ADCPPB1STAMP Register (Offset = 6Bh) [Reset = 0000h]

ADCPPB1STAMP is shown in Figure 14-119 and described in Table 14-102.

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ADC PPB1 Sample Delay Time Stamp Register

Figure 14-119 ADCPPB1STAMP Register

15	14	13	12	11	10	9	8
RESERVED				DLYSTAMP
R-0h				R-0h

7	6	5	4	3	2	1	0
DLYSTAMP
R-0h

Table 14-102 ADCPPB1STAMP Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11-0	DLYSTAMP	R	0h	ADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field, thereby giving the number of system clock cycles delay between the SOC trigger and the actual start of the sample. Reset type: SYSRSn

14.14.3.42 ADCPPB1OFFCAL Register (Offset = 6Ch) [Reset = 0000h]

ADCPPB1OFFCAL is shown in Figure 14-120 and described in Table 14-103.

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ADC PPB1 Offset Calibration Register

Figure 14-120 ADCPPB1OFFCAL Register

15	14	13	12	11	10	9	8
RESERVED						OFFCAL
R-0h						R/W-0h

7	6	5	4	3	2	1	0
OFFCAL
R/W-0h

Table 14-103 ADCPPB1OFFCAL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	OFFCAL	R/W	0h	ADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register. 000h No change. The ADC output is stored directly into ADCRESULT. 001h ADC output - 1 is stored into ADCRESULT. 002h ADC output - 2 is stored into ADCRESULT. ... 200h ADC output + 512 is stored into ADCRESULT. ... 3FFh ADC output + 1 is stored into ADCRESULT. NOTE: In 16-bit mode, the subtraction will saturate at 0000h and FFFFh before being stored into the ADCRESULT register. In 12-bit mode, the subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register. Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied. Reset type: SYSRSn

14.14.3.43 ADCPPB1OFFREF Register (Offset = 6Dh) [Reset = 0000h]

ADCPPB1OFFREF is shown in Figure 14-121 and described in Table 14-104.

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ADC PPB1 Offset Reference Register

Figure 14-121 ADCPPB1OFFREF Register

15	14	13	12	11	10	9	8
OFFREF
R/W-0h

7	6	5	4	3	2	1	0
OFFREF
R/W-0h

Table 14-104 ADCPPB1OFFREF Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	OFFREF	R/W	0h	ADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB1RESULT register. This subtraction is not saturated. 0000h No change. The ADCRESULT value is passed on. 0001h ADCRESULT - 1 is passed on. 0002h ADCRESULT - 2 is passed on. ... 8000h ADCRESULT - 32,768 is passed on. ... FFFFh ADCRESULT - 65,535 is passed on. NOTE: In 12-bit mode the size of this register does not change from 16-bits. It is the user's responsibility to ensure that only a 12-bit value is written to this register when in 12-bit mode. Reset type: SYSRSn

14.14.3.44 ADCPPB1TRIPHI Register (Offset = 6Eh) [Reset = 00000000h]

ADCPPB1TRIPHI is shown in Figure 14-122 and described in Table 14-105.

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ADC PPB1 Trip High Register

Figure 14-122 ADCPPB1TRIPHI Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								LIMITHI
R-0h								R/W-0h

Table 14-105 ADCPPB1TRIPHI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	LIMITHI	R/W	0h	ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will be ignored in 12 bit mode Reset type: SYSRSn

14.14.3.45 ADCPPB1TRIPLO Register (Offset = 70h) [Reset = 00000000h]

ADCPPB1TRIPLO is shown in Figure 14-123 and described in Table 14-106.

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ADC PPB1 Trip Low/Trigger Time Stamp Register

Figure 14-123 ADCPPB1TRIPLO Register

31	30	29	28	27	26	25	24
REQSTAMP
R-0h

23	22	21	20	19	18	17	16
REQSTAMP				LIMITLO2EN	RESERVED		LSIGN
R-0h				R/W-0h	R-0h		R/W-0h

15	14	13	12	11	10	9	8
LIMITLO
R/W-0h

7	6	5	4	3	2	1	0
LIMITLO
R/W-0h

Table 14-106 ADCPPB1TRIPLO Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	REQSTAMP	R	0h	ADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field. Reset type: SYSRSn
19	LIMITLO2EN	R/W	0h	Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB1TRIPLO register. Not compatible with comparison with ADCPPB1PSUM or ADCPPB1SUM 1 = Low limit set by ADCPPB1TRIPLO2 register Reset type: SYSRSn
18-17	RESERVED	R	0h	Reserved
16	LSIGN	R/W	0h	Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode. Reset type: SYSRSn
15-0	LIMITLO	R/W	0h	ADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0 will be compared against bits 12:0 of the PPBRSULT bit field of the ADCPPB1RESULT register. Reset type: SYSRSn

14.14.3.46 ADCPPBTRIP1FILCTL Register (Offset = 72h) [Reset = 0000h]

ADCPPBTRIP1FILCTL is shown in Figure 14-124 and described in Table 14-107.

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ADCEVT1 Trip High Filter Control Register

Figure 14-124 ADCPPBTRIP1FILCTL Register

15	14	13	12	11	10	9	8
FILINIT	THRESH						SAMPWIN
R-0/W1S-0h	R/W-0h						R/W-0h

7	6	5	4	3	2	1	0
SAMPWIN					RESERVED	FILTLOEN	FILTHIEN
R/W-0h					R-0h	R/W-0h	R/W-0h

Table 14-107 ADCPPBTRIP1FILCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	FILINIT	R-0/W1S	0h	Trip filter initialization for PPB1. 0 No effect 1 Initialize all samples to the filter input value This applies to the filter on both the high and low trips. Reset type: SYSRSn
14-9	THRESH	R/W	0h	Trip filter majority voting threshold on PPB1. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1. This applies to the filter on both the high and low trips. Reset type: SYSRSn
8-3	SAMPWIN	R/W	0h	Trip filter sample window size on PPB1. Number of samples to monitor is SAMPWIN+1. This applies to the filter on both the high and low trips. Reset type: SYSRSn
2	RESERVED	R	0h	Reserved
1	FILTLOEN	R/W	0h	ADC PPB1 TRIPLO Filter Enable 0 No filtering of PPB 1 trip low limit events 1 PPB1 trip high limit event filtering enabled Reset type: SYSRSn
0	FILTHIEN	R/W	0h	ADC PPB1 TRIPHI Filter Enable 0 No filtering of PPB 1 trip high limit events 1 PPB1 trip high limit event filtering enabled Reset type: SYSRSn

14.14.3.47 ADCPPBTRIP1FILCLKCTL Register (Offset = 74h) [Reset = 00000000h]

ADCPPBTRIP1FILCLKCTL is shown in Figure 14-125 and described in Table 14-108.

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ADCEVT1 Trip High Filter Prescale Control Register

Figure 14-125 ADCPPBTRIP1FILCLKCTL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																CLKPRESCALE
R-0h																R/W-0h

Table 14-108 ADCPPBTRIP1FILCLKCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	CLKPRESCALE	R/W	0h	ADCPPB1 filter sample clock prescale. The effective prescale value is (CLKPRESCALE + 1). This applies to the filter on both the high and low trips. Reset type: SYSRSn

14.14.3.48 ADCPPB2CONFIG Register (Offset = 7Ah) [Reset = 0001h]

ADCPPB2CONFIG is shown in Figure 14-126 and described in Table 14-109.

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ADC PPB{#} Config Register

Figure 14-126 ADCPPB2CONFIG Register

15	14	13	12	11	10	9	8
RESERVED							DELTAEN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
TWOSCOMPEN	ABSEN	CBCEN	RESERVED	CONFIG
R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-1h

Table 14-109 ADCPPB2CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8	DELTAEN	R/W	0h	ADC Post Processing Block 2 enable delta (difference) from last sample calcualtion. When set, the ADCPPB2RESULT register will contain the difference between the most recent conversion result and the last value that would have been loaded into the ADCPPB2RESULT (if the delta calculation wasn't enabled). The delta calculation occurs after OFFREF, TWOSCOMPEN, and ABSEN calculations are applied. 0 Delta calculation disabled: no modification to ADCPPB2RESULT 1 ADCPPB2RESULT = ADCPPB2RESULT'[t] - ADCPPB2RESULT'[t - 1] Where ADCPPB2RESULT' is the value that would have been loaded into ADCPPB2RESULT without delta calculation Reset type: SYSRSn
7	TWOSCOMPEN	R/W	0h	ADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB2RESULT register. 0 ADCPPB2RESULT = ADCRESULTx - ADCPPB2OFFREF 1 ADCPPB2RESULT = ADCPPB2OFFREF - ADCRESULTx Reset type: SYSRSn
6	ABSEN	R/W	0h	ADC Post Processing Block 2 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB2. This occurs before the TWOSCOMPEN logic is evaluated (so enabling both TWOSCOMPEN and ABSEN will always result in a negative value stored in ADCPPBxRESULT) 0 ADCPPB2RESULT = ADCRESULTx - ADCPPB2OFFREF 1 ADCPPB2RESULT = abs(ADCRESULTx - ADCPPB2OFFREF) Reset type: SYSRSn
5	CBCEN	R/W	0h	ADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present. Reset type: SYSRSn
4	RESERVED	R	0h	Reserved
3-0	CONFIG	R/W	1h	ADC Post Processing Block {#} Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block {#} 0001 SOC1/EOC1/RESULT1 is associated with post processing block {#} 0010 SOC2/EOC2/RESULT2 is associated with post processing block {#} 0011 SOC3/EOC3/RESULT3 is associated with post processing block {#} 0100 SOC4/EOC4/RESULT4 is associated with post processing block {#} 0101 SOC5/EOC5/RESULT5 is associated with post processing block {#} 0110 SOC6/EOC6/RESULT6 is associated with post processing block {#} 0111 SOC7/EOC7/RESULT7 is associated with post processing block {#} 1000 SOC8/EOC8/RESULT8 is associated with post processing block {#} 1001 SOC9/EOC9/RESULT9 is associated with post processing block {#} 1010 SOC10/EOC10/RESULT10 is associated with post processing block {#} 1011 SOC11/EOC11/RESULT11 is associated with post processing block {#} 1100 SOC12/EOC12/RESULT12 is associated with post processing block {#} 1101 SOC13/EOC13/RESULT13 is associated with post processing block {#} 1110 SOC14/EOC14/RESULT14 is associated with post processing block {#} 1111 SOC15/EOC15/RESULT15 is associated with post processing block {#} Reset type: SYSRSn

14.14.3.49 ADCPPB2STAMP Register (Offset = 7Bh) [Reset = 0000h]

ADCPPB2STAMP is shown in Figure 14-127 and described in Table 14-110.

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ADC PPB2 Sample Delay Time Stamp Register

Figure 14-127 ADCPPB2STAMP Register

15	14	13	12	11	10	9	8
RESERVED				DLYSTAMP
R-0h				R-0h

7	6	5	4	3	2	1	0
DLYSTAMP
R-0h

Table 14-110 ADCPPB2STAMP Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11-0	DLYSTAMP	R	0h	ADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field, thereby giving the number of system clock cycles delay between the SOC trigger and the actual start of the sample. Reset type: SYSRSn

14.14.3.50 ADCPPB2OFFCAL Register (Offset = 7Ch) [Reset = 0000h]

ADCPPB2OFFCAL is shown in Figure 14-128 and described in Table 14-111.

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ADC PPB2 Offset Calibration Register

Figure 14-128 ADCPPB2OFFCAL Register

15	14	13	12	11	10	9	8
RESERVED						OFFCAL
R-0h						R/W-0h

7	6	5	4	3	2	1	0
OFFCAL
R/W-0h

Table 14-111 ADCPPB2OFFCAL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	OFFCAL	R/W	0h	ADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register. 000h No change. The ADC output is stored directly into ADCRESULT. 001h ADC output - 1 is stored into ADCRESULT. 002h ADC output - 2 is stored into ADCRESULT. ... 200h ADC output + 512 is stored into ADCRESULT. ... 3FFh ADC output + 1 is stored into ADCRESULT. NOTE: In 16-bit mode, the subtraction will saturate at 0000h and FFFFh before being stored into the ADCRESULT register. In 12-bit mode, the subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register. Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied. Reset type: SYSRSn

14.14.3.51 ADCPPB2OFFREF Register (Offset = 7Dh) [Reset = 0000h]

ADCPPB2OFFREF is shown in Figure 14-129 and described in Table 14-112.

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ADC PPB2 Offset Reference Register

Figure 14-129 ADCPPB2OFFREF Register

15	14	13	12	11	10	9	8
OFFREF
R/W-0h

7	6	5	4	3	2	1	0
OFFREF
R/W-0h

Table 14-112 ADCPPB2OFFREF Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	OFFREF	R/W	0h	ADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB2RESULT register. This subtraction is not saturated. 0000h No change. The ADCRESULT value is passed on. 0001h ADCRESULT - 1 is passed on. 0002h ADCRESULT - 2 is passed on. ... 8000h ADCRESULT - 32,768 is passed on. ... FFFFh ADCRESULT - 65,535 is passed on. NOTE: In 12-bit mode the size of this register does not change from 16-bits. It is the user's responsibility to ensure that only a 12-bit value is written to this register when in 12-bit mode. Reset type: SYSRSn

14.14.3.52 ADCPPB2TRIPHI Register (Offset = 7Eh) [Reset = 00000000h]

ADCPPB2TRIPHI is shown in Figure 14-130 and described in Table 14-113.

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ADC PPB2 Trip High Register

Figure 14-130 ADCPPB2TRIPHI Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								LIMITHI
R-0h								R/W-0h

Table 14-113 ADCPPB2TRIPHI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	LIMITHI	R/W	0h	ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will be ignored in 12 bit mode Reset type: SYSRSn

14.14.3.53 ADCPPB2TRIPLO Register (Offset = 80h) [Reset = 00000000h]

ADCPPB2TRIPLO is shown in Figure 14-131 and described in Table 14-114.

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ADC PPB2 Trip Low/Trigger Time Stamp Register

Figure 14-131 ADCPPB2TRIPLO Register

31	30	29	28	27	26	25	24
REQSTAMP
R-0h

23	22	21	20	19	18	17	16
REQSTAMP				LIMITLO2EN	RESERVED		LSIGN
R-0h				R/W-0h	R-0h		R/W-0h

15	14	13	12	11	10	9	8
LIMITLO
R/W-0h

7	6	5	4	3	2	1	0
LIMITLO
R/W-0h

Table 14-114 ADCPPB2TRIPLO Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	REQSTAMP	R	0h	ADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field. Reset type: SYSRSn
19	LIMITLO2EN	R/W	0h	Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB2TRIPLO register. Not compatible with comparison with ADCPPB2PSUM or ADCPPB2SUM 1 = Low limit set by ADCPPB2TRIPLO2 register Reset type: SYSRSn
18-17	RESERVED	R	0h	Reserved
16	LSIGN	R/W	0h	Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode. Reset type: SYSRSn
15-0	LIMITLO	R/W	0h	ADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0 will be compared against bits 12:0 of the PPBRSULT bit field of the ADCPPB2RESULT register. Reset type: SYSRSn

14.14.3.54 ADCPPBTRIP2FILCTL Register (Offset = 82h) [Reset = 0000h]

ADCPPBTRIP2FILCTL is shown in Figure 14-132 and described in Table 14-115.

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ADCEVT2 Trip High Filter Control Register

Figure 14-132 ADCPPBTRIP2FILCTL Register

15	14	13	12	11	10	9	8
FILINIT	THRESH						SAMPWIN
R-0/W1S-0h	R/W-0h						R/W-0h

7	6	5	4	3	2	1	0
SAMPWIN					RESERVED	FILTLOEN	FILTHIEN
R/W-0h					R-0h	R/W-0h	R/W-0h

Table 14-115 ADCPPBTRIP2FILCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	FILINIT	R-0/W1S	0h	Trip filter initialization for PPB2. 0 No effect 1 Initialize all samples to the filter input value This applies to the filter on both the high and low trips. Reset type: SYSRSn
14-9	THRESH	R/W	0h	Trip filter majority voting threshold on PPB2. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1. This applies to the filter on both the high and low trips. Reset type: SYSRSn
8-3	SAMPWIN	R/W	0h	Trip filter sample window size on PPB2. Number of samples to monitor is SAMPWIN+1. This applies to the filter on both the high and low trips. Reset type: SYSRSn
2	RESERVED	R	0h	Reserved
1	FILTLOEN	R/W	0h	ADC PPB2 TRIPLO Filter Enable 0 No filtering of PPB 2 trip low limit events 1 PPB2 trip high limit event filtering enabled Reset type: SYSRSn
0	FILTHIEN	R/W	0h	ADC PPB2 TRIPHI Filter Enable 0 No filtering of PPB 2 trip high limit events 1 PPB2 trip high limit event filtering enabled Reset type: SYSRSn

14.14.3.55 ADCPPBTRIP2FILCLKCTL Register (Offset = 84h) [Reset = 00000000h]

ADCPPBTRIP2FILCLKCTL is shown in Figure 14-133 and described in Table 14-116.

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ADCEVT2 Trip High Filter Prescale Control Register

Figure 14-133 ADCPPBTRIP2FILCLKCTL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																CLKPRESCALE
R-0h																R/W-0h

Table 14-116 ADCPPBTRIP2FILCLKCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	CLKPRESCALE	R/W	0h	ADCPPB2 filter sample clock prescale. The effective prescale value is (CLKPRESCALE + 1). This applies to the filter on both the high and low trips. Reset type: SYSRSn

14.14.3.56 ADCPPB3CONFIG Register (Offset = 8Ah) [Reset = 0002h]

ADCPPB3CONFIG is shown in Figure 14-134 and described in Table 14-117.

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ADC PPB{#} Config Register

Figure 14-134 ADCPPB3CONFIG Register

15	14	13	12	11	10	9	8
RESERVED							DELTAEN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
TWOSCOMPEN	ABSEN	CBCEN	RESERVED	CONFIG
R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-2h

Table 14-117 ADCPPB3CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8	DELTAEN	R/W	0h	ADC Post Processing Block 3 enable delta (difference) from last sample calcualtion. When set, the ADCPPB3RESULT register will contain the difference between the most recent conversion result and the last value that would have been loaded into the ADCPPB3RESULT (if the delta calculation wasn't enabled). The delta calculation occurs after OFFREF, TWOSCOMPEN, and ABSEN calculations are applied. 0 Delta calculation disabled: no modification to ADCPPB3RESULT 1 ADCPPB3RESULT = ADCPPB3RESULT'[t] - ADCPPB3RESULT'[t - 1] Where ADCPPB3RESULT' is the value that would have been loaded into ADCPPB3RESULT without delta calculation Reset type: SYSRSn
7	TWOSCOMPEN	R/W	0h	ADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB3RESULT register. 0 ADCPPB3RESULT = ADCRESULTx - ADCPPB3OFFREF 1 ADCPPB3RESULT = ADCPPB3OFFREF - ADCRESULTx Reset type: SYSRSn
6	ABSEN	R/W	0h	ADC Post Processing Block 3 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB3. This occurs before the TWOSCOMPEN logic is evaluated (so enabling both TWOSCOMPEN and ABSEN will always result in a negative value stored in ADCPPBxRESULT) 0 ADCPPB3RESULT = ADCRESULTx - ADCPPB3OFFREF 1 ADCPPB3RESULT = abs(ADCRESULTx - ADCPPB3OFFREF) Reset type: SYSRSn
5	CBCEN	R/W	0h	ADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present. Reset type: SYSRSn
4	RESERVED	R	0h	Reserved
3-0	CONFIG	R/W	2h	ADC Post Processing Block {#} Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block {#} 0001 SOC1/EOC1/RESULT1 is associated with post processing block {#} 0010 SOC2/EOC2/RESULT2 is associated with post processing block {#} 0011 SOC3/EOC3/RESULT3 is associated with post processing block {#} 0100 SOC4/EOC4/RESULT4 is associated with post processing block {#} 0101 SOC5/EOC5/RESULT5 is associated with post processing block {#} 0110 SOC6/EOC6/RESULT6 is associated with post processing block {#} 0111 SOC7/EOC7/RESULT7 is associated with post processing block {#} 1000 SOC8/EOC8/RESULT8 is associated with post processing block {#} 1001 SOC9/EOC9/RESULT9 is associated with post processing block {#} 1010 SOC10/EOC10/RESULT10 is associated with post processing block {#} 1011 SOC11/EOC11/RESULT11 is associated with post processing block {#} 1100 SOC12/EOC12/RESULT12 is associated with post processing block {#} 1101 SOC13/EOC13/RESULT13 is associated with post processing block {#} 1110 SOC14/EOC14/RESULT14 is associated with post processing block {#} 1111 SOC15/EOC15/RESULT15 is associated with post processing block {#} Reset type: SYSRSn

14.14.3.57 ADCPPB3STAMP Register (Offset = 8Bh) [Reset = 0000h]

ADCPPB3STAMP is shown in Figure 14-135 and described in Table 14-118.

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ADC PPB3 Sample Delay Time Stamp Register

Figure 14-135 ADCPPB3STAMP Register

15	14	13	12	11	10	9	8
RESERVED				DLYSTAMP
R-0h				R-0h

7	6	5	4	3	2	1	0
DLYSTAMP
R-0h

Table 14-118 ADCPPB3STAMP Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11-0	DLYSTAMP	R	0h	ADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field, thereby giving the number of system clock cycles delay between the SOC trigger and the actual start of the sample. Reset type: SYSRSn

14.14.3.58 ADCPPB3OFFCAL Register (Offset = 8Ch) [Reset = 0000h]

ADCPPB3OFFCAL is shown in Figure 14-136 and described in Table 14-119.

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ADC PPB3 Offset Calibration Register

Figure 14-136 ADCPPB3OFFCAL Register

15	14	13	12	11	10	9	8
RESERVED						OFFCAL
R-0h						R/W-0h

7	6	5	4	3	2	1	0
OFFCAL
R/W-0h

Table 14-119 ADCPPB3OFFCAL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	OFFCAL	R/W	0h	ADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register. 000h No change. The ADC output is stored directly into ADCRESULT. 001h ADC output - 1 is stored into ADCRESULT. 002h ADC output - 2 is stored into ADCRESULT. ... 200h ADC output + 512 is stored into ADCRESULT. ... 3FFh ADC output + 1 is stored into ADCRESULT. NOTE: In 16-bit mode, the subtraction will saturate at 0000h and FFFFh before being stored into the ADCRESULT register. In 12-bit mode, the subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register. Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied. Reset type: SYSRSn

14.14.3.59 ADCPPB3OFFREF Register (Offset = 8Dh) [Reset = 0000h]

ADCPPB3OFFREF is shown in Figure 14-137 and described in Table 14-120.

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ADC PPB3 Offset Reference Register

Figure 14-137 ADCPPB3OFFREF Register

15	14	13	12	11	10	9	8
OFFREF
R/W-0h

7	6	5	4	3	2	1	0
OFFREF
R/W-0h

Table 14-120 ADCPPB3OFFREF Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	OFFREF	R/W	0h	ADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB3RESULT register. This subtraction is not saturated. 0000h No change. The ADCRESULT value is passed on. 0001h ADCRESULT - 1 is passed on. 0002h ADCRESULT - 2 is passed on. ... 8000h ADCRESULT - 32,768 is passed on. ... FFFFh ADCRESULT - 65,535 is passed on. NOTE: In 12-bit mode the size of this register does not change from 16-bits. It is the user's responsibility to ensure that only a 12-bit value is written to this register when in 12-bit mode. Reset type: SYSRSn

14.14.3.60 ADCPPB3TRIPHI Register (Offset = 8Eh) [Reset = 00000000h]

ADCPPB3TRIPHI is shown in Figure 14-138 and described in Table 14-121.

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ADC PPB3 Trip High Register

Figure 14-138 ADCPPB3TRIPHI Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								LIMITHI
R-0h								R/W-0h

Table 14-121 ADCPPB3TRIPHI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	LIMITHI	R/W	0h	ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will be ignored in 12 bit mode Reset type: SYSRSn

14.14.3.61 ADCPPB3TRIPLO Register (Offset = 90h) [Reset = 00000000h]

ADCPPB3TRIPLO is shown in Figure 14-139 and described in Table 14-122.

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ADC PPB3 Trip Low/Trigger Time Stamp Register

Figure 14-139 ADCPPB3TRIPLO Register

31	30	29	28	27	26	25	24
REQSTAMP
R-0h

23	22	21	20	19	18	17	16
REQSTAMP				LIMITLO2EN	RESERVED		LSIGN
R-0h				R/W-0h	R-0h		R/W-0h

15	14	13	12	11	10	9	8
LIMITLO
R/W-0h

7	6	5	4	3	2	1	0
LIMITLO
R/W-0h

Table 14-122 ADCPPB3TRIPLO Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	REQSTAMP	R	0h	ADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field. Reset type: SYSRSn
19	LIMITLO2EN	R/W	0h	Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB3TRIPLO register. Not compatible with comparison with ADCPPB3PSUM or ADCPPB3SUM 1 = Low limit set by ADCPPB3TRIPLO2 register Reset type: SYSRSn
18-17	RESERVED	R	0h	Reserved
16	LSIGN	R/W	0h	Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode. Reset type: SYSRSn
15-0	LIMITLO	R/W	0h	ADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0 will be compared against bits 12:0 of the PPBRSULT bit field of the ADCPPB3RESULT register. Reset type: SYSRSn

14.14.3.62 ADCPPBTRIP3FILCTL Register (Offset = 92h) [Reset = 0000h]

ADCPPBTRIP3FILCTL is shown in Figure 14-140 and described in Table 14-123.

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ADCEVT3 Trip High Filter Control Register

Figure 14-140 ADCPPBTRIP3FILCTL Register

15	14	13	12	11	10	9	8
FILINIT	THRESH						SAMPWIN
R-0/W1S-0h	R/W-0h						R/W-0h

7	6	5	4	3	2	1	0
SAMPWIN					RESERVED	FILTLOEN	FILTHIEN
R/W-0h					R-0h	R/W-0h	R/W-0h

Table 14-123 ADCPPBTRIP3FILCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	FILINIT	R-0/W1S	0h	Trip filter initialization for PPB3. 0 No effect 1 Initialize all samples to the filter input value This applies to the filter on both the high and low trips. Reset type: SYSRSn
14-9	THRESH	R/W	0h	Trip filter majority voting threshold on PPB3. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1. This applies to the filter on both the high and low trips. Reset type: SYSRSn
8-3	SAMPWIN	R/W	0h	Trip filter sample window size on PPB3. Number of samples to monitor is SAMPWIN+1. This applies to the filter on both the high and low trips. Reset type: SYSRSn
2	RESERVED	R	0h	Reserved
1	FILTLOEN	R/W	0h	ADC PPB3 TRIPLO Filter Enable 0 No filtering of PPB 3 trip low limit events 1 PPB3 trip high limit event filtering enabled Reset type: SYSRSn
0	FILTHIEN	R/W	0h	ADC PPB3 TRIPHI Filter Enable 0 No filtering of PPB 3 trip high limit events 1 PPB3 trip high limit event filtering enabled Reset type: SYSRSn

14.14.3.63 ADCPPBTRIP3FILCLKCTL Register (Offset = 94h) [Reset = 00000000h]

ADCPPBTRIP3FILCLKCTL is shown in Figure 14-141 and described in Table 14-124.

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ADCEVT3 Trip High Filter Prescale Control Register

Figure 14-141 ADCPPBTRIP3FILCLKCTL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																CLKPRESCALE
R-0h																R/W-0h

Table 14-124 ADCPPBTRIP3FILCLKCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	CLKPRESCALE	R/W	0h	ADCPPB3 filter sample clock prescale. The effective prescale value is (CLKPRESCALE + 1). This applies to the filter on both the high and low trips. Reset type: SYSRSn

14.14.3.64 ADCPPB4CONFIG Register (Offset = 9Ah) [Reset = 0003h]

ADCPPB4CONFIG is shown in Figure 14-142 and described in Table 14-125.

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ADC PPB{#} Config Register

Figure 14-142 ADCPPB4CONFIG Register

15	14	13	12	11	10	9	8
RESERVED							DELTAEN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
TWOSCOMPEN	ABSEN	CBCEN	RESERVED	CONFIG
R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-3h

Table 14-125 ADCPPB4CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8	DELTAEN	R/W	0h	ADC Post Processing Block 4 enable delta (difference) from last sample calcualtion. When set, the ADCPPB4RESULT register will contain the difference between the most recent conversion result and the last value that would have been loaded into the ADCPPB4RESULT (if the delta calculation wasn't enabled). The delta calculation occurs after OFFREF, TWOSCOMPEN, and ABSEN calculations are applied. 0 Delta calculation disabled: no modification to ADCPPB4RESULT 1 ADCPPB4RESULT = ADCPPB4RESULT'[t] - ADCPPB4RESULT'[t - 1] Where ADCPPB4RESULT' is the value that would have been loaded into ADCPPB4RESULT without delta calculation Reset type: SYSRSn
7	TWOSCOMPEN	R/W	0h	ADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB4RESULT register. 0 ADCPPB4RESULT = ADCRESULTx - ADCPPB4OFFREF 1 ADCPPB4RESULT = ADCPPB4OFFREF - ADCRESULTx Reset type: SYSRSn
6	ABSEN	R/W	0h	ADC Post Processing Block 4 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB4. This occurs before the TWOSCOMPEN logic is evaluated (so enabling both TWOSCOMPEN and ABSEN will always result in a negative value stored in ADCPPBxRESULT) 0 ADCPPB4RESULT = ADCRESULTx - ADCPPB4OFFREF 1 ADCPPB4RESULT = abs(ADCRESULTx - ADCPPB4OFFREF) Reset type: SYSRSn
5	CBCEN	R/W	0h	ADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present. Reset type: SYSRSn
4	RESERVED	R	0h	Reserved
3-0	CONFIG	R/W	3h	ADC Post Processing Block {#} Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block {#} 0001 SOC1/EOC1/RESULT1 is associated with post processing block {#} 0010 SOC2/EOC2/RESULT2 is associated with post processing block {#} 0011 SOC3/EOC3/RESULT3 is associated with post processing block {#} 0100 SOC4/EOC4/RESULT4 is associated with post processing block {#} 0101 SOC5/EOC5/RESULT5 is associated with post processing block {#} 0110 SOC6/EOC6/RESULT6 is associated with post processing block {#} 0111 SOC7/EOC7/RESULT7 is associated with post processing block {#} 1000 SOC8/EOC8/RESULT8 is associated with post processing block {#} 1001 SOC9/EOC9/RESULT9 is associated with post processing block {#} 1010 SOC10/EOC10/RESULT10 is associated with post processing block {#} 1011 SOC11/EOC11/RESULT11 is associated with post processing block {#} 1100 SOC12/EOC12/RESULT12 is associated with post processing block {#} 1101 SOC13/EOC13/RESULT13 is associated with post processing block {#} 1110 SOC14/EOC14/RESULT14 is associated with post processing block {#} 1111 SOC15/EOC15/RESULT15 is associated with post processing block {#} Reset type: SYSRSn

14.14.3.65 ADCPPB4STAMP Register (Offset = 9Bh) [Reset = 0000h]

ADCPPB4STAMP is shown in Figure 14-143 and described in Table 14-126.

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ADC PPB4 Sample Delay Time Stamp Register

Figure 14-143 ADCPPB4STAMP Register

15	14	13	12	11	10	9	8
RESERVED				DLYSTAMP
R-0h				R-0h

7	6	5	4	3	2	1	0
DLYSTAMP
R-0h

Table 14-126 ADCPPB4STAMP Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11-0	DLYSTAMP	R	0h	ADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field, thereby giving the number of system clock cycles delay between the SOC trigger and the actual start of the sample. Reset type: SYSRSn

14.14.3.66 ADCPPB4OFFCAL Register (Offset = 9Ch) [Reset = 0000h]

ADCPPB4OFFCAL is shown in Figure 14-144 and described in Table 14-127.

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ADC PPB4 Offset Calibration Register

Figure 14-144 ADCPPB4OFFCAL Register

15	14	13	12	11	10	9	8
RESERVED						OFFCAL
R-0h						R/W-0h

7	6	5	4	3	2	1	0
OFFCAL
R/W-0h

Table 14-127 ADCPPB4OFFCAL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	OFFCAL	R/W	0h	ADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register. 000h No change. The ADC output is stored directly into ADCRESULT. 001h ADC output - 1 is stored into ADCRESULT. 002h ADC output - 2 is stored into ADCRESULT. ... 200h ADC output + 512 is stored into ADCRESULT. ... 3FFh ADC output + 1 is stored into ADCRESULT. NOTE: In 16-bit mode, the subtraction will saturate at 0000h and FFFFh before being stored into the ADCRESULT register. In 12-bit mode, the subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register. Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied. Reset type: SYSRSn

14.14.3.67 ADCPPB4OFFREF Register (Offset = 9Dh) [Reset = 0000h]

ADCPPB4OFFREF is shown in Figure 14-145 and described in Table 14-128.

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ADC PPB4 Offset Reference Register

Figure 14-145 ADCPPB4OFFREF Register

15	14	13	12	11	10	9	8
OFFREF
R/W-0h

7	6	5	4	3	2	1	0
OFFREF
R/W-0h

Table 14-128 ADCPPB4OFFREF Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	OFFREF	R/W	0h	ADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB4RESULT register. This subtraction is not saturated. 0000h No change. The ADCRESULT value is passed on. 0001h ADCRESULT - 1 is passed on. 0002h ADCRESULT - 2 is passed on. ... 8000h ADCRESULT - 32,768 is passed on. ... FFFFh ADCRESULT - 65,535 is passed on. NOTE: In 12-bit mode the size of this register does not change from 16-bits. It is the user's responsibility to ensure that only a 12-bit value is written to this register when in 12-bit mode. Reset type: SYSRSn

14.14.3.68 ADCPPB4TRIPHI Register (Offset = 9Eh) [Reset = 00000000h]

ADCPPB4TRIPHI is shown in Figure 14-146 and described in Table 14-129.

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ADC PPB4 Trip High Register

Figure 14-146 ADCPPB4TRIPHI Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								LIMITHI
R-0h								R/W-0h

Table 14-129 ADCPPB4TRIPHI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	LIMITHI	R/W	0h	ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will be ignored in 12 bit mode Reset type: SYSRSn

14.14.3.69 ADCPPB4TRIPLO Register (Offset = A0h) [Reset = 00000000h]

ADCPPB4TRIPLO is shown in Figure 14-147 and described in Table 14-130.

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ADC PPB4 Trip Low/Trigger Time Stamp Register

Figure 14-147 ADCPPB4TRIPLO Register

31	30	29	28	27	26	25	24
REQSTAMP
R-0h

23	22	21	20	19	18	17	16
REQSTAMP				LIMITLO2EN	RESERVED		LSIGN
R-0h				R/W-0h	R-0h		R/W-0h

15	14	13	12	11	10	9	8
LIMITLO
R/W-0h

7	6	5	4	3	2	1	0
LIMITLO
R/W-0h

Table 14-130 ADCPPB4TRIPLO Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	REQSTAMP	R	0h	ADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field. Reset type: SYSRSn
19	LIMITLO2EN	R/W	0h	Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB4TRIPLO register. Not compatible with comparison with ADCPPB4PSUM or ADCPPB4SUM 1 = Low limit set by ADCPPB4TRIPLO2 register Reset type: SYSRSn
18-17	RESERVED	R	0h	Reserved
16	LSIGN	R/W	0h	Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode. Reset type: SYSRSn
15-0	LIMITLO	R/W	0h	ADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0 will be compared against bits 12:0 of the PPBRSULT bit field of the ADCPPB4RESULT register. Reset type: SYSRSn

14.14.3.70 ADCPPBTRIP4FILCTL Register (Offset = A2h) [Reset = 0000h]

ADCPPBTRIP4FILCTL is shown in Figure 14-148 and described in Table 14-131.

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ADCEVT4 Trip High Filter Control Register

Figure 14-148 ADCPPBTRIP4FILCTL Register

15	14	13	12	11	10	9	8
FILINIT	THRESH						SAMPWIN
R-0/W1S-0h	R/W-0h						R/W-0h

7	6	5	4	3	2	1	0
SAMPWIN					RESERVED	FILTLOEN	FILTHIEN
R/W-0h					R-0h	R/W-0h	R/W-0h

Table 14-131 ADCPPBTRIP4FILCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	FILINIT	R-0/W1S	0h	Trip filter initialization for PPB4. 0 No effect 1 Initialize all samples to the filter input value This applies to the filter on both the high and low trips. Reset type: SYSRSn
14-9	THRESH	R/W	0h	Trip filter majority voting threshold on PPB4. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1. This applies to the filter on both the high and low trips. Reset type: SYSRSn
8-3	SAMPWIN	R/W	0h	Trip filter sample window size on PPB4. Number of samples to monitor is SAMPWIN+1. This applies to the filter on both the high and low trips. Reset type: SYSRSn
2	RESERVED	R	0h	Reserved
1	FILTLOEN	R/W	0h	ADC PPB4 TRIPLO Filter Enable 0 No filtering of PPB 4 trip low limit events 1 PPB4 trip high limit event filtering enabled Reset type: SYSRSn
0	FILTHIEN	R/W	0h	ADC PPB4 TRIPHI Filter Enable 0 No filtering of PPB 4 trip high limit events 1 PPB4 trip high limit event filtering enabled Reset type: SYSRSn

14.14.3.71 ADCPPBTRIP4FILCLKCTL Register (Offset = A4h) [Reset = 00000000h]

ADCPPBTRIP4FILCLKCTL is shown in Figure 14-149 and described in Table 14-132.

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ADCEVT4 Trip High Filter Prescale Control Register

Figure 14-149 ADCPPBTRIP4FILCLKCTL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																CLKPRESCALE
R-0h																R/W-0h

Table 14-132 ADCPPBTRIP4FILCLKCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	CLKPRESCALE	R/W	0h	ADCPPB4 filter sample clock prescale. The effective prescale value is (CLKPRESCALE + 1). This applies to the filter on both the high and low trips. Reset type: SYSRSn

14.14.3.72 ADCINTCYCLE Register (Offset = B9h) [Reset = 0000h]

ADCINTCYCLE is shown in Figure 14-150 and described in Table 14-133.

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ADC Early Interrupt Generation Cycle

Figure 14-150 ADCINTCYCLE Register

15	14	13	12	11	10	9	8
DELAY
R/W-0h

7	6	5	4	3	2	1	0
DELAY
R/W-0h

Table 14-133 ADCINTCYCLE Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	DELAY	R/W	0h	ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles, for the interrupt to be generated. Reset type: SYSRSn

14.14.3.73 ADCINLTRIM1 Register (Offset = BAh) [Reset = 00000000h]

ADCINLTRIM1 is shown in Figure 14-151 and described in Table 14-134.

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ADC Linearity Trim 1 Register

Figure 14-151 ADCINLTRIM1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INLTRIM31TO0
R/W-0h

Table 14-134 ADCINLTRIM1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	INLTRIM31TO0	R/W	0h	ADC Linearity Trim Bits 31-0. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications. Reset type: XRSn

14.14.3.74 ADCINLTRIM2 Register (Offset = BCh) [Reset = 00000000h]

ADCINLTRIM2 is shown in Figure 14-152 and described in Table 14-135.

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ADC Linearity Trim 2 Register

Figure 14-152 ADCINLTRIM2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INLTRIM63TO32
R/W-0h

Table 14-135 ADCINLTRIM2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	INLTRIM63TO32	R/W	0h	ADC Linearity Trim Bits 63-32. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications. Reset type: XRSn

14.14.3.75 ADCINLTRIM3 Register (Offset = BEh) [Reset = 00000000h]

ADCINLTRIM3 is shown in Figure 14-153 and described in Table 14-136.

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ADC Linearity Trim 3 Register

Figure 14-153 ADCINLTRIM3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INLTRIM95TO64
R/W-0h

Table 14-136 ADCINLTRIM3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	INLTRIM95TO64	R/W	0h	ADC Linearity Trim Bits 95-64. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications. Reset type: XRSn

14.14.3.76 ADCINLTRIM4 Register (Offset = C0h) [Reset = 00000000h]

ADCINLTRIM4 is shown in Figure 14-154 and described in Table 14-137.

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design

Figure 14-154 ADCINLTRIM4 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INLTRIM127TO96
R/W-0h

Table 14-137 ADCINLTRIM4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	INLTRIM127TO96	R/W	0h	ADC Linearity Trim Bits 127-96. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications. Reset type: XRSn

14.14.3.77 ADCINLTRIM5 Register (Offset = C2h) [Reset = 00000000h]

ADCINLTRIM5 is shown in Figure 14-155 and described in Table 14-138.

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design

Figure 14-155 ADCINLTRIM5 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INLTRIM159TO128
R/W-0h

Table 14-138 ADCINLTRIM5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	INLTRIM159TO128	R/W	0h	ADC Linearity Trim Bits 159-128. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications. Reset type: XRSn

14.14.3.78 ADCINLTRIM6 Register (Offset = C4h) [Reset = 00000000h]

ADCINLTRIM6 is shown in Figure 14-156 and described in Table 14-139.

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design

Figure 14-156 ADCINLTRIM6 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INLTRIM191TO160
R/W-0h

Table 14-139 ADCINLTRIM6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	INLTRIM191TO160	R/W	0h	ADC Linearity Trim Bits 191-160. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications. Reset type: XRSn

14.14.3.79 ADCREV2 Register (Offset = C7h) [Reset = 0005h]

ADCREV2 is shown in Figure 14-157 and described in Table 14-140.

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ADC Wrapper Revision Register

Figure 14-157 ADCREV2 Register

15	14	13	12	11	10	9	8
WRAPPERREV
R-0h

7	6	5	4	3	2	1	0
WRAPPERTYPE
R-5h

Table 14-140 ADCREV2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	WRAPPERREV	R	0h	ADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h. Reset type: SYSRSn
7-0	WRAPPERTYPE	R	5h	ADC Wrapper Type. Always set to 5 forType 5 ADC Wrapper. Reset type: SYSRSn

14.14.3.80 REP1CTL Register (Offset = CAh) [Reset = 00000000h]

REP1CTL is shown in Figure 14-158 and described in Table 14-141.

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ADC Trigger Repeater 1 Control Register

Figure 14-158 REP1CTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
SWSYNC	RESERVED	SYNCINSEL
R-0/W1S-0h	R-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	TRIGGER
R-0h	R/W-0h

7	6	5	4	3	2	1	0
TRIGGEROVF	PHASEOVF	RESERVED	RESERVED	MODULEBUSY	RESERVED	ACTIVEMODE	MODE
R/W1C-0h	R/W1C-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R/W-0h

Table 14-141 REP1CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23	SWSYNC	R-0/W1S	0h	Trigger repeater 1 software force sync. On a sync. event, all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL, PHASE, and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared. Reset type: SYSRSn
22	RESERVED	R	0h	Reserved
21-16	SYNCINSEL	R/W	0h	Trigger repeater 1 sync. input select. On a sync. event, all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL, PHASE, and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared. Refer to SOC spec for more details Reset type: SYSRSn
15	RESERVED	R	0h	Reserved
14-8	TRIGGER	R/W	0h	ADC Trigger Repeater 1 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - CPU1 Timer 0, TINT0n 02h REPTRIG2 - CPU1 Timer 1, TINT1n 03h REPTRIG3 - CPU1 Timer 2, TINT2n 04h REPTRIG4 - GPIO, Input X-Bar INPUT5 05h REPTRIG5 - ePWM1, ADCSOCA 06h REPTRIG6 - ePWM1, ADCSOCB 07h REPTRIG7 - ePWM2, ADCSOCA 08h REPTRIG8 - ePWM2, ADCSOCB 09h REPTRIG9 - ePWM3, ADCSOCA 0Ah REPTRIG10 - ePWM3, ADCSOCB 0Bh REPTRIG11 - ePWM4, ADCSOCA 0Ch REPTRIG12 - ePWM4, ADCSOCB 0Dh REPTRIG13 - ePWM5, ADCSOCA 0Eh REPTRIG14 - ePWM5, ADCSOCB 0Fh REPTRIG15 - ePWM6, ADCSOCA 10h REPTRIG16 - ePWM6, ADCSOCB 11h REPTRIG17 - ePWM7, ADCSOCA 12h REPTRIG18 - ePWM7, ADCSOCB 13h REPTRIG19 - ePWM8, ADCSOCA 14h REPTRIG20 - ePWM8, ADCSOCB 15h REPTRIG21 - ePWM9, ADCSOCA 16h REPTRIG22 - ePWM9, ADCSOCB 17h REPTRIG23 - ePWM10, ADCSOCA 18h REPTRIG24 - ePWM10, ADCSOCB 19h REPTRIG25 - ePWM11, ADCSOCA 1Ah REPTRIG26 - ePWM11, ADCSOCB 1Bh REPTRIG27 - ePWM12, ADCSOCA 1Ch REPTRIG28 - ePWM12, ADCSOCB 1Dh REPTRIG29 - CPU2 Timer 0, TINT0n 1Eh REPTRIG30 - CPU2 Timer 1, TINT1n 1Fh REPTRIG31 - CPU2 Timer 2, TINT2n 20h - 4Fh - Reserved 50h REPTRIG80 eCAP1 51h REPTRIG81 eCAP2 52h REPTRIG82 eCAP3 53h REPTRIG83 eCAP4 54h REPTRIG84 eCAP5 55h REPTRIG85 eCAP6 56h REPTRIG86 eCAP7 57h REPTRIG87 eCAP8 58h REPTRIG88 - ePWM13, ADCSOCA 59h REPTRIG89 - ePWM13, ADCSOCB 5Ah REPTRIG90 - ePWM14, ADCSOCA 5Bh REPTRIG91 - ePWM14, ADCSOCB 5Ch REPTRIG92 - ePWM15, ADCSOCA 5Dh REPTRIG93 - ePWM15, ADCSOCB 5Eh REPTRIG94 - ePWM16, ADCSOCA 5Fh REPTRIG95 - ePWM16, ADCSOCB 60h REPTRIG96 - ePWM17, ADCSOCA 61h REPTRIG97 - ePWM17, ADCSOCB 62h REPTRIG98 - ePWM18, ADCSOCA 63h REPTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn
7	TRIGGEROVF	R/W1C	0h	ADC Trigger Repeater 1 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers (NCOUNT was not 0 or SOCs associated with Repeater 1 were still pending). Writing a 1 will clear this flag. Note: This flag won't be set in undersampling mode or when NSEL = 0 if a trigger arrives before the previous SOCs have completed, the trigger will be passed and the overflow flags of the SOCs that were still pending will be set. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn
6	PHASEOVF	R/W1C	0h	ADC Trigger Repeater 1 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger (PHASECOUNT was not 0). Writing a 1 will clear this flag. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	MODULEBUSY	R	0h	ADC Trigger Repeater 1 Module Busy indicator. In oversampling mode: 0 = Repeater 1 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 1 still has repeated triggers remaining (NCOUNT > 0) or associated SOCs are still pending (SOCBUSY is 1) If a new oversampled trigger is received while the module is still busy, the TRIGGEROVF bit will be set and the trigger will be ignored. Reset type: SYSRSn
2	RESERVED	R	0h	Reserved
1	ACTIVEMODE	R	0h	When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't cause any changes in functionality until the module becomes idle and then a new trigger is received. 0 = module is oversampling 1 = module is undersampling Reset type: SYSRSn
0	MODE	R/W	0h	ADC trigger repeater 1 mode selection. Select either oversampling or undersampling mode. In oversampling mode, when the trigger selected by REP1CTL.TRIGSEL is received, the repeater will repeat the trigger REP1N.NSEL + 1 times. In undersampling mode, when the trigger selected by REP1CTL.TRIGSEL is received the first time, the repeater will pass the trigger through. The next REP1N.NSEL triggers will be ignored. 0 = oversampling 1 = undersampling Reset type: SYSRSn

14.14.3.81 REP1N Register (Offset = CCh) [Reset = 00000000h]

REP1N is shown in Figure 14-159 and described in Table 14-142.

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ADC Trigger Repeater 1 N Select Register

Figure 14-159 REP1N Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED									NCOUNT							RESERVED									NSEL
R-0h									R-0h							R-0h									R/W-0h

Table 14-142 REP1N Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R	0h	Reserved
22-16	NCOUNT	R	0h	ADC trigger repeater 1 trigger count. In oversampling mode, indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP1CTL.TRIGSEL while NCOUNT is not 0 (the repeater is still busy generating the repeated triggers) then the trigger will be ignored and REP1CTL.TRIGOVF will be set to 1. In undersampling mode, indicates the number of triggers remaining to be supressed. Reset type: SYSRSn
15-7	RESERVED	R	0h	Reserved
6-0	NSEL	R/W	0h	ADC Trigger Repeater 1 selection of number of triggers. In oversampling mode, selects the number of repeated triggers. For each trigger received corresponding to REP1CTL.TRIGSEL, NSEL + 1 triggers will be generated. 0 = 1 trigger is generated (pass-through) 1 = 2 triggers are generated 2 = 3 triggers are generated ... 127 = 128 triggers are generated In undersampling mode, selects the number triggers to be supressed. 1 out NSEL + 1 triggers received corresponding to REP1CTL.TRIGSEL will be passed through (the first trigger will be passed through and the subsequent NSEL triggers will be supressed). 0 = all triggers are passed 1 = 1 out of 2 triggers are passed 2 = 1 out of 3 triggers are passed ... 127 = 1 out of 128 triggers are passed Reset type: SYSRSn

14.14.3.82 REP1PHASE Register (Offset = CEh) [Reset = 00000000h]

REP1PHASE is shown in Figure 14-160 and described in Table 14-143.

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ADC Trigger Repeater 1 Phase Select Register

Figure 14-160 REP1PHASE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PHASECOUNT																PHASE
R-0h																R/W-0h

Table 14-143 REP1PHASE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	PHASECOUNT	R	0h	ADC trigger repeater 1 phase delay status. When the trigger selected by REP1CTL.TRIGSEL is received, this register will start counting down from PHASECOUNT until the counter reaches 0, at which point the trigger will be passed on to the repeater re-trigger logic. If the trigger selected by REP1CTL.TRIGSEL is recieved when PHASECOUNT is not 0 (the phase delay logic is busy from the previous trigger) then the new trigger will be ignored and REP1CTL.PHASEOVF will be set to 1. Reset type: SYSRSn
15-0	PHASE	R/W	0h	ADC trigger repeater 1 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 = trigger is delayed by 2 SYSCLKs ... 65535 = trigger is delayed by 65535 SYSCLKs Reset type: SYSRSn

14.14.3.83 REP1SPREAD Register (Offset = D0h) [Reset = 00000000h]

REP1SPREAD is shown in Figure 14-161 and described in Table 14-144.

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ADC Trigger Repeater 1 Spread Select Register

Figure 14-161 REP1SPREAD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPREADCOUNT																SPREAD
R-0h																R/W-0h

Table 14-144 REP1SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	SPREADCOUNT	R	0h	ADC trigger repeater 1 spread status. When a trigger is sent to the ADC in oversampling mode, this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not occur until SPREADCOUNT is 0 (minimum time is complete) and REP1CTL.BUSY = 0 (SOCs associated with trigger repeater 1 are no longer pending). Reset type: SYSRSn
15-0	SPREAD	R/W	0h	ADC trigger repeater 1 spread delay configuration. In oversampling mode, defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with repeater 1 to sample and convert, then the repeater will generate triggers as fast as the ADC can convert the associated conversions. If SPREAD is greater than the time needed for all SOCs associated with repeater 1 to sample and convert, then repeated triggers to the ADC will be SPREAD SYSCLK cycles apart. 0 = oversampled repeated triggers occur as fast as the ADC can sample and convert associated SOCs 1 = time between repeated triggers is at least 1 SYSCLKs 2 = time between repeated triggers is at least 2 SYSCLKs ... 65535 = time between repeated triggers is at least 65535 SYSCLKs Reset type: SYSRSn

14.14.3.84 REP1FRC Register (Offset = D2h) [Reset = 0000h]

REP1FRC is shown in Figure 14-162 and described in Table 14-145.

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ADC Trigger Repeater 1 Software Force Register

Figure 14-162 REP1FRC Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							SWFRC
R-0h							R-0/W1S-0h

Table 14-145 REP1FRC Register Field Descriptions

Bit	Field	Type	Reset	Description
15-1	RESERVED	R	0h	Reserved
0	SWFRC	R-0/W1S	0h	Write 1 to force a trigger to repeat block 1 input regardless of the value of TRIGGER. Always reads 0. Reset type: SYSRSn

14.14.3.85 REP2CTL Register (Offset = DAh) [Reset = 00000000h]

REP2CTL is shown in Figure 14-163 and described in Table 14-146.

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ADC Trigger Repeater 2 Control Register

Figure 14-163 REP2CTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
SWSYNC	RESERVED	SYNCINSEL
R-0/W1S-0h	R-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	TRIGGER
R-0h	R/W-0h

7	6	5	4	3	2	1	0
TRIGGEROVF	PHASEOVF	RESERVED	RESERVED	MODULEBUSY	RESERVED	ACTIVEMODE	MODE
R/W1C-0h	R/W1C-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R/W-0h

Table 14-146 REP2CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23	SWSYNC	R-0/W1S	0h	Trigger repeater 2 software force sync. On a sync. event, all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL, PHASE, and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared. Reset type: SYSRSn
22	RESERVED	R	0h	Reserved
21-16	SYNCINSEL	R/W	0h	Trigger repeater 2 sync. input select. On a sync. event, all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL, PHASE, and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared. Refer to SOC spec for more details Reset type: SYSRSn
15	RESERVED	R	0h	Reserved
14-8	TRIGGER	R/W	0h	ADC Trigger Repeater 2 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - CPU1 Timer 0, TINT0n 02h REPTRIG2 - CPU1 Timer 1, TINT1n 03h REPTRIG3 - CPU1 Timer 2, TINT2n 04h REPTRIG4 - GPIO, Input X-Bar INPUT5 05h REPTRIG5 - ePWM1, ADCSOCA 06h REPTRIG6 - ePWM1, ADCSOCB 07h REPTRIG7 - ePWM2, ADCSOCA 08h REPTRIG8 - ePWM2, ADCSOCB 09h REPTRIG9 - ePWM3, ADCSOCA 0Ah REPTRIG10 - ePWM3, ADCSOCB 0Bh REPTRIG11 - ePWM4, ADCSOCA 0Ch REPTRIG12 - ePWM4, ADCSOCB 0Dh REPTRIG13 - ePWM5, ADCSOCA 0Eh REPTRIG14 - ePWM5, ADCSOCB 0Fh REPTRIG15 - ePWM6, ADCSOCA 10h REPTRIG16 - ePWM6, ADCSOCB 11h REPTRIG17 - ePWM7, ADCSOCA 12h REPTRIG18 - ePWM7, ADCSOCB 13h REPTRIG19 - ePWM8, ADCSOCA 14h REPTRIG20 - ePWM8, ADCSOCB 15h REPTRIG21 - ePWM9, ADCSOCA 16h REPTRIG22 - ePWM9, ADCSOCB 17h REPTRIG23 - ePWM10, ADCSOCA 18h REPTRIG24 - ePWM10, ADCSOCB 19h REPTRIG25 - ePWM11, ADCSOCA 1Ah REPTRIG26 - ePWM11, ADCSOCB 1Bh REPTRIG27 - ePWM12, ADCSOCA 1Ch REPTRIG28 - ePWM12, ADCSOCB 1Dh REPTRIG29 - CPU2 Timer 0, TINT0n 1Eh REPTRIG30 - CPU2 Timer 1, TINT1n 1Fh REPTRIG31 - CPU2 Timer 2, TINT2n 20h - 4Fh - Reserved 50h REPTRIG80 eCAP1 51h REPTRIG81 eCAP2 52h REPTRIG82 eCAP3 53h REPTRIG83 eCAP4 54h REPTRIG84 eCAP5 55h REPTRIG85 eCAP6 56h REPTRIG86 eCAP7 57h REPTRIG87 eCAP8 58h REPTRIG88 - ePWM13, ADCSOCA 59h REPTRIG89 - ePWM13, ADCSOCB 5Ah REPTRIG90 - ePWM14, ADCSOCA 5Bh REPTRIG91 - ePWM14, ADCSOCB 5Ch REPTRIG92 - ePWM15, ADCSOCA 5Dh REPTRIG93 - ePWM15, ADCSOCB 5Eh REPTRIG94 - ePWM16, ADCSOCA 5Fh REPTRIG95 - ePWM16, ADCSOCB 60h REPTRIG96 - ePWM17, ADCSOCA 61h REPTRIG97 - ePWM17, ADCSOCB 62h REPTRIG98 - ePWM18, ADCSOCA 63h REPTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn
7	TRIGGEROVF	R/W1C	0h	ADC Trigger Repeater 2 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers (NCOUNT was not 0 or SOCs associated with Repeater 2 were still pending). Writing a 1 will clear this flag. Note: This flag won't be set in undersampling mode or when NSEL = 0 if a trigger arrives before the previous SOCs have completed, the trigger will be passed and the overflow flags of the SOCs that were still pending will be set. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn
6	PHASEOVF	R/W1C	0h	ADC Trigger Repeater 2 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger (PHASECOUNT was not 0). Writing a 1 will clear this flag. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	MODULEBUSY	R	0h	ADC Trigger Repeater 2 Module Busy indicator. In oversampling mode: 0 = Repeater 2 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 2 still has repeated triggers remaining (NCOUNT > 0) or associated SOCs are still pending (SOCBUSY is 1) If a new oversampled trigger is received while the module is still busy, the TRIGGEROVF bit will be set and the trigger will be ignored. Reset type: SYSRSn
2	RESERVED	R	0h	Reserved
1	ACTIVEMODE	R	0h	When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't cause any changes in functionality until the module becomes idle and then a new trigger is received. 0 = module is oversampling 1 = module is undersampling Reset type: SYSRSn
0	MODE	R/W	0h	ADC trigger repeater 2 mode selection. Select either oversampling or undersampling mode. In oversampling mode, when the trigger selected by REP2CTL.TRIGSEL is received, the repeater will repeat the trigger REP2N.NSEL + 1 times. In undersampling mode, when the trigger selected by REP2CTL.TRIGSEL is received the first time, the repeater will pass the trigger through. The next REP2N.NSEL triggers will be ignored. 0 = oversampling 1 = undersampling Reset type: SYSRSn

14.14.3.86 REP2N Register (Offset = DCh) [Reset = 00000000h]

REP2N is shown in Figure 14-164 and described in Table 14-147.

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ADC Trigger Repeater 2 N Select Register

Figure 14-164 REP2N Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED									NCOUNT							RESERVED									NSEL
R-0h									R-0h							R-0h									R/W-0h

Table 14-147 REP2N Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R	0h	Reserved
22-16	NCOUNT	R	0h	ADC trigger repeater 2 trigger count. In oversampling mode, indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP2CTL.TRIGSEL while NCOUNT is not 0 (the repeater is still busy generating the repeated triggers) then the trigger will be ignored and REP2CTL.TRIGOVF will be set to 1. In undersampling mode, indicates the number of triggers remaining to be supressed. Reset type: SYSRSn
15-7	RESERVED	R	0h	Reserved
6-0	NSEL	R/W	0h	ADC Trigger Repeater 2 selection of number of triggers. In oversampling mode, selects the number of repeated triggers. For each trigger received corresponding to REP2CTL.TRIGSEL, NSEL + 1 triggers will be generated. 0 = 1 trigger is generated (pass-through) 1 = 2 triggers are generated 2 = 3 triggers are generated ... 127 = 128 triggers are generated In undersampling mode, selects the number triggers to be supressed. 1 out NSEL + 1 triggers received corresponding to REP2CTL.TRIGSEL will be passed through (the first trigger will be passed through and the subsequent NSEL triggers will be supressed). 0 = all triggers are passed 1 = 1 out of 2 triggers are passed 2 = 1 out of 3 triggers are passed ... 127 = 1 out of 128 triggers are passed Reset type: SYSRSn

14.14.3.87 REP2PHASE Register (Offset = DEh) [Reset = 00000000h]

REP2PHASE is shown in Figure 14-165 and described in Table 14-148.

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ADC Trigger Repeater 2 Phase Select Register

Figure 14-165 REP2PHASE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PHASECOUNT																PHASE
R-0h																R/W-0h

Table 14-148 REP2PHASE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	PHASECOUNT	R	0h	ADC trigger repeater 2 phase delay status. When the trigger selected by REP2CTL.TRIGSEL is received, this register will start counting down from PHASECOUNT until the counter reaches 0, at which point the trigger will be passed on to the repeater re-trigger logic. If the trigger selected by REP2CTL.TRIGSEL is recieved when PHASECOUNT is not 0 (the phase delay logic is busy from the previous trigger) then the new trigger will be ignored and REP2CTL.PHASEOVF will be set to 1. Reset type: SYSRSn
15-0	PHASE	R/W	0h	ADC trigger repeater 2 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 = trigger is delayed by 2 SYSCLKs ... 65535 = trigger is delayed by 65535 SYSCLKs Reset type: SYSRSn

14.14.3.88 REP2SPREAD Register (Offset = E0h) [Reset = 00000000h]

REP2SPREAD is shown in Figure 14-166 and described in Table 14-149.

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ADC Trigger Repeater 2 Spread Select Register

Figure 14-166 REP2SPREAD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPREADCOUNT																SPREAD
R-0h																R/W-0h

Table 14-149 REP2SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	SPREADCOUNT	R	0h	ADC trigger repeater 2 spread status. When a trigger is sent to the ADC in oversampling mode, this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not occur until SPREADCOUNT is 0 (minimum time is complete) and REP2CTL.BUSY = 0 (SOCs associated with trigger repeater 2 are no longer pending). Reset type: SYSRSn
15-0	SPREAD	R/W	0h	ADC trigger repeater 2 spread delay configuration. In oversampling mode, defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with repeater 2 to sample and convert, then the repeater will generate triggers as fast as the ADC can convert the associated conversions. If SPREAD is greater than the time needed for all SOCs associated with repeater 2 to sample and convert, then repeated triggers to the ADC will be SPREAD SYSCLK cycles apart. 0 = oversampled repeated triggers occur as fast as the ADC can sample and convert associated SOCs 1 = time between repeated triggers is at least 1 SYSCLKs 2 = time between repeated triggers is at least 2 SYSCLKs ... 65535 = time between repeated triggers is at least 65535 SYSCLKs Reset type: SYSRSn

14.14.3.89 REP2FRC Register (Offset = E2h) [Reset = 0000h]

REP2FRC is shown in Figure 14-167 and described in Table 14-150.

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ADC Trigger Repeater 2 Software Force Register

Figure 14-167 REP2FRC Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							SWFRC
R-0h							R-0/W1S-0h

Table 14-150 REP2FRC Register Field Descriptions

Bit	Field	Type	Reset	Description
15-1	RESERVED	R	0h	Reserved
0	SWFRC	R-0/W1S	0h	Write 1 to force a trigger to repeat block 2 input regardless of the value of TRIGGER. Always reads 0. Reset type: SYSRSn

14.14.3.90 ADCPPB1LIMIT Register (Offset = EAh) [Reset = 0000h]

ADCPPB1LIMIT is shown in Figure 14-168 and described in Table 14-151.

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ADC PPB1Conversion Count Limit Register

Figure 14-168 ADCPPB1LIMIT Register

15	14	13	12	11	10	9	8
RESERVED						LIMIT
R-0h						R/W-0h

7	6	5	4	3	2	1	0
LIMIT
R/W-0h

Table 14-151 ADCPPB1LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	LIMIT	R/W	0h	Post Processing Block 1 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing, do not write a value larger than 128 when the ADC is operating in 16-bit mode. Reset type: SYSRSn

14.14.3.91 ADCPPBP1PCOUNT Register (Offset = ECh) [Reset = 0000h]

ADCPPBP1PCOUNT is shown in Figure 14-169 and described in Table 14-152.

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ADC PPB1 Partial Conversion Count Register

Figure 14-169 ADCPPBP1PCOUNT Register

15	14	13	12	11	10	9	8
RESERVED						PCOUNT
R-0h						R-0h

7	6	5	4	3	2	1	0
PCOUNT
R-0h

Table 14-152 ADCPPBP1PCOUNT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	PCOUNT	R	0h	Post Processing Block 1 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB1PSUM this register is incremented by 1. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information). Reset type: SYSRSn

14.14.3.92 ADCPPB1CONFIG2 Register (Offset = EEh) [Reset = 0000h]

ADCPPB1CONFIG2 is shown in Figure 14-170 and described in Table 14-153.

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ADC PPB1 Sum Shift Register

Figure 14-170 ADCPPB1CONFIG2 Register

15	14	13	12	11	10	9	8
COMPSEL		RESERVED	OSINTSEL	SWSYNC	RESERVED	SYNCINSEL
R/W-0h		R-0h	R/W-0h	R-0/W1S-0h	R-0h	R/W-0h

7	6	5	4	3	2	1	0
SYNCINSEL				SHIFT
R/W-0h				R/W-0h

Table 14-153 ADCPPB1CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	COMPSEL	R/W	0h	Post Processing Block 1 Compare Source Select. This field determines whether ADCPPB1RESULT, ADCPPB1PSUM, or ADCPPB1SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB1RESULT is used for compare logic 01 = ADCPPB1PSUM is used for compare logic 10 = ADCPPB1SUM is used for compare logic 11 = Reserved Note: when ADCPPB1PSUM is selected as the compare source and when a LIMIT match occurs (ADCPPB1LIMIT equals ADCPPB1COUNT) the ADCPPB1PSUM register will be cleared and the final sum will be loaded into ADCPPB1SUM. For this sample, the final sum, ADCPPB1SUM will be used for the compariosn instead of ADCPPB1PSUM. Reset type: SYSRSn
13	RESERVED	R	0h	Reserved
12	OSINTSEL	R/W	0h	Post Processing Block 1 Interrupt Source Select. OSINT1 can be used to trigger an ADC interrupt (ADCINT1 through ADCINT4) via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT1 in addition to a PCOUNT = LIMIT event. 0 = OSINT1 will be generated from PCOUNT = LIMIT only 1 = OSTIN1 will be generated form PCOUNT = LIMIT or a sync. event. Note: If a SYNC event would cause an OSINT one cycle after OSINT would have been cause by PCOUNT = LIMIT match, then the second OSINT is ignored. Reset type: SYSRSn
11	SWSYNC	R-0/W1S	0h	PPB 1 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur. Reset type: SYSRSn
10	RESERVED	R	0h	Reserved
9-4	SYNCINSEL	R/W	0h	PPB 1 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details Reset type: SYSRSn
3-0	SHIFT	R/W	0h	Post Processing Block 1 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM >> 1 2 : SUM = PSUM >> 2 ... 10 : SUM = PSUM >> 10 11 - 15 : Reserved Reset type: SYSRSn

14.14.3.93 ADCPPB1PSUM Register (Offset = F0h) [Reset = 00000000h]

ADCPPB1PSUM is shown in Figure 14-171 and described in Table 14-154.

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ADC PPB1 Partial Sum Register

Figure 14-171 ADCPPB1PSUM Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN								PSUM
R-0h								R-0h

Table 14-154 ADCPPB1PSUM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 23. Reset type: SYSRSn
23-0	PSUM	R	0h	Post Processing Block 1 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result is subsequently accumulated into this register. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 SYSCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 SYSCLK cycles (refer to the TRM for detailed timing information). Reset type: SYSRSn

14.14.3.94 ADCPPB1PMAX Register (Offset = F2h) [Reset = 00000000h]

ADCPPB1PMAX is shown in Figure 14-172 and described in Table 14-155.

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ADC PPB1 Partial Max Register

Figure 14-172 ADCPPB1PMAX Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN															PMAX
R-0h															R-0h

Table 14-155 ADCPPB1PMAX Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn
16-0	PMAX	R	0h	Post Processing Block 1 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is larger. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information). Reset type: SYSRSn

14.14.3.95 ADCPPB1PMAXI Register (Offset = F4h) [Reset = 0000h]

ADCPPB1PMAXI is shown in Figure 14-173 and described in Table 14-156.

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ADC PPB1 Partial Max Index Register

Figure 14-173 ADCPPB1PMAXI Register

15	14	13	12	11	10	9	8
RESERVED						PMAXI
R-0h						R-0h

7	6	5	4	3	2	1	0
PMAXI
R-0h

Table 14-156 ADCPPB1PMAXI Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	PMAXI	R	0h	Post Processing Block 1 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information). Reset type: SYSRSn

14.14.3.96 ADCPPB1PMIN Register (Offset = F6h) [Reset = 00000000h]

ADCPPB1PMIN is shown in Figure 14-174 and described in Table 14-157.

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ADC PPB1 Partial MIN Register

Figure 14-174 ADCPPB1PMIN Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN															PMIN
R-0h															R-0h

Table 14-157 ADCPPB1PMIN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn
16-0	PMIN	R	0h	Post Processing Block 1 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is smaller. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information). Reset type: SYSRSn

14.14.3.97 ADCPPB1PMINI Register (Offset = F8h) [Reset = 0000h]

ADCPPB1PMINI is shown in Figure 14-175 and described in Table 14-158.

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ADC PPB1 Partial Min Index Register

Figure 14-175 ADCPPB1PMINI Register

15	14	13	12	11	10	9	8
RESERVED						PMINI
R-0h						R-0h

7	6	5	4	3	2	1	0
PMINI
R-0h

Table 14-158 ADCPPB1PMINI Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	PMINI	R	0h	Post Processing Block 1 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information). Reset type: SYSRSn

14.14.3.98 ADCPPB1TRIPLO2 Register (Offset = FAh) [Reset = 00000000h]

ADCPPB1TRIPLO2 is shown in Figure 14-176 and described in Table 14-159.

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ADC PPB1 Extended Trip Low Register

Figure 14-176 ADCPPB1TRIPLO2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								LIMITLO
R-0h								R/W-0h

Table 14-159 ADCPPB1TRIPLO2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	LIMITLO	R/W	0h	ADC Post Processing Block 1 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB1TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPLO2[23:17] will be ignored in 16 bit mode - TRIPLO2[23:13] will be ignored in 12 bit mode Reset type: SYSRSn

14.14.3.99 ADCPPB2LIMIT Register (Offset = 104h) [Reset = 0000h]

ADCPPB2LIMIT is shown in Figure 14-177 and described in Table 14-160.

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ADC PPB2Conversion Count Limit Register

Figure 14-177 ADCPPB2LIMIT Register

15	14	13	12	11	10	9	8
RESERVED						LIMIT
R-0h						R/W-0h

7	6	5	4	3	2	1	0
LIMIT
R/W-0h

Table 14-160 ADCPPB2LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	LIMIT	R/W	0h	Post Processing Block 2 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing, do not write a value larger than 128 when the ADC is operating in 16-bit mode. Reset type: SYSRSn

14.14.3.100 ADCPPBP2PCOUNT Register (Offset = 106h) [Reset = 0000h]

ADCPPBP2PCOUNT is shown in Figure 14-178 and described in Table 14-161.

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ADC PPB2 Partial Conversion Count Register

Figure 14-178 ADCPPBP2PCOUNT Register

15	14	13	12	11	10	9	8
RESERVED						PCOUNT
R-0h						R-0h

7	6	5	4	3	2	1	0
PCOUNT
R-0h

Table 14-161 ADCPPBP2PCOUNT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	PCOUNT	R	0h	Post Processing Block 2 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB2PSUM this register is incremented by 1. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information). Reset type: SYSRSn

14.14.3.101 ADCPPB2CONFIG2 Register (Offset = 108h) [Reset = 0000h]

ADCPPB2CONFIG2 is shown in Figure 14-179 and described in Table 14-162.

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ADC PPB2 Sum Shift Register

Figure 14-179 ADCPPB2CONFIG2 Register

15	14	13	12	11	10	9	8
COMPSEL		RESERVED	OSINTSEL	SWSYNC	RESERVED	SYNCINSEL
R/W-0h		R-0h	R/W-0h	R-0/W1S-0h	R-0h	R/W-0h

7	6	5	4	3	2	1	0
SYNCINSEL				SHIFT
R/W-0h				R/W-0h

Table 14-162 ADCPPB2CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	COMPSEL	R/W	0h	Post Processing Block 2 Compare Source Select. This field determines whether ADCPPB2RESULT, ADCPPB2PSUM, or ADCPPB2SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB2RESULT is used for compare logic 01 = ADCPPB2PSUM is used for compare logic 10 = ADCPPB2SUM is used for compare logic 11 = Reserved Note: when ADCPPB2PSUM is selected as the compare source and when a LIMIT match occurs (ADCPPB2LIMIT equals ADCPPB2COUNT) the ADCPPB2PSUM register will be cleared and the final sum will be loaded into ADCPPB2SUM. For this sample, the final sum, ADCPPB2SUM will be used for the compariosn instead of ADCPPB2PSUM. Reset type: SYSRSn
13	RESERVED	R	0h	Reserved
12	OSINTSEL	R/W	0h	Post Processing Block 2 Interrupt Source Select. OSINT2 can be used to trigger an ADC interrupt (ADCINT1 through ADCINT4) via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT2 in addition to a PCOUNT = LIMIT event. 0 = OSINT2 will be generated from PCOUNT = LIMIT only 1 = OSTIN2 will be generated form PCOUNT = LIMIT or a sync. event. Note: If a SYNC event would cause an OSINT one cycle after OSINT would have been cause by PCOUNT = LIMIT match, then the second OSINT is ignored. Reset type: SYSRSn
11	SWSYNC	R-0/W1S	0h	PPB 2 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur. Reset type: SYSRSn
10	RESERVED	R	0h	Reserved
9-4	SYNCINSEL	R/W	0h	PPB 2 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details Reset type: SYSRSn
3-0	SHIFT	R/W	0h	Post Processing Block 2 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM >> 1 2 : SUM = PSUM >> 2 ... 10 : SUM = PSUM >> 10 11 - 15 : Reserved Reset type: SYSRSn

14.14.3.102 ADCPPB2PSUM Register (Offset = 10Ah) [Reset = 00000000h]

ADCPPB2PSUM is shown in Figure 14-180 and described in Table 14-163.

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ADC PPB2 Partial Sum Register

Figure 14-180 ADCPPB2PSUM Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN								PSUM
R-0h								R-0h

Table 14-163 ADCPPB2PSUM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 23. Reset type: SYSRSn
23-0	PSUM	R	0h	Post Processing Block 2 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result is subsequently accumulated into this register. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 SYSCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 SYSCLK cycles (refer to the TRM for detailed timing information). Reset type: SYSRSn

14.14.3.103 ADCPPB2PMAX Register (Offset = 10Ch) [Reset = 00000000h]

ADCPPB2PMAX is shown in Figure 14-181 and described in Table 14-164.

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ADC PPB2 Partial Max Register

Figure 14-181 ADCPPB2PMAX Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN															PMAX
R-0h															R-0h

Table 14-164 ADCPPB2PMAX Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn
16-0	PMAX	R	0h	Post Processing Block 2 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is larger. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information). Reset type: SYSRSn

14.14.3.104 ADCPPB2PMAXI Register (Offset = 10Eh) [Reset = 0000h]

ADCPPB2PMAXI is shown in Figure 14-182 and described in Table 14-165.

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ADC PPB2 Partial Max Index Register

Figure 14-182 ADCPPB2PMAXI Register

15	14	13	12	11	10	9	8
RESERVED						PMAXI
R-0h						R-0h

7	6	5	4	3	2	1	0
PMAXI
R-0h

Table 14-165 ADCPPB2PMAXI Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	PMAXI	R	0h	Post Processing Block 2 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information). Reset type: SYSRSn

14.14.3.105 ADCPPB2PMIN Register (Offset = 110h) [Reset = 00000000h]

ADCPPB2PMIN is shown in Figure 14-183 and described in Table 14-166.

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ADC PPB2 Partial MIN Register

Figure 14-183 ADCPPB2PMIN Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN															PMIN
R-0h															R-0h

Table 14-166 ADCPPB2PMIN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn
16-0	PMIN	R	0h	Post Processing Block 2 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is smaller. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information). Reset type: SYSRSn

14.14.3.106 ADCPPB2PMINI Register (Offset = 112h) [Reset = 0000h]

ADCPPB2PMINI is shown in Figure 14-184 and described in Table 14-167.

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ADC PPB2 Partial Min Index Register

Figure 14-184 ADCPPB2PMINI Register

15	14	13	12	11	10	9	8
RESERVED						PMINI
R-0h						R-0h

7	6	5	4	3	2	1	0
PMINI
R-0h

Table 14-167 ADCPPB2PMINI Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	PMINI	R	0h	Post Processing Block 2 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information). Reset type: SYSRSn

14.14.3.107 ADCPPB2TRIPLO2 Register (Offset = 114h) [Reset = 00000000h]

ADCPPB2TRIPLO2 is shown in Figure 14-185 and described in Table 14-168.

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ADC PPB2 Extended Trip Low Register

Figure 14-185 ADCPPB2TRIPLO2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								LIMITLO
R-0h								R/W-0h

Table 14-168 ADCPPB2TRIPLO2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	LIMITLO	R/W	0h	ADC Post Processing Block 2 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB2TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPLO2[23:17] will be ignored in 16 bit mode - TRIPLO2[23:13] will be ignored in 12 bit mode Reset type: SYSRSn

14.14.3.108 ADCPPB3LIMIT Register (Offset = 11Eh) [Reset = 0000h]

ADCPPB3LIMIT is shown in Figure 14-186 and described in Table 14-169.

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ADC PPB3Conversion Count Limit Register

Figure 14-186 ADCPPB3LIMIT Register

15	14	13	12	11	10	9	8
RESERVED						LIMIT
R-0h						R/W-0h

7	6	5	4	3	2	1	0
LIMIT
R/W-0h

Table 14-169 ADCPPB3LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	LIMIT	R/W	0h	Post Processing Block 3 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing, do not write a value larger than 128 when the ADC is operating in 16-bit mode. Reset type: SYSRSn

14.14.3.109 ADCPPBP3PCOUNT Register (Offset = 120h) [Reset = 0000h]

ADCPPBP3PCOUNT is shown in Figure 14-187 and described in Table 14-170.

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ADC PPB3 Partial Conversion Count Register

Figure 14-187 ADCPPBP3PCOUNT Register

15	14	13	12	11	10	9	8
RESERVED						PCOUNT
R-0h						R-0h

7	6	5	4	3	2	1	0
PCOUNT
R-0h

Table 14-170 ADCPPBP3PCOUNT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	PCOUNT	R	0h	Post Processing Block 3 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB3PSUM this register is incremented by 1. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information). Reset type: SYSRSn

14.14.3.110 ADCPPB3CONFIG2 Register (Offset = 122h) [Reset = 0000h]

ADCPPB3CONFIG2 is shown in Figure 14-188 and described in Table 14-171.

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ADC PPB3 Sum Shift Register

Figure 14-188 ADCPPB3CONFIG2 Register

15	14	13	12	11	10	9	8
COMPSEL		RESERVED	OSINTSEL	SWSYNC	RESERVED	SYNCINSEL
R/W-0h		R-0h	R/W-0h	R-0/W1S-0h	R-0h	R/W-0h

7	6	5	4	3	2	1	0
SYNCINSEL				SHIFT
R/W-0h				R/W-0h

Table 14-171 ADCPPB3CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	COMPSEL	R/W	0h	Post Processing Block 3 Compare Source Select. This field determines whether ADCPPB3RESULT, ADCPPB3PSUM, or ADCPPB3SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB3RESULT is used for compare logic 01 = ADCPPB3PSUM is used for compare logic 10 = ADCPPB3SUM is used for compare logic 11 = Reserved Note: when ADCPPB3PSUM is selected as the compare source and when a LIMIT match occurs (ADCPPB3LIMIT equals ADCPPB3COUNT) the ADCPPB3PSUM register will be cleared and the final sum will be loaded into ADCPPB3SUM. For this sample, the final sum, ADCPPB3SUM will be used for the compariosn instead of ADCPPB3PSUM. Reset type: SYSRSn
13	RESERVED	R	0h	Reserved
12	OSINTSEL	R/W	0h	Post Processing Block 3 Interrupt Source Select. OSINT3 can be used to trigger an ADC interrupt (ADCINT1 through ADCINT4) via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT3 in addition to a PCOUNT = LIMIT event. 0 = OSINT3 will be generated from PCOUNT = LIMIT only 1 = OSTIN3 will be generated form PCOUNT = LIMIT or a sync. event. Note: If a SYNC event would cause an OSINT one cycle after OSINT would have been cause by PCOUNT = LIMIT match, then the second OSINT is ignored. Reset type: SYSRSn
11	SWSYNC	R-0/W1S	0h	PPB 3 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur. Reset type: SYSRSn
10	RESERVED	R	0h	Reserved
9-4	SYNCINSEL	R/W	0h	PPB 3 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details Reset type: SYSRSn
3-0	SHIFT	R/W	0h	Post Processing Block 3 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM >> 1 2 : SUM = PSUM >> 2 ... 10 : SUM = PSUM >> 10 11 - 15 : Reserved Reset type: SYSRSn

14.14.3.111 ADCPPB3PSUM Register (Offset = 124h) [Reset = 00000000h]

ADCPPB3PSUM is shown in Figure 14-189 and described in Table 14-172.

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ADC PPB3 Partial Sum Register

Figure 14-189 ADCPPB3PSUM Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN								PSUM
R-0h								R-0h

Table 14-172 ADCPPB3PSUM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 23. Reset type: SYSRSn
23-0	PSUM	R	0h	Post Processing Block 3 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result is subsequently accumulated into this register. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 SYSCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 SYSCLK cycles (refer to the TRM for detailed timing information). Reset type: SYSRSn

14.14.3.112 ADCPPB3PMAX Register (Offset = 126h) [Reset = 00000000h]

ADCPPB3PMAX is shown in Figure 14-190 and described in Table 14-173.

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ADC PPB3 Partial Max Register

Figure 14-190 ADCPPB3PMAX Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN															PMAX
R-0h															R-0h

Table 14-173 ADCPPB3PMAX Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn
16-0	PMAX	R	0h	Post Processing Block 3 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is larger. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information). Reset type: SYSRSn

14.14.3.113 ADCPPB3PMAXI Register (Offset = 128h) [Reset = 0000h]

ADCPPB3PMAXI is shown in Figure 14-191 and described in Table 14-174.

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ADC PPB3 Partial Max Index Register

Figure 14-191 ADCPPB3PMAXI Register

15	14	13	12	11	10	9	8
RESERVED						PMAXI
R-0h						R-0h

7	6	5	4	3	2	1	0
PMAXI
R-0h

Table 14-174 ADCPPB3PMAXI Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	PMAXI	R	0h	Post Processing Block 3 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information). Reset type: SYSRSn

14.14.3.114 ADCPPB3PMIN Register (Offset = 12Ah) [Reset = 00000000h]

ADCPPB3PMIN is shown in Figure 14-192 and described in Table 14-175.

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ADC PPB3 Partial MIN Register

Figure 14-192 ADCPPB3PMIN Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN															PMIN
R-0h															R-0h

Table 14-175 ADCPPB3PMIN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn
16-0	PMIN	R	0h	Post Processing Block 3 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is smaller. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information). Reset type: SYSRSn

14.14.3.115 ADCPPB3PMINI Register (Offset = 12Ch) [Reset = 0000h]

ADCPPB3PMINI is shown in Figure 14-193 and described in Table 14-176.

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ADC PPB3 Partial Min Index Register

Figure 14-193 ADCPPB3PMINI Register

15	14	13	12	11	10	9	8
RESERVED						PMINI
R-0h						R-0h

7	6	5	4	3	2	1	0
PMINI
R-0h

Table 14-176 ADCPPB3PMINI Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	PMINI	R	0h	Post Processing Block 3 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information). Reset type: SYSRSn

14.14.3.116 ADCPPB3TRIPLO2 Register (Offset = 12Eh) [Reset = 00000000h]

ADCPPB3TRIPLO2 is shown in Figure 14-194 and described in Table 14-177.

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ADC PPB3 Extended Trip Low Register

Figure 14-194 ADCPPB3TRIPLO2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								LIMITLO
R-0h								R/W-0h

Table 14-177 ADCPPB3TRIPLO2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	LIMITLO	R/W	0h	ADC Post Processing Block 3 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB3TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPLO2[23:17] will be ignored in 16 bit mode - TRIPLO2[23:13] will be ignored in 12 bit mode Reset type: SYSRSn

14.14.3.117 ADCPPB4LIMIT Register (Offset = 138h) [Reset = 0000h]

ADCPPB4LIMIT is shown in Figure 14-195 and described in Table 14-178.

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ADC PPB4Conversion Count Limit Register

Figure 14-195 ADCPPB4LIMIT Register

15	14	13	12	11	10	9	8
RESERVED						LIMIT
R-0h						R/W-0h

7	6	5	4	3	2	1	0
LIMIT
R/W-0h

Table 14-178 ADCPPB4LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	LIMIT	R/W	0h	Post Processing Block 4 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing, do not write a value larger than 128 when the ADC is operating in 16-bit mode. Reset type: SYSRSn

14.14.3.118 ADCPPBP4PCOUNT Register (Offset = 13Ah) [Reset = 0000h]

ADCPPBP4PCOUNT is shown in Figure 14-196 and described in Table 14-179.

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ADC PPB4 Partial Conversion Count Register

Figure 14-196 ADCPPBP4PCOUNT Register

15	14	13	12	11	10	9	8
RESERVED						PCOUNT
R-0h						R-0h

7	6	5	4	3	2	1	0
PCOUNT
R-0h

Table 14-179 ADCPPBP4PCOUNT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	PCOUNT	R	0h	Post Processing Block 4 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB4PSUM this register is incremented by 1. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information). Reset type: SYSRSn

14.14.3.119 ADCPPB4CONFIG2 Register (Offset = 13Ch) [Reset = 0000h]

ADCPPB4CONFIG2 is shown in Figure 14-197 and described in Table 14-180.

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ADC PPB4 Sum Shift Register

Figure 14-197 ADCPPB4CONFIG2 Register

15	14	13	12	11	10	9	8
COMPSEL		RESERVED	OSINTSEL	SWSYNC	RESERVED	SYNCINSEL
R/W-0h		R-0h	R/W-0h	R-0/W1S-0h	R-0h	R/W-0h

7	6	5	4	3	2	1	0
SYNCINSEL				SHIFT
R/W-0h				R/W-0h

Table 14-180 ADCPPB4CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	COMPSEL	R/W	0h	Post Processing Block 4 Compare Source Select. This field determines whether ADCPPB4RESULT, ADCPPB4PSUM, or ADCPPB4SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB4RESULT is used for compare logic 01 = ADCPPB4PSUM is used for compare logic 10 = ADCPPB4SUM is used for compare logic 11 = Reserved Note: when ADCPPB4PSUM is selected as the compare source and when a LIMIT match occurs (ADCPPB4LIMIT equals ADCPPB4COUNT) the ADCPPB4PSUM register will be cleared and the final sum will be loaded into ADCPPB4SUM. For this sample, the final sum, ADCPPB4SUM will be used for the compariosn instead of ADCPPB4PSUM. Reset type: SYSRSn
13	RESERVED	R	0h	Reserved
12	OSINTSEL	R/W	0h	Post Processing Block 4 Interrupt Source Select. OSINT4 can be used to trigger an ADC interrupt (ADCINT1 through ADCINT4) via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT4 in addition to a PCOUNT = LIMIT event. 0 = OSINT4 will be generated from PCOUNT = LIMIT only 1 = OSTIN4 will be generated form PCOUNT = LIMIT or a sync. event. Note: If a SYNC event would cause an OSINT one cycle after OSINT would have been cause by PCOUNT = LIMIT match, then the second OSINT is ignored. Reset type: SYSRSn
11	SWSYNC	R-0/W1S	0h	PPB 4 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur. Reset type: SYSRSn
10	RESERVED	R	0h	Reserved
9-4	SYNCINSEL	R/W	0h	PPB 4 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details Reset type: SYSRSn
3-0	SHIFT	R/W	0h	Post Processing Block 4 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM >> 1 2 : SUM = PSUM >> 2 ... 10 : SUM = PSUM >> 10 11 - 15 : Reserved Reset type: SYSRSn

14.14.3.120 ADCPPB4PSUM Register (Offset = 13Eh) [Reset = 00000000h]

ADCPPB4PSUM is shown in Figure 14-198 and described in Table 14-181.

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ADC PPB4 Partial Sum Register

Figure 14-198 ADCPPB4PSUM Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN								PSUM
R-0h								R-0h

Table 14-181 ADCPPB4PSUM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 23. Reset type: SYSRSn
23-0	PSUM	R	0h	Post Processing Block 4 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result is subsequently accumulated into this register. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 SYSCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 SYSCLK cycles (refer to the TRM for detailed timing information). Reset type: SYSRSn

14.14.3.121 ADCPPB4PMAX Register (Offset = 140h) [Reset = 00000000h]

ADCPPB4PMAX is shown in Figure 14-199 and described in Table 14-182.

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ADC PPB4 Partial Max Register

Figure 14-199 ADCPPB4PMAX Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN															PMAX
R-0h															R-0h

Table 14-182 ADCPPB4PMAX Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn
16-0	PMAX	R	0h	Post Processing Block 4 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is larger. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information). Reset type: SYSRSn

14.14.3.122 ADCPPB4PMAXI Register (Offset = 142h) [Reset = 0000h]

ADCPPB4PMAXI is shown in Figure 14-200 and described in Table 14-183.

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ADC PPB4 Partial Max Index Register

Figure 14-200 ADCPPB4PMAXI Register

15	14	13	12	11	10	9	8
RESERVED						PMAXI
R-0h						R-0h

7	6	5	4	3	2	1	0
PMAXI
R-0h

Table 14-183 ADCPPB4PMAXI Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	PMAXI	R	0h	Post Processing Block 4 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information). Reset type: SYSRSn

14.14.3.123 ADCPPB4PMIN Register (Offset = 144h) [Reset = 00000000h]

ADCPPB4PMIN is shown in Figure 14-201 and described in Table 14-184.

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ADC PPB4 Partial MIN Register

Figure 14-201 ADCPPB4PMIN Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGN															PMIN
R-0h															R-0h

Table 14-184 ADCPPB4PMIN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn
16-0	PMIN	R	0h	Post Processing Block 4 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is smaller. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information). Reset type: SYSRSn

14.14.3.124 ADCPPB4PMINI Register (Offset = 146h) [Reset = 0000h]

ADCPPB4PMINI is shown in Figure 14-202 and described in Table 14-185.

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ADC PPB4 Partial Min Index Register

Figure 14-202 ADCPPB4PMINI Register

15	14	13	12	11	10	9	8
RESERVED						PMINI
R-0h						R-0h

7	6	5	4	3	2	1	0
PMINI
R-0h

Table 14-185 ADCPPB4PMINI Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	PMINI	R	0h	Post Processing Block 4 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information). Reset type: SYSRSn

14.14.3.125 ADCPPB4TRIPLO2 Register (Offset = 148h) [Reset = 00000000h]

ADCPPB4TRIPLO2 is shown in Figure 14-203 and described in Table 14-186.

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ADC PPB4 Extended Trip Low Register

Figure 14-203 ADCPPB4TRIPLO2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								LIMITLO
R-0h								R/W-0h

Table 14-186 ADCPPB4TRIPLO2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	LIMITLO	R/W	0h	ADC Post Processing Block 4 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB4TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPLO2[23:17] will be ignored in 16 bit mode - TRIPLO2[23:13] will be ignored in 12 bit mode Reset type: SYSRSn