SPRUJ53 April 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Table 3-226 lists the memory-mapped registers for the PERIPH_AC_REGS registers. All register offset addresses not listed in Table 3-226 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | ADCA_AC | ADCA Controller Access Control Register | EALLOW | Go |
2h | ADCB_AC | ADCB Controller Access Control Register | EALLOW | Go |
4h | ADCC_AC | ADCC Controller Access Control Register | EALLOW | Go |
6h | ADCD_AC | ADCD Controller Access Control Register | EALLOW | Go |
8h | ADCE_AC | ADCE Controller Access Control Register | EALLOW | Go |
10h | CMPSS1_AC | CMPSS1 Controller Access Control Register | EALLOW | Go |
12h | CMPSS2_AC | CMPSS2 Controller Access Control Register | EALLOW | Go |
14h | CMPSS3_AC | CMPSS3 Controller Access Control Register | EALLOW | Go |
16h | CMPSS4_AC | CMPSS4 Controller Access Control Register | EALLOW | Go |
28h | DACA_AC | DACA Controller Access Control Register | EALLOW | Go |
38h | PGA1_AC | PGAA Controller Access Control Register | EALLOW | Go |
3Ah | PGA2_AC | PGAB Controller Access Control Register | EALLOW | Go |
3Ch | PGA3_AC | PGAC Controller Access Control Register | EALLOW | Go |
48h | EPWM1_AC | EPWM1 Controller Access Control Register | EALLOW | Go |
4Ah | EPWM2_AC | EPWM2 Controller Access Control Register | EALLOW | Go |
4Ch | EPWM3_AC | EPWM3 Controller Access Control Register | EALLOW | Go |
4Eh | EPWM4_AC | EPWM4 Controller Access Control Register | EALLOW | Go |
50h | EPWM5_AC | EPWM5 Controller Access Control Register | EALLOW | Go |
52h | EPWM6_AC | EPWM6 Controller Access Control Register | EALLOW | Go |
54h | EPWM7_AC | EPWM7 Controller Access Control Register | EALLOW | Go |
56h | EPWM8_AC | EPWM8 Controller Access Control Register | EALLOW | Go |
58h | EPWM9_AC | EPWM9 Controller Access Control Register | EALLOW | Go |
5Ah | EPWM10_AC | EPWM10 Controller Access Control Register | EALLOW | Go |
5Ch | EPWM11_AC | EPWM11 Controller Access Control Register | EALLOW | Go |
5Eh | EPWM12_AC | EPWM12 Controller Access Control Register | EALLOW | Go |
70h | EQEP1_AC | EQEP1 Controller Access Control Register | EALLOW | Go |
72h | EQEP2_AC | EQEP2 Controller Access Control Register | EALLOW | Go |
74h | EQEP3_AC | EQEP3 Controller Access Control Register | EALLOW | Go |
80h | ECAP1_AC | ECAP1 Controller Access Control Register | EALLOW | Go |
82h | ECAP2_AC | ECAP2 Controller Access Control Register | EALLOW | Go |
B0h | CLB1_AC | CLB1 Controller Access Control Register | EALLOW | Go |
B2h | CLB2_AC | CLB2 Controller Access Control Register | EALLOW | Go |
100h | SCIA_AC | SCIA Controller Access Control Register | EALLOW | Go |
102h | SCIB_AC | SCIB Controller Access Control Register | EALLOW | Go |
104h | SCIC_AC | SCIC Controller Access Control Register | EALLOW | Go |
110h | SPIA_AC | SPIA Controller Access Control Register | EALLOW | Go |
112h | SPIB_AC | SPIB Controller Access Control Register | EALLOW | Go |
120h | I2CA_AC | I2CA Controller Access Control Register | EALLOW | Go |
122h | I2CB_AC | I2CB Controller Access Control Register | EALLOW | Go |
130h | PMBUS_A_AC | PMBUSA Controller Access Control Register | EALLOW | Go |
138h | LIN_A_AC | LINA Controller Access Control Register | EALLOW | Go |
148h | MCANA_AC | MCANA Controller Access Control Register | EALLOW | Go |
14Ah | MCANB_AC | MCANB Controller Access Control Register | EALLOW | Go |
158h | FSIATX_AC | FSIA Controller Access Control Register | EALLOW | Go |
15Ah | FSIARX_AC | FSIB Controller Access Control Register | EALLOW | Go |
182h | USBA_AC | USBA Controller Access Control Register | EALLOW | Go |
1AAh | HRPWM_A_AC | HRPWM Controller Access Control Register | EALLOW | Go |
1AEh | AESA_AC | AES Controller Access Control Register | EALLOW | Go |
1FEh | PERIPH_AC_LOCK | Lock Register to stop Write access to peripheral Access register. | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-227 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
ADCA_AC is shown in Figure 3-199 and described in Table 3-228.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ADCB_AC is shown in Figure 3-200 and described in Table 3-229.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ADCC_AC is shown in Figure 3-201 and described in Table 3-230.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ADCD_AC is shown in Figure 3-202 and described in Table 3-231.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ADCE_AC is shown in Figure 3-203 and described in Table 3-232.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CMPSS1_AC is shown in Figure 3-204 and described in Table 3-233.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CMPSS2_AC is shown in Figure 3-205 and described in Table 3-234.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CMPSS3_AC is shown in Figure 3-206 and described in Table 3-235.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CMPSS4_AC is shown in Figure 3-207 and described in Table 3-236.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
DACA_AC is shown in Figure 3-208 and described in Table 3-237.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
PGA1_AC is shown in Figure 3-209 and described in Table 3-238.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
PGA2_AC is shown in Figure 3-210 and described in Table 3-239.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
PGA3_AC is shown in Figure 3-211 and described in Table 3-240.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM1_AC is shown in Figure 3-212 and described in Table 3-241.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM2_AC is shown in Figure 3-213 and described in Table 3-242.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM3_AC is shown in Figure 3-214 and described in Table 3-243.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM4_AC is shown in Figure 3-215 and described in Table 3-244.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM5_AC is shown in Figure 3-216 and described in Table 3-245.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM6_AC is shown in Figure 3-217 and described in Table 3-246.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM7_AC is shown in Figure 3-218 and described in Table 3-247.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM8_AC is shown in Figure 3-219 and described in Table 3-248.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM9_AC is shown in Figure 3-220 and described in Table 3-249.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM10_AC is shown in Figure 3-221 and described in Table 3-250.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM11_AC is shown in Figure 3-222 and described in Table 3-251.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM12_AC is shown in Figure 3-223 and described in Table 3-252.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EQEP1_AC is shown in Figure 3-224 and described in Table 3-253.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EQEP2_AC is shown in Figure 3-225 and described in Table 3-254.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EQEP3_AC is shown in Figure 3-226 and described in Table 3-255.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ECAP1_AC is shown in Figure 3-227 and described in Table 3-256.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ECAP2_AC is shown in Figure 3-228 and described in Table 3-257.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CLB1_AC is shown in Figure 3-229 and described in Table 3-258.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CLB2_AC is shown in Figure 3-230 and described in Table 3-259.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
SCIA_AC is shown in Figure 3-231 and described in Table 3-260.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R-0-0h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R-0 | 0h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
SCIB_AC is shown in Figure 3-232 and described in Table 3-261.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R-0-0h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R-0 | 0h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
SCIC_AC is shown in Figure 3-233 and described in Table 3-262.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R-0-0h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R-0 | 0h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
SPIA_AC is shown in Figure 3-234 and described in Table 3-263.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
SPIB_AC is shown in Figure 3-235 and described in Table 3-264.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
I2CA_AC is shown in Figure 3-236 and described in Table 3-265.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R-0-0h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R-0 | 0h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
I2CB_AC is shown in Figure 3-237 and described in Table 3-266.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R-0-0h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R-0 | 0h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
PMBUS_A_AC is shown in Figure 3-238 and described in Table 3-267.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
LIN_A_AC is shown in Figure 3-239 and described in Table 3-268.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
MCANA_AC is shown in Figure 3-240 and described in Table 3-269.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
MCANB_AC is shown in Figure 3-241 and described in Table 3-270.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
FSIATX_AC is shown in Figure 3-242 and described in Table 3-271.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
FSIARX_AC is shown in Figure 3-243 and described in Table 3-272.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
USBA_AC is shown in Figure 3-244 and described in Table 3-273.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
HRPWM_A_AC is shown in Figure 3-245 and described in Table 3-274.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
AESA_AC is shown in Figure 3-246 and described in Table 3-275.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected Controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
PERIPH_AC_LOCK is shown in Figure 3-247 and described in Table 3-276.
Return to the Summary Table.
Based on status bit control the Access registers are either RD/WR or RD only.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_AC_WR | ||||||
R-0-0h | R/WSonce-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R-0 | 0h | Reserved |
0 | LOCK_AC_WR | R/WSonce | 0h | Defines Access control definition for the CPU1 as: 1: Access Control registers are Read Only 0: Read/Write Access allowed to Access Control registers. Writing '1' sets the bit, writing '0' has no effect. Reset type: SYSRSn |