SWCU185F january 2018 – march 2023 CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1
The GPTM is placed into concatenated mode by writing a 0x0 or a 0x1 to the GPTM Configuration register (GPT:CFG) GPTMCFG bit field. In both configurations, certain 16- and 32-bit GPTM registers are concatenated to form pseudo 32-bit registers. These registers include the following:
In the 32-bit modes, the GPTM translates a 32-bit write access to the GPT:TAILR register into a write access to both the GPT:TAILR and the GPT:TBILR registers. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0]. Likewise, a 32-bit read access to GPT:TAR register returns the value: GPTMTBR[15:0]:GPTMTAR[15:0]. A 32-bit read access to GPT:TAV returns the value: GPTMTBV[15:0]:GPTMTAV[15:0].