SWCU185F january   2018  – march 2023 CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5. 1.1 Trademarks
  2. 2 Architectural Overview
    1. 2.1 Target Applications
    2. 2.2 Overview
    3. 2.3 Functional Overview
      1. 2.3.1  Arm® Cortex®-M4F
        1. 2.3.1.1 Processor Core
        2. 2.3.1.2 System Timer (SysTick)
        3. 2.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 2.3.1.4 System Control Block
      2. 2.3.2  On-Chip Memory
        1. 2.3.2.1 SRAM
        2. 2.3.2.2 Flash Memory
        3. 2.3.2.3 ROM
      3. 2.3.3  Radio
      4. 2.3.4  Security Core
      5. 2.3.5  General-Purpose Timers
        1. 2.3.5.1 Watchdog Timer
        2. 2.3.5.2 Always-On Domain
      6. 2.3.6  Direct Memory Access
      7. 2.3.7  System Control and Clock
      8. 2.3.8  Serial Communication Peripherals
        1. 2.3.8.1 UART
        2. 2.3.8.2 I2C
        3. 2.3.8.3 I2S
        4. 2.3.8.4 SSI
      9. 2.3.9  Programmable I/Os
      10. 2.3.10 Sensor Controller
      11. 2.3.11 Random Number Generator
      12. 2.3.12 cJTAG and JTAG
      13. 2.3.13 Power Supply System
        1. 2.3.13.1 Supply System
          1. 2.3.13.1.1 VDDS
          2. 2.3.13.1.2 VDDR
          3. 2.3.13.1.3 Digital Core Supply
          4. 2.3.13.1.4 Other Internal Supplies
        2. 2.3.13.2 DC/DC Converter
  3. 3 Arm® Cortex®-M4F Processor
    1. 3.1 Arm® Cortex®-M4F Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 Overview
      1. 3.3.1 System-Level Interface
      2. 3.3.2 Integrated Configurable Debug
      3. 3.3.3 Trace Port Interface Unit
      4. 3.3.4 Floating Point Unit (FPU)
      5. 3.3.5 Memory Protection Unit (MPU)
      6. 3.3.6 Arm® Cortex®-M4F System Component Details
    4. 3.4 Programming Model
      1. 3.4.1 Processor Mode and Privilege Levels for Software Execution
      2. 3.4.2 Stacks
      3. 3.4.3 Exceptions and Interrupts
      4. 3.4.4 Data Types
    5. 3.5 Arm® Cortex®-M4F Core Registers
      1. 3.5.1 Core Register Map
      2. 3.5.2 Core Register Descriptions
        1. 3.5.2.1  Cortex®General-Purpose Register 0 (R0)
        2. 3.5.2.2  Cortex® General-Purpose Register 1 (R1)
        3. 3.5.2.3  Cortex® General-Purpose Register 2 (R2)
        4. 3.5.2.4  Cortex® General-Purpose Register 3 (R3)
        5. 3.5.2.5  Cortex® General-Purpose Register 4 (R4)
        6. 3.5.2.6  Cortex® General-Purpose Register 5 (R5)
        7. 3.5.2.7  Cortex® General-Purpose Register 6 (R6)
        8. 3.5.2.8  Cortex® General-Purpose Register 7 (R7)
        9. 3.5.2.9  Cortex® General-Purpose Register 8 (R8)
        10. 3.5.2.10 Cortex® General-Purpose Register 9 (R9)
        11. 3.5.2.11 Cortex® General-Purpose Register 10 (R10)
        12. 3.5.2.12 Cortex® General-Purpose Register 11 (R11)
        13. 3.5.2.13 Cortex® General-Purpose Register 12 (R12)
        14. 3.5.2.14 Stack Pointer (SP)
        15. 3.5.2.15 Link Register (LR)
        16. 3.5.2.16 Program Counter (PC)
        17. 3.5.2.17 Program Status Register (PSR)
        18. 3.5.2.18 Priority Mask Register (PRIMASK)
        19. 3.5.2.19 Fault Mask Register (FAULTMASK)
        20. 3.5.2.20 Base Priority Mask Register (BASEPRI)
        21. 3.5.2.21 Control Register (CONTROL)
    6. 3.6 Instruction Set Summary
      1. 3.6.1 Arm® Cortex®-M4F Instructions
      2. 3.6.2 Load and Store Timings
      3. 3.6.3 Binary Compatibility With Other Cortex® Processors
    7. 3.7 Floating Point Unit (FPU)
      1. 3.7.1 About the FPU
      2. 3.7.2 FPU Functional Description
        1. 3.7.2.1 FPU Views of the Register Bank
        2. 3.7.2.2 Modes of Operation
          1. 3.7.2.2.1 Full-Compliance Mode
          2. 3.7.2.2.2 Flush-to-Zero Mode
          3. 3.7.2.2.3 Default NaN Mode
        3. 3.7.2.3 FPU Instruction Set
        4. 3.7.2.4 Compliance With the IEEE 754 Standard
        5. 3.7.2.5 Complete Implementation of the IEEE 754 Standard
        6. 3.7.2.6 IEEE 754 Standard Implementation Choices
          1. 3.7.2.6.1 NaN Handling
          2. 3.7.2.6.2 Comparisons
          3. 3.7.2.6.3 Underflow
        7. 3.7.2.7 Exceptions
      3. 3.7.3 FPU Programmers Model
        1. 3.7.3.1 Enabling the FPU
          1. 3.7.3.1.1 Enabling the FPU
    8. 3.8 Memory Protection Unit (MPU)
      1. 3.8.1 About the MPU
      2. 3.8.2 MPU Functional Description
      3. 3.8.3 MPU Programmers Model
    9. 3.9 Arm® Cortex®-M4F Processor Registers
      1. 3.9.1 CPU_DWT Registers
      2. 3.9.2 CPU_FPB Registers
      3. 3.9.3 CPU_ITM Registers
      4. 3.9.4 CPU_SCS Registers
      5. 3.9.5 CPU_TPIU Registers
  4. 4 Memory Map
    1. 4.1 Memory Map
  5. 5 Arm® Cortex®-M4F Peripherals
    1. 5.1 Arm® Cortex®-M4F Peripherals Introduction
    2. 5.2 Functional Description
      1. 5.2.1 SysTick
      2. 5.2.2 NVIC
        1. 5.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 5.2.2.2 Hardware and Software Control of Interrupts
      3. 5.2.3 SCB
      4. 5.2.4 ITM
      5. 5.2.5 FPB
      6. 5.2.6 TPIU
      7. 5.2.7 DWT
  6. 6 Interrupts and Events
    1. 6.1 Exception Model
      1. 6.1.1 Exception States
      2. 6.1.2 Exception Types
      3. 6.1.3 Exception Handlers
      4. 6.1.4 Vector Table
      5. 6.1.5 Exception Priorities
      6. 6.1.6 Interrupt Priority Grouping
      7. 6.1.7 Exception Entry and Return
        1. 6.1.7.1 Exception Entry
        2. 6.1.7.2 Exception Return
    2. 6.2 Fault Handling
      1. 6.2.1 Fault Types
      2. 6.2.2 Fault Escalation and Hard Faults
      3. 6.2.3 Fault Status Registers and Fault Address Registers
      4. 6.2.4 Lockup
    3. 6.3 Event Fabric
      1. 6.3.1 Introduction
      2. 6.3.2 Event Fabric Overview
        1. 6.3.2.1 Registers
    4. 6.4 AON Event Fabric
      1. 6.4.1 Common Input Event List
      2. 6.4.2 Event Subscribers
        1. 6.4.2.1 Wake-Up Controller (WUC)
        2. 6.4.2.2 Real-Time Clock
        3. 6.4.2.3 MCU Event Fabric
    5. 6.5 MCU Event Fabric
      1. 6.5.1 Common Input Event List
      2. 6.5.2 Event Subscribers
        1. 6.5.2.1 System CPU
        2. 6.5.2.2 NMI
        3. 6.5.2.3 Freeze
    6. 6.6 AON Events
    7. 6.7 Interrupts and Events Registers
      1. 6.7.1 AON_EVENT Registers
      2. 6.7.2 EVENT Registers
  7. 7 JTAG Interface
    1. 7.1  Top-Level Debug System
    2. 7.2  cJTAG
      1. 7.2.1 cJTAG Commands
        1. 7.2.1.1 Mandatory Commands
      2. 7.2.2 Programming Sequences
        1. 7.2.2.1 Opening Command Window
        2. 7.2.2.2 Changing to 4-Pin Mode
        3. 7.2.2.3 Close Command Window
    3. 7.3  ICEPick
      1. 7.3.1 Secondary TAPs
        1. 7.3.1.1 Slave DAP (CPU DAP)
        2. 7.3.1.2 Ordering Slave TAPs and DAPs
      2. 7.3.2 ICEPick Registers
        1. 7.3.2.1 IR Instructions
        2. 7.3.2.2 Data Shift Register
        3. 7.3.2.3 Instruction Register
        4. 7.3.2.4 Bypass Register
        5. 7.3.2.5 Device Identification Register
        6. 7.3.2.6 User Code Register
        7. 7.3.2.7 ICEPick Identification Register
        8. 7.3.2.8 Connect Register
      3. 7.3.3 Router Scan Chain
      4. 7.3.4 TAP Routing Registers
        1. 7.3.4.1 ICEPick Control Block
          1. 7.3.4.1.1 All0s Register
          2. 7.3.4.1.2 ICEPick Control Register
          3. 7.3.4.1.3 Linking Mode Register
        2. 7.3.4.2 Test TAP Linking Block
          1. 7.3.4.2.1 Secondary Test TAP Register
        3. 7.3.4.3 Debug TAP Linking Block
          1. 7.3.4.3.1 Secondary Debug TAP Register
    4. 7.4  ICEMelter
    5. 7.5  Serial Wire Viewer (SWV)
    6. 7.6  Halt In Boot (HIB)
    7. 7.7  Debug and Shutdown
    8. 7.8  Debug Features Supported Through WUC TAP
    9. 7.9  Profiler Register
    10. 7.10 Boundary Scan
  8. 8 Power, Reset, and Clock Management (PRCM)
    1. 8.1 Introduction
    2. 8.2 System CPU Mode
    3. 8.3 Supply System
      1. 8.3.1 Internal DC/DC Converter and Global LDO
    4. 8.4 Digital Power Partitioning
      1. 8.4.1 MCU_VD
        1. 8.4.1.1 MCU_VD Power Domains
      2. 8.4.2 AON_VD
        1. 8.4.2.1 AON_VD Power Domains
    5. 8.5 Clock Management
      1. 8.5.1 System Clocks
        1. 8.5.1.1 Controlling the Oscillators
      2. 8.5.2 Clocks in MCU_VD
        1. 8.5.2.1 Clock Gating
        2. 8.5.2.2 Scaler to GPTs
        3. 8.5.2.3 Scaler to WDT
      3. 8.5.3 Clocks in AON_VD
    6. 8.6 Power Modes
      1. 8.6.1 Start-Up State
      2. 8.6.2 Active Mode
      3. 8.6.3 Idle Mode
      4. 8.6.4 Standby Mode
      5. 8.6.5 Shutdown Mode
    7. 8.7 Reset
      1. 8.7.1 System Resets
        1. 8.7.1.1 Clock Loss Detection
        2. 8.7.1.2 Software-Initiated System Reset
        3. 8.7.1.3 Warm Reset Converted to System Reset
      2. 8.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 8.7.3 Reset of AON_VD
    8. 8.8 PRCM Registers
      1. 8.8.1 DDI_0_OSC Registers
      2. 8.8.2 PRCM Registers
      3. 8.8.3 AON_PMCTL Registers
  9. 9 Versatile Instruction Memory System (VIMS)
    1. 9.1 Introduction
    2. 9.2 VIMS Configurations
      1. 9.2.1 VIMS Modes
        1. 9.2.1.1 GPRAM Mode
        2. 9.2.1.2 Off Mode
        3. 9.2.1.3 Cache Mode
      2. 9.2.2 VIMS FLASH Line Buffers
      3. 9.2.3 VIMS Arbitration
      4. 9.2.4 VIMS Cache TAG Prefetch
    3. 9.3 VIMS Software Remarks
      1. 9.3.1 FLASH Program or Update
      2. 9.3.2 VIMS Retention
        1. 9.3.2.1 Mode 1
        2. 9.3.2.2 Mode 2
        3. 9.3.2.3 Mode 3
    4. 9.4 ROM
    5. 9.5 FLASH
      1. 9.5.1 FLASH Memory Protection
      2. 9.5.2 Memory Programming
      3. 9.5.3 FLASH Memory Programming
      4. 9.5.4 Power Management Requirements
    6. 9.6 ROM Functions
    7. 9.7 VIMS Registers
      1. 9.7.1 FLASH Registers
      2. 9.7.2 VIMS Registers
  10. 10SRAM
    1. 10.1 Introduction
    2. 10.2 Main Features
    3. 10.3 Data Retention
    4. 10.4 Parity and SRAM Error Support
    5. 10.5 SRAM Auto-Initialization
    6. 10.6 Parity Debug Behavior
    7. 10.7 SRAM Registers
      1. 10.7.1 SRAM_MMR Registers
      2. 10.7.2 SRAM Registers
  11. 11Bootloader
    1. 11.1 Bootloader Functionality
      1. 11.1.1 Bootloader Disabling
      2. 11.1.2 Bootloader Backdoor
    2. 11.2 Bootloader Interfaces
      1. 11.2.1 Packet Handling
        1. 11.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 11.2.2 Transport Layer
        1. 11.2.2.1 UART Transport
          1. 11.2.2.1.1 UART Baud Rate Automatic Detection
        2. 11.2.2.2 SSI Transport
      3. 11.2.3 Serial Bus Commands
        1. 11.2.3.1  COMMAND_PING
        2. 11.2.3.2  COMMAND_DOWNLOAD
        3. 11.2.3.3  COMMAND_SEND_DATA
        4. 11.2.3.4  COMMAND_SECTOR_ERASE
        5. 11.2.3.5  COMMAND_GET_STATUS
        6. 11.2.3.6  COMMAND_RESET
        7. 11.2.3.7  COMMAND_GET_CHIP_ID
        8. 11.2.3.8  COMMAND_CRC32
        9. 11.2.3.9  COMMAND_BANK_ERASE
        10. 11.2.3.10 COMMAND_MEMORY_READ
        11. 11.2.3.11 COMMAND_MEMORY_WRITE
        12. 11.2.3.12 COMMAND_SET_CCFG
        13. 11.2.3.13 COMMAND_DOWNLOAD_CRC
  12. 12Device Configuration
    1. 12.1 Customer Configuration (CCFG)
    2. 12.2 CCFG Registers
      1. 12.2.1 CCFG Registers
    3. 12.3 Factory Configuration (FCFG)
    4. 12.4 FCFG Registers
      1. 12.4.1 FCFG1 Registers
  13. 13Cryptography
    1. 13.1 AES and Hash Cryptoprocessor Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Debug Capabilities
      2. 13.2.2 Exception Handling
    3. 13.3 Power Management and Sleep Modes
    4. 13.4 Hardware Description
      1. 13.4.1 AHB Slave Bus
      2. 13.4.2 AHB Master Bus
      3. 13.4.3 Interrupts
    5. 13.5 Module Description
      1. 13.5.1 Introduction
      2. 13.5.2 Module Memory Map
      3. 13.5.3 DMA Controller
        1. 13.5.3.1 Internal Operation
        2. 13.5.3.2 Supported DMA Operations
      4. 13.5.4 Master Control and Select Module
        1. 13.5.4.1 Algorithm Select Register
          1. 13.5.4.1.1 Algorithm Select
        2. 13.5.4.2 Master PROT Enable
          1. 13.5.4.2.1 Master PROT-Privileged Access-Enable
        3. 13.5.4.3 Software Reset
      5. 13.5.5 AES Engine
        1. 13.5.5.1 Second Key Registers (Internal, But Clearable)
        2. 13.5.5.2 AES Initialization Vector (IV) Registers
        3. 13.5.5.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 13.5.5.4 Data Input and Output Registers
        5. 13.5.5.5 TAG Registers
      6. 13.5.6 Key Area Registers
        1. 13.5.6.1 Key Write Area Register
        2. 13.5.6.2 Key Written Area Register
        3. 13.5.6.3 Key Size Register
        4. 13.5.6.4 Key Store Read Area Register
        5. 13.5.6.5 Hash Engine
    6. 13.6 AES Module Performance
      1. 13.6.1 Introduction
      2. 13.6.2 Performance for DMA-Based Operations
    7. 13.7 Programming Guidelines
      1. 13.7.1 One-Time Initialization After a Reset
      2. 13.7.2 DMAC and Master Control
        1. 13.7.2.1 Regular Use
        2. 13.7.2.2 Interrupting DMA Transfers
        3. 13.7.2.3 Interrupts, Hardware, and Software Synchronization
      3. 13.7.3 Hashing
        1. 13.7.3.1 Data Format and Byte Order
        2. 13.7.3.2 Basic Hash With Data From DMA
          1. 13.7.3.2.1 New Hash Session With Digest Read Through Slave
          2. 13.7.3.2.2 New Hash Session With Digest to External Memory
          3. 13.7.3.2.3 Resumed Hash Session
        3. 13.7.3.3 HMAC
          1. 13.7.3.3.1 Secure HMAC
        4. 13.7.3.4 Alternative Basic Hash Where Data Originates From Slave Interface
          1. 13.7.3.4.1 New Hash Session
          2. 13.7.3.4.2 Resumed Hash Session
      4. 13.7.4 Encryption and Decryption
        1. 13.7.4.1 Data Format and Byte Order
        2. 13.7.4.2 Key Store
          1. 13.7.4.2.1 Load Keys From External Memory
        3. 13.7.4.3 Basic AES Modes
          1. 13.7.4.3.1 AES-ECB
          2. 13.7.4.3.2 AES-CBC
          3. 13.7.4.3.3 AES-CTR
          4. 13.7.4.3.4 Programming Sequence With DMA Data
        4. 13.7.4.4 CBC-MAC
          1. 13.7.4.4.1 Programming Sequence for CBC-MAC
        5. 13.7.4.5 AES-CCM
          1. 13.7.4.5.1 Programming Sequence for AES-CCM
        6. 13.7.4.6 AES-GCM
          1. 13.7.4.6.1 Programming Sequence for AES-GCM
      5. 13.7.5 Exceptions Handling
        1. 13.7.5.1 Soft Reset
        2. 13.7.5.2 External Port Errors
        3. 13.7.5.3 Key Store Errors
          1. 13.7.5.3.1 PKA Engine
          2. 13.7.5.3.2 Functional Description
            1. 13.7.5.3.2.1 Module Architecture
          3. 13.7.5.3.3 PKA RAM
            1. 13.7.5.3.3.1 PKCP Operations
            2. 13.7.5.3.3.2 Sequencer Operations
              1. 13.7.5.3.3.2.1 Modular Exponentiation Operations
              2. 13.7.5.3.3.2.2 Modular Inversion Operation
              3. 13.7.5.3.3.2.3 Performance
              4. 13.7.5.3.3.2.4 ECC Operations
              5. 13.7.5.3.3.2.5 Performance
              6. 13.7.5.3.3.2.6 ExpMod Performance
              7. 13.7.5.3.3.2.7 Modular Inversion Performance
              8. 13.7.5.3.3.2.8 ECC Operation Performance
            3. 13.7.5.3.3.3 Sequencer ROM Behavior and Interfaces
            4. 13.7.5.3.3.4 Register Configurations
            5. 13.7.5.3.3.5 Operation Sequence
    8. 13.8 Conventions and Compliances
      1. 13.8.1 Conventions Used in This Manual
        1. 13.8.1.1 Terminology
        2. 13.8.1.2 Formulas and Nomenclature
      2. 13.8.2 Compliance
    9. 13.9 Cryptography Registers
      1. 13.9.1 CRYPTO Registers
  14. 14I/O Controller (IOC)
    1. 14.1  Introduction
    2. 14.2  IOC Overview
    3. 14.3  I/O Mapping and Configuration
      1. 14.3.1 Basic I/O Mapping
      2. 14.3.2 Mapping AUXIOs to DIO Pins
      3. 14.3.3 Control External LNA/PA (Range Extender) With I/Os
      4. 14.3.4 Map the 32 kHz System Clock (LF Clock) to DIO
    4. 14.4  Edge Detection on DIO Pins
      1. 14.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT
    5. 14.5  Unused I/O Pins
    6. 14.6  GPIO
    7. 14.7  I/O Pin Capability
    8. 14.8  Peripheral PORTIDs
    9. 14.9  I/O Pins
      1. 14.9.1 Input/Output Modes
        1. 14.9.1.1 Physical Pin
        2. 14.9.1.2 Pin Configuration
    10. 14.10 IOC Registers
      1. 14.10.1 AON_IOC Registers
      2. 14.10.2 GPIO Registers
      3. 14.10.3 IOC Registers
  15. 15Micro Direct Memory Access (µDMA)
    1. 15.1 μDMA Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
    4. 15.4 Initialization and Configuration
      1. 15.4.1 Module Initialization
      2. 15.4.2 Configuring a Memory-to-Memory Transfer
        1. 15.4.2.1 Configure the Channel Attributes
        2. 15.4.2.2 Configure the Channel Control Structure
        3. 15.4.2.3 Start the Transfer
    5. 15.5 µDMA Registers
      1. 15.5.1 UDMA Registers
  16. 16Timers
    1. 16.1 General-Purpose Timers
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1 GPTM Reset Conditions
      2. 16.3.2 Timer Modes
        1. 16.3.2.1 One-Shot or Periodic Timer Mode
        2. 16.3.2.2 Input Edge-Count Mode
        3. 16.3.2.3 Input Edge-Time Mode
        4. 16.3.2.4 PWM Mode
        5. 16.3.2.5 Wait-for-Trigger Mode
      3. 16.3.3 Synchronizing GPT Blocks
      4. 16.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 16.4 Initialization and Configuration
      1. 16.4.1 One-Shot and Periodic Timer Modes
      2. 16.4.2 Input Edge-Count Mode
      3. 16.4.3 Input Edge-Timing Mode
      4. 16.4.4 PWM Mode
      5. 16.4.5 Producing DMA Trigger Events
    5. 16.5 GPTM Registers
      1. 16.5.1 GPT Registers
  17. 17Real-Time Clock (RTC)
    1. 17.1 Introduction
    2. 17.2 Functional Specifications
      1. 17.2.1 Functional Overview
      2. 17.2.2 Free-Running Counter
      3. 17.2.3 Channels
        1. 17.2.3.1 Capture and Compare
      4. 17.2.4 Events
    3. 17.3 RTC Register Information
      1. 17.3.1 Register Access
      2. 17.3.2 Entering Sleep and Wakeup From Sleep
      3. 17.3.3 AON_RTC:SYNC Register
    4. 17.4 RTC Registers
      1. 17.4.1 AON_RTC Registers
  18. 18Watchdog Timer (WDT)
    1. 18.1 Introduction
    2. 18.2 Functional Description
    3. 18.3 Initialization and Configuration
    4. 18.4 WDT Registers
      1. 18.4.1 WDT Registers
  19. 19True Random Number Generator (TRNG)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 TRNG Software Reset
    4. 19.4 Interrupt Requests
    5. 19.5 TRNG Operation Description
      1. 19.5.1 TRNG Shutdown
      2. 19.5.2 TRNG Alarms
      3. 19.5.3 TRNG Entropy
    6. 19.6 TRNG Low-Level Programing Guide
      1. 19.6.1 Initialization
        1. 19.6.1.1 Interfacing Modules
        2. 19.6.1.2 TRNG Main Sequence
        3. 19.6.1.3 TRNG Operating Modes
          1. 19.6.1.3.1 Polling Mode
          2. 19.6.1.3.2 Interrupt Mode
    7. 19.7 TRNG Registers
      1. 19.7.1 TRNG Registers
  20. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 AIODIO
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 SMPH
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPIM
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
              1. 20.4.7.2.5.1.1 Timer Period and Pulse Width Capture
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.2.1 Center-Aligned PWM Generation by Channel 0
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.3.1 Edge-Aligned PWM Generation by Channel 0
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 COMPA
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 COMPB
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference DAC
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 ISRC
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  21. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 BATMON Registers
      1. 21.3.1 AON_BATMON Registers
  22. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud-rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to DMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
      1. 22.7.1 UART Registers
  23. 23Synchronous Serial Interface (SSI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
        2. 23.4.2.2 Receive FIFO
      3. 23.4.3 Interrupts
      4. 23.4.4 Frame Formats
        1. 23.4.4.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.4.2 Motorola SPI Frame Format
          1. 23.4.4.2.1 SPO Clock Polarity Bit
          2. 23.4.4.2.2 SPH Phase-Control Bit
        3. 23.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
        4. 23.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
        5. 23.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
        6. 23.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
        7. 23.4.4.7 MICROWIRE Frame Format
    5. 23.5 DMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SSI Registers
      1. 23.7.1 SSI Registers
  24. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format With 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
      1. 24.5.1 I2C Registers
  25. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
      1. 25.9.1 I2S Registers
  26. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization With Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond With Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration (Depricated)
          19. 26.3.3.2.19 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          20. 26.3.3.2.20 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® low energy
      1. 26.6.1 Bluetooth® low energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® low energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® low energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Nonconnectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  27. 27Revision History

9.7.1 FLASH Registers

Table 9-3 lists the memory-mapped registers for the FLASH registers. All register offset addresses not listed in Table 9-3 should be considered as reserved locations and the register contents should not be modified.

Table 9-3 FLASH Registers
OffsetAcronymRegister NameSection
1ChSTATFMC and Efuse StatusSTAT Register (Offset = 1Ch) [Reset = 00000000h]
24hCFGInternalCFG Register (Offset = 24h) [Reset = 00000000h]
28hSYSCODE_STARTInternalSYSCODE_START Register (Offset = 28h) [Reset = 00000000h]
2ChFLASH_SIZEInternalFLASH_SIZE Register (Offset = 2Ch) [Reset = 00000000h]
3ChFWLOCKInternalFWLOCK Register (Offset = 3Ch) [Reset = 00000000h]
40hFWFLAGInternalFWFLAG Register (Offset = 40h) [Reset = 00000000h]
1000hEFUSEInternalEFUSE Register (Offset = 1000h) [Reset = 00000000h]
1004hEFUSEADDRInternalEFUSEADDR Register (Offset = 1004h) [Reset = 00000000h]
1008hDATAUPPERInternalDATAUPPER Register (Offset = 1008h) [Reset = 00000000h]
100ChDATALOWERInternalDATALOWER Register (Offset = 100Ch) [Reset = 00000000h]
1010hEFUSECFGInternalEFUSECFG Register (Offset = 1010h) [Reset = 00000001h]
1014hEFUSESTATInternalEFUSESTAT Register (Offset = 1014h) [Reset = 00000001h]
1018hACCInternalACC Register (Offset = 1018h) [Reset = 00000000h]
101ChBOUNDARYInternalBOUNDARY Register (Offset = 101Ch) [Reset = 00000000h]
1020hEFUSEFLAGInternalEFUSEFLAG Register (Offset = 1020h) [Reset = 00000000h]
1024hEFUSEKEYInternalEFUSEKEY Register (Offset = 1024h) [Reset = 00000000h]
1028hEFUSERELEASEInternalEFUSERELEASE Register (Offset = 1028h) [Reset = 00000000h]
102ChEFUSEPINSInternalEFUSEPINS Register (Offset = 102Ch) [Reset = 00000000h]
1030hEFUSECRAInternalEFUSECRA Register (Offset = 1030h) [Reset = 00000000h]
1034hEFUSEREADInternalEFUSEREAD Register (Offset = 1034h) [Reset = 00000000h]
1038hEFUSEPROGRAMInternalEFUSEPROGRAM Register (Offset = 1038h) [Reset = 00000000h]
103ChEFUSEERRORInternalEFUSEERROR Register (Offset = 103Ch) [Reset = 00000000h]
1040hSINGLEBITInternalSINGLEBIT Register (Offset = 1040h) [Reset = 00000000h]
1044hTWOBITInternalTWOBIT Register (Offset = 1044h) [Reset = 00000000h]
1048hSELFTESTCYCInternalSELFTESTCYC Register (Offset = 1048h) [Reset = 00000000h]
104ChSELFTESTSIGNInternalSELFTESTSIGN Register (Offset = 104Ch) [Reset = 00000000h]
2000hFRDCTLInternalFRDCTL Register (Offset = 2000h) [Reset = 00000200h]
2004hFSPRDInternalFSPRD Register (Offset = 2004h) [Reset = 00000000h]
2008hFEDACCTL1InternalFEDACCTL1 Register (Offset = 2008h) [Reset = 00000000h]
201ChFEDACSTATInternalFEDACSTAT Register (Offset = 201Ch) [Reset = 00000000h]
2030hFBPROTInternalFBPROT Register (Offset = 2030h) [Reset = 00000000h]
2034hFBSEInternalFBSE Register (Offset = 2034h) [Reset = 00000000h]
2038hFBBUSYInternalFBBUSY Register (Offset = 2038h) [Reset = 000000FEh]
203ChFBACInternalFBAC Register (Offset = 203Ch) [Reset = 0000000Fh]
2040hFBFALLBACKInternalFBFALLBACK Register (Offset = 2040h) [Reset = 0505FFFFh]
2044hFBPRDYInternalFBPRDY Register (Offset = 2044h) [Reset = 00FF00FEh]
2048hFPAC1InternalFPAC1 Register (Offset = 2048h) [Reset = 02082081h]
204ChFPAC2InternalFPAC2 Register (Offset = 204Ch) [Reset = 00000000h]
2050hFMACInternalFMAC Register (Offset = 2050h) [Reset = 00000000h]
2054hFMSTATInternalFMSTAT Register (Offset = 2054h) [Reset = 00000000h]
2064hFLOCKInternalFLOCK Register (Offset = 2064h) [Reset = 000055AAh]
2080hFVREADCTInternalFVREADCT Register (Offset = 2080h) [Reset = 00000008h]
2084hFVHVCT1InternalFVHVCT1 Register (Offset = 2084h) [Reset = 00840088h]
2088hFVHVCT2InternalFVHVCT2 Register (Offset = 2088h) [Reset = 00A20000h]
208ChFVHVCT3InternalFVHVCT3 Register (Offset = 208Ch) [Reset = 000F0000h]
2090hFVNVCTInternalFVNVCT Register (Offset = 2090h) [Reset = 00000800h]
2094hFVSLPInternalFVSLP Register (Offset = 2094h) [Reset = 00008000h]
2098hFVWLCTInternalFVWLCT Register (Offset = 2098h) [Reset = 00000008h]
209ChFEFUSECTLInternalFEFUSECTL Register (Offset = 209Ch) [Reset = 0701010Ah]
20A0hFEFUSESTATInternalFEFUSESTAT Register (Offset = 20A0h) [Reset = 00000000h]
20A4hFEFUSEDATAInternalFEFUSEDATA Register (Offset = 20A4h) [Reset = 00000000h]
20A8hFSEQPMPInternalFSEQPMP Register (Offset = 20A8h) [Reset = 85080000h]
2100hFBSTROBESInternalFBSTROBES Register (Offset = 2100h) [Reset = 00000104h]
2104hFPSTROBESInternalFPSTROBES Register (Offset = 2104h) [Reset = 00000103h]
2108hFBMODEInternalFBMODE Register (Offset = 2108h) [Reset = 00000000h]
210ChFTCRInternalFTCR Register (Offset = 210Ch) [Reset = 00000000h]
2110hFADDRInternalFADDR Register (Offset = 2110h) [Reset = 00000000h]
211ChFTCTLInternalFTCTL Register (Offset = 211Ch) [Reset = 00000000h]
2120hFWPWRITE0InternalFWPWRITE0 Register (Offset = 2120h) [Reset = FFFFFFFFh]
2124hFWPWRITE1InternalFWPWRITE1 Register (Offset = 2124h) [Reset = FFFFFFFFh]
2128hFWPWRITE2InternalFWPWRITE2 Register (Offset = 2128h) [Reset = FFFFFFFFh]
212ChFWPWRITE3InternalFWPWRITE3 Register (Offset = 212Ch) [Reset = FFFFFFFFh]
2130hFWPWRITE4InternalFWPWRITE4 Register (Offset = 2130h) [Reset = FFFFFFFFh]
2134hFWPWRITE5InternalFWPWRITE5 Register (Offset = 2134h) [Reset = FFFFFFFFh]
2138hFWPWRITE6InternalFWPWRITE6 Register (Offset = 2138h) [Reset = FFFFFFFFh]
213ChFWPWRITE7InternalFWPWRITE7 Register (Offset = 213Ch) [Reset = FFFFFFFFh]
2140hFWPWRITE_ECCInternalFWPWRITE_ECC Register (Offset = 2140h) [Reset = FFFFFFFFh]
2144hFSWSTATInternalFSWSTAT Register (Offset = 2144h) [Reset = 00000001h]
2200hFSM_GLBCTLInternalFSM_GLBCTL Register (Offset = 2200h) [Reset = 00000001h]
2204hFSM_STATEInternalFSM_STATE Register (Offset = 2204h) [Reset = 00000C00h]
2208hFSM_STATInternalFSM_STAT Register (Offset = 2208h) [Reset = 00000004h]
220ChFSM_CMDInternalFSM_CMD Register (Offset = 220Ch) [Reset = 00000000h]
2210hFSM_PE_OSUInternalFSM_PE_OSU Register (Offset = 2210h) [Reset = 00000000h]
2214hFSM_VSTATInternalFSM_VSTAT Register (Offset = 2214h) [Reset = 00003000h]
2218hFSM_PE_VSUInternalFSM_PE_VSU Register (Offset = 2218h) [Reset = 00000000h]
221ChFSM_CMP_VSUInternalFSM_CMP_VSU Register (Offset = 221Ch) [Reset = 00000000h]
2220hFSM_EX_VALInternalFSM_EX_VAL Register (Offset = 2220h) [Reset = 00000301h]
2224hFSM_RD_HInternalFSM_RD_H Register (Offset = 2224h) [Reset = 0000005Ah]
2228hFSM_P_OHInternalFSM_P_OH Register (Offset = 2228h) [Reset = 00000100h]
222ChFSM_ERA_OHInternalFSM_ERA_OH Register (Offset = 222Ch) [Reset = 00000001h]
2230hFSM_SAV_PPULInternalFSM_SAV_PPUL Register (Offset = 2230h) [Reset = 00000000h]
2234hFSM_PE_VHInternalFSM_PE_VH Register (Offset = 2234h) [Reset = 00000100h]
2240hFSM_PRG_PWInternalFSM_PRG_PW Register (Offset = 2240h) [Reset = 00000000h]
2244hFSM_ERA_PWInternalFSM_ERA_PW Register (Offset = 2244h) [Reset = 00000000h]
2254hFSM_SAV_ERA_PULInternalFSM_SAV_ERA_PUL Register (Offset = 2254h) [Reset = 00000000h]
2258hFSM_TIMERInternalFSM_TIMER Register (Offset = 2258h) [Reset = 00000000h]
225ChFSM_MODEInternalFSM_MODE Register (Offset = 225Ch) [Reset = 00000000h]
2260hFSM_PGMInternalFSM_PGM Register (Offset = 2260h) [Reset = 00000000h]
2264hFSM_ERAInternalFSM_ERA Register (Offset = 2264h) [Reset = 00000000h]
2268hFSM_PRG_PULInternalFSM_PRG_PUL Register (Offset = 2268h) [Reset = 00040032h]
226ChFSM_ERA_PULInternalFSM_ERA_PUL Register (Offset = 226Ch) [Reset = 00040BB8h]
2270hFSM_STEP_SIZEInternalFSM_STEP_SIZE Register (Offset = 2270h) [Reset = 00000000h]
2274hFSM_PUL_CNTRInternalFSM_PUL_CNTR Register (Offset = 2274h) [Reset = 00000000h]
2278hFSM_EC_STEP_HEIGHTInternalFSM_EC_STEP_HEIGHT Register (Offset = 2278h) [Reset = 00000000h]
227ChFSM_ST_MACHINEInternalFSM_ST_MACHINE Register (Offset = 227Ch) [Reset = 00800500h]
2280hFSM_FLESInternalFSM_FLES Register (Offset = 2280h) [Reset = 00000000h]
2288hFSM_WR_ENAInternalFSM_WR_ENA Register (Offset = 2288h) [Reset = 00000002h]
228ChFSM_ACC_PPInternalFSM_ACC_PP Register (Offset = 228Ch) [Reset = 00000000h]
2290hFSM_ACC_EPInternalFSM_ACC_EP Register (Offset = 2290h) [Reset = 00000000h]
22A0hFSM_ADDRInternalFSM_ADDR Register (Offset = 22A0h) [Reset = 00000000h]
22A4hFSM_SECTORInternalFSM_SECTOR Register (Offset = 22A4h) [Reset = FFFF0000h]
22A8hFMC_REV_IDInternalFMC_REV_ID Register (Offset = 22A8h) [Reset = 00000000h]
22AChFSM_ERR_ADDRInternalFSM_ERR_ADDR Register (Offset = 22ACh) [Reset = 00000000h]
22B0hFSM_PGM_MAXPULInternalFSM_PGM_MAXPUL Register (Offset = 22B0h) [Reset = 00000000h]
22B4hFSM_EXECUTEInternalFSM_EXECUTE Register (Offset = 22B4h) [Reset = 000A000Ah]
22C0hFSM_SECTOR1InternalFSM_SECTOR1 Register (Offset = 22C0h) [Reset = FFFFFFFFh]
22C4hFSM_SECTOR2InternalFSM_SECTOR2 Register (Offset = 22C4h) [Reset = 00000FFFh]
22E0hFSM_BSLE0InternalFSM_BSLE0 Register (Offset = 22E0h) [Reset = 00000000h]
22E4hFSM_BSLE1InternalFSM_BSLE1 Register (Offset = 22E4h) [Reset = 00000000h]
22F0hFSM_BSLP0InternalFSM_BSLP0 Register (Offset = 22F0h) [Reset = 00000000h]
22F4hFSM_BSLP1InternalFSM_BSLP1 Register (Offset = 22F4h) [Reset = 00000000h]
22F8hFSM_PGM128FMC FSM Enable 128-bit Wide ProgrammingFSM_PGM128 Register (Offset = 22F8h) [Reset = 00000000h]
2400hFCFG_BANKInternalFCFG_BANK Register (Offset = 2400h) [Reset = 00000801h]
2404hFCFG_WRAPPERInternalFCFG_WRAPPER Register (Offset = 2404h) [Reset = 50009007h]
2408hFCFG_BNK_TYPEInternalFCFG_BNK_TYPE Register (Offset = 2408h) [Reset = 00000004h]
2410hFCFG_B0_STARTInternalFCFG_B0_START Register (Offset = 2410h) [Reset = 02000000h]
2414hFCFG_B1_STARTInternalFCFG_B1_START Register (Offset = 2414h) [Reset = 00000000h]
2418hFCFG_B2_STARTInternalFCFG_B2_START Register (Offset = 2418h) [Reset = 00000000h]
241ChFCFG_B3_STARTInternalFCFG_B3_START Register (Offset = 241Ch) [Reset = 00000000h]
2420hFCFG_B4_STARTInternalFCFG_B4_START Register (Offset = 2420h) [Reset = 00000000h]
2424hFCFG_B5_STARTInternalFCFG_B5_START Register (Offset = 2424h) [Reset = 00000000h]
2428hFCFG_B6_STARTInternalFCFG_B6_START Register (Offset = 2428h) [Reset = 00000000h]
242ChFCFG_B7_STARTInternalFCFG_B7_START Register (Offset = 242Ch) [Reset = 00000000h]
2430hFCFG_B0_SSIZE0InternalFCFG_B0_SSIZE0 Register (Offset = 2430h) [Reset = 002C0008h]

Complex bit access types are encoded to fit into small table cells. Table 9-4 shows the codes that are used for access types in this section.

Table 9-4 FLASH Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

9.7.1.1 STAT Register (Offset = 1Ch) [Reset = 00000000h]

STAT is shown in Figure 9-9 and described in Table 9-5.

Return to the Summary Table.

FMC and Efuse Status

Figure 9-9 STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
EFUSE_BLANKEFUSE_TIMEOUTSPRS_BYTE_NOT_OKEFUSE_ERRCODE
R-0hR-0hR-0hR-0h
76543210
RESERVEDSAMHOLD_DISBUSYPOWER_MODE
R-0hR-0hR-0hR-0h
Table 9-5 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15EFUSE_BLANKR0hEfuse scanning detected if fuse ROM is blank:
0 : Not blank
1 : Blank
14EFUSE_TIMEOUTR0hEfuse scanning resulted in timeout error.
0 : No Timeout error
1 : Timeout Error
13SPRS_BYTE_NOT_OKR0hEfuse scanning resulted in scan chain Sparse byte error.
0 : No Sparse error
1 : Sparse Error
12-8EFUSE_ERRCODER0hSame as EFUSEERROR.CODE
7-3RESERVEDR0hReserved
2SAMHOLD_DISR0hStatus indicator of flash sample and hold sequencing logic. This bit will go to 1 some delay after CFG.DIS_IDLE is set to 1.
0: Not disabled
1: Sample and hold disabled and stable
1BUSYR0hFast version of the FMC FMSTAT.BUSY bit.
This flag is valid immediately after the operation setting it (FMSTAT.BUSY is delayed some cycles)
0 : Not busy
1 : Busy
0POWER_MODER0hPower state of the flash sub-system.
0 : Active
1 : Low power

9.7.1.2 CFG Register (Offset = 24h) [Reset = 00000000h]

CFG is shown in Figure 9-10 and described in Table 9-6.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-10 CFG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDSTANDBY_MODE_SEL
R-0hR/W-0h
76543210
STANDBY_PW_SELDIS_EFUSECLKDIS_READACCESSENABLE_SWINTFRESERVEDDIS_STANDBYDIS_IDLE
R/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h
Table 9-6 CFG Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8STANDBY_MODE_SELR/W0hInternal. Only to be used through TI provided API.
7-6STANDBY_PW_SELR/W0hInternal. Only to be used through TI provided API.
5DIS_EFUSECLKR/W0hInternal. Only to be used through TI provided API.
4DIS_READACCESSR/W0hInternal. Only to be used through TI provided API.
3ENABLE_SWINTFR/W0hInternal. Only to be used through TI provided API.
2RESERVEDR0hReserved
1DIS_STANDBYR/W0hInternal. Only to be used through TI provided API.
0DIS_IDLER/W0hInternal. Only to be used through TI provided API.

9.7.1.3 SYSCODE_START Register (Offset = 28h) [Reset = 00000000h]

SYSCODE_START is shown in Figure 9-11 and described in Table 9-7.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-11 SYSCODE_START Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSYSCODE_START
R-0hR/W-0h
Table 9-7 SYSCODE_START Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0SYSCODE_STARTR/W0hInternal. Only to be used through TI provided API.

9.7.1.4 FLASH_SIZE Register (Offset = 2Ch) [Reset = 00000000h]

FLASH_SIZE is shown in Figure 9-12 and described in Table 9-8.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-12 FLASH_SIZE Register
313029282726252423222120191817161514131211109876543210
RESERVEDSECTORS
R-0hR/W-0h
Table 9-8 FLASH_SIZE Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0SECTORSR/W0hInternal. Only to be used through TI provided API.

9.7.1.5 FWLOCK Register (Offset = 3Ch) [Reset = 00000000h]

FWLOCK is shown in Figure 9-13 and described in Table 9-9.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-13 FWLOCK Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDFWLOCK
R-0hR/W-0h
Table 9-9 FWLOCK Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0FWLOCKR/W0hInternal. Only to be used through TI provided API.

9.7.1.6 FWFLAG Register (Offset = 40h) [Reset = 00000000h]

FWFLAG is shown in Figure 9-14 and described in Table 9-10.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-14 FWFLAG Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDFWFLAG
R-0hR/W-0h
Table 9-10 FWFLAG Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0FWFLAGR/W0hInternal. Only to be used through TI provided API.

9.7.1.7 EFUSE Register (Offset = 1000h) [Reset = 00000000h]

EFUSE is shown in Figure 9-15 and described in Table 9-11.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-15 EFUSE Register
31302928272625242322212019181716
RESERVEDINSTRUCTIONRESERVED
R-0hR/W-0hR-0h
1514131211109876543210
DUMPWORD
R/W-0h
Table 9-11 EFUSE Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-24INSTRUCTIONR/W0hInternal. Only to be used through TI provided API.
23-16RESERVEDR0hReserved
15-0DUMPWORDR/W0hInternal. Only to be used through TI provided API.

9.7.1.8 EFUSEADDR Register (Offset = 1004h) [Reset = 00000000h]

EFUSEADDR is shown in Figure 9-16 and described in Table 9-12.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-16 EFUSEADDR Register
313029282726252423222120191817161514131211109876543210
RESERVEDBLOCKROW
R-0hR/W-0hR/W-0h
Table 9-12 EFUSEADDR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-11BLOCKR/W0hInternal. Only to be used through TI provided API.
10-0ROWR/W0hInternal. Only to be used through TI provided API.

9.7.1.9 DATAUPPER Register (Offset = 1008h) [Reset = 00000000h]

DATAUPPER is shown in Figure 9-17 and described in Table 9-13.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-17 DATAUPPER Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSPAREPREEN
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-13 DATAUPPER Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-3SPARER/W0hInternal. Only to be used through TI provided API.
2PR/W0hInternal. Only to be used through TI provided API.
1RR/W0hInternal. Only to be used through TI provided API.
0EENR/W0hInternal. Only to be used through TI provided API.

9.7.1.10 DATALOWER Register (Offset = 100Ch) [Reset = 00000000h]

DATALOWER is shown in Figure 9-18 and described in Table 9-14.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-18 DATALOWER Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
Table 9-14 DATALOWER Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hInternal. Only to be used through TI provided API.

9.7.1.11 EFUSECFG Register (Offset = 1010h) [Reset = 00000001h]

EFUSECFG is shown in Figure 9-19 and described in Table 9-15.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-19 EFUSECFG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDIDLEGATING
R-0hR/W-0h
76543210
RESERVEDSLAVEPOWERRESERVEDGATING
R-0hR/W-0hR-0hR/W-1h
Table 9-15 EFUSECFG Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8IDLEGATINGR/W0hInternal. Only to be used through TI provided API.
7-5RESERVEDR0hReserved
4-3SLAVEPOWERR/W0hInternal. Only to be used through TI provided API.
2-1RESERVEDR0hReserved
0GATINGR/W1hInternal. Only to be used through TI provided API.

9.7.1.12 EFUSESTAT Register (Offset = 1014h) [Reset = 00000001h]

EFUSESTAT is shown in Figure 9-20 and described in Table 9-16.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-20 EFUSESTAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESETDONE
R-0hR-1h
Table 9-16 EFUSESTAT Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0RESETDONER1hInternal. Only to be used through TI provided API.

9.7.1.13 ACC Register (Offset = 1018h) [Reset = 00000000h]

ACC is shown in Figure 9-21 and described in Table 9-17.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-21 ACC Register
313029282726252423222120191817161514131211109876543210
RESERVEDACCUMULATOR
R-0hR-0h
Table 9-17 ACC Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0ACCUMULATORR0hInternal. Only to be used through TI provided API.

9.7.1.14 BOUNDARY Register (Offset = 101Ch) [Reset = 00000000h]

BOUNDARY is shown in Figure 9-22 and described in Table 9-18.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-22 BOUNDARY Register
3130292827262524
RESERVED
R-0h
2322212019181716
DISROW0SPAREEFC_SELF_TEST_ERROREFC_INSTRUCTION_INFOEFC_INSTRUCTION_ERROREFC_AUTOLOAD_ERROROUTPUTENABLE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
OUTPUTENABLESYS_ECC_SELF_TEST_ENSYS_ECC_OVERRIDE_ENEFC_FDISYS_DIEID_AUTOLOAD_ENSYS_REPAIR_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
SYS_WS_READ_STATESINPUTENABLE
R/W-0hR/W-0h
Table 9-18 BOUNDARY Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23DISROW0R/W0hInternal. Only to be used through TI provided API.
22SPARER/W0hInternal. Only to be used through TI provided API.
21EFC_SELF_TEST_ERRORR/W0hInternal. Only to be used through TI provided API.
20EFC_INSTRUCTION_INFOR/W0hInternal. Only to be used through TI provided API.
19EFC_INSTRUCTION_ERRORR/W0hInternal. Only to be used through TI provided API.
18EFC_AUTOLOAD_ERRORR/W0hInternal. Only to be used through TI provided API.
17-14OUTPUTENABLER/W0hInternal. Only to be used through TI provided API.
13SYS_ECC_SELF_TEST_ENR/W0hInternal. Only to be used through TI provided API.
12SYS_ECC_OVERRIDE_ENR/W0hInternal. Only to be used through TI provided API.
11EFC_FDIR/W0hInternal. Only to be used through TI provided API.
10SYS_DIEID_AUTOLOAD_ENR/W0hInternal. Only to be used through TI provided API.
9-8SYS_REPAIR_ENR/W0hInternal. Only to be used through TI provided API.
7-4SYS_WS_READ_STATESR/W0hInternal. Only to be used through TI provided API.
3-0INPUTENABLER/W0hInternal. Only to be used through TI provided API.

9.7.1.15 EFUSEFLAG Register (Offset = 1020h) [Reset = 00000000h]

EFUSEFLAG is shown in Figure 9-23 and described in Table 9-19.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-23 EFUSEFLAG Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDKEY
R-0hR-0h
Table 9-19 EFUSEFLAG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0KEYR0hInternal. Only to be used through TI provided API.

9.7.1.16 EFUSEKEY Register (Offset = 1024h) [Reset = 00000000h]

EFUSEKEY is shown in Figure 9-24 and described in Table 9-20.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-24 EFUSEKEY Register
313029282726252423222120191817161514131211109876543210
CODE
R/W-0h
Table 9-20 EFUSEKEY Register Field Descriptions
BitFieldTypeResetDescription
31-0CODER/W0hInternal. Only to be used through TI provided API.

9.7.1.17 EFUSERELEASE Register (Offset = 1028h) [Reset = 00000000h]

EFUSERELEASE is shown in Figure 9-25 and described in Table 9-21.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-25 EFUSERELEASE Register
31302928272625242322212019181716
ODPYEARODPMONTHODPDAY
R-XR-XR-X
1514131211109876543210
EFUSEYEAREFUSEMONTHEFUSEDAY
R-XR-XR-X
Table 9-21 EFUSERELEASE Register Field Descriptions
BitFieldTypeResetDescription
31-25ODPYEARRXInternal. Only to be used through TI provided API.
24-21ODPMONTHRXInternal. Only to be used through TI provided API.
20-16ODPDAYRXInternal. Only to be used through TI provided API.
15-9EFUSEYEARRXInternal. Only to be used through TI provided API.
8-5EFUSEMONTHRXInternal. Only to be used through TI provided API.
4-0EFUSEDAYRXInternal. Only to be used through TI provided API.

9.7.1.18 EFUSEPINS Register (Offset = 102Ch) [Reset = 00000000h]

EFUSEPINS is shown in Figure 9-26 and described in Table 9-22.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-26 EFUSEPINS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
EFC_SELF_TEST_DONEEFC_SELF_TEST_ERRORSYS_ECC_SELF_TEST_ENEFC_INSTRUCTION_INFOEFC_INSTRUCTION_ERROREFC_AUTOLOAD_ERRORSYS_ECC_OVERRIDE_ENEFC_READY
R-XR-XR-XR-XR-XR-XR-XR-X
76543210
EFC_FCLRZSYS_DIEID_AUTOLOAD_ENSYS_REPAIR_ENSYS_WS_READ_STATES
R-XR-XR-XR-X
Table 9-22 EFUSEPINS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hInternal. Only to be used through TI provided API.
15EFC_SELF_TEST_DONERXInternal. Only to be used through TI provided API.
14EFC_SELF_TEST_ERRORRXInternal. Only to be used through TI provided API.
13SYS_ECC_SELF_TEST_ENRXInternal. Only to be used through TI provided API.
12EFC_INSTRUCTION_INFORXInternal. Only to be used through TI provided API.
11EFC_INSTRUCTION_ERRORRXInternal. Only to be used through TI provided API.
10EFC_AUTOLOAD_ERRORRXInternal. Only to be used through TI provided API.
9SYS_ECC_OVERRIDE_ENRXInternal. Only to be used through TI provided API.
8EFC_READYRXInternal. Only to be used through TI provided API.
7EFC_FCLRZRXInternal. Only to be used through TI provided API.
6SYS_DIEID_AUTOLOAD_ENRXInternal. Only to be used through TI provided API.
5-4SYS_REPAIR_ENRXInternal. Only to be used through TI provided API.
3-0SYS_WS_READ_STATESRXInternal. Only to be used through TI provided API.

9.7.1.19 EFUSECRA Register (Offset = 1030h) [Reset = 00000000h]

EFUSECRA is shown in Figure 9-27 and described in Table 9-23.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-27 EFUSECRA Register
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-0hR/W-0h
Table 9-23 EFUSECRA Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0DATAR/W0hInternal. Only to be used through TI provided API.

9.7.1.20 EFUSEREAD Register (Offset = 1034h) [Reset = 00000000h]

EFUSEREAD is shown in Figure 9-28 and described in Table 9-24.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-28 EFUSEREAD Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDATABIT
R-0hR/W-0h
76543210
READCLOCKDEBUGSPAREMARGIN
R/W-0hR/W-0hR/W-0hR/W-0h
Table 9-24 EFUSEREAD Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-8DATABITR/W0hInternal. Only to be used through TI provided API.
7-4READCLOCKR/W0hInternal. Only to be used through TI provided API.
3DEBUGR/W0hInternal. Only to be used through TI provided API.
2SPARER/W0hInternal. Only to be used through TI provided API.
1-0MARGINR/W0hInternal. Only to be used through TI provided API.

9.7.1.21 EFUSEPROGRAM Register (Offset = 1038h) [Reset = 00000000h]

EFUSEPROGRAM is shown in Figure 9-29 and described in Table 9-25.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-29 EFUSEPROGRAM Register
3130292827262524
RESERVEDCOMPAREDISABLECLOCKSTALL
R-0hR/W-0hR/W-0h
2322212019181716
CLOCKSTALL
R/W-0h
15141312111098
CLOCKSTALLVPPTOVDDITERATIONSWRITECLOCK
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
WRITECLOCK
R/W-0h
Table 9-25 EFUSEPROGRAM Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30COMPAREDISABLER/W0hInternal. Only to be used through TI provided API.
29-14CLOCKSTALLR/W0hInternal. Only to be used through TI provided API.
13VPPTOVDDR/W0hInternal. Only to be used through TI provided API.
12-9ITERATIONSR/W0hInternal. Only to be used through TI provided API.
8-0WRITECLOCKR/W0hInternal. Only to be used through TI provided API.

9.7.1.22 EFUSEERROR Register (Offset = 103Ch) [Reset = 00000000h]

EFUSEERROR is shown in Figure 9-30 and described in Table 9-26.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-30 EFUSEERROR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDONECODE
R-0hR/W-0hR/W-0h
Table 9-26 EFUSEERROR Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5DONER/W0hInternal. Only to be used through TI provided API.
4-0CODER/W0hInternal. Only to be used through TI provided API.

9.7.1.23 SINGLEBIT Register (Offset = 1040h) [Reset = 00000000h]

SINGLEBIT is shown in Figure 9-31 and described in Table 9-27.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-31 SINGLEBIT Register
3130292827262524
FROMN
R-0h
2322212019181716
FROMN
R-0h
15141312111098
FROMN
R-0h
76543210
FROMNFROM0
R-0hR-0h
Table 9-27 SINGLEBIT Register Field Descriptions
BitFieldTypeResetDescription
31-1FROMNR0hInternal. Only to be used through TI provided API.
0FROM0R0hInternal. Only to be used through TI provided API.

9.7.1.24 TWOBIT Register (Offset = 1044h) [Reset = 00000000h]

TWOBIT is shown in Figure 9-32 and described in Table 9-28.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-32 TWOBIT Register
3130292827262524
FROMN
R-0h
2322212019181716
FROMN
R-0h
15141312111098
FROMN
R-0h
76543210
FROMNFROM0
R-0hR-0h
Table 9-28 TWOBIT Register Field Descriptions
BitFieldTypeResetDescription
31-1FROMNR0hInternal. Only to be used through TI provided API.
0FROM0R0hInternal. Only to be used through TI provided API.

9.7.1.25 SELFTESTCYC Register (Offset = 1048h) [Reset = 00000000h]

SELFTESTCYC is shown in Figure 9-33 and described in Table 9-29.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-33 SELFTESTCYC Register
313029282726252423222120191817161514131211109876543210
CYCLES
R/W-0h
Table 9-29 SELFTESTCYC Register Field Descriptions
BitFieldTypeResetDescription
31-0CYCLESR/W0hInternal. Only to be used through TI provided API.

9.7.1.26 SELFTESTSIGN Register (Offset = 104Ch) [Reset = 00000000h]

SELFTESTSIGN is shown in Figure 9-34 and described in Table 9-30.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-34 SELFTESTSIGN Register
313029282726252423222120191817161514131211109876543210
SIGNATURE
R/W-0h
Table 9-30 SELFTESTSIGN Register Field Descriptions
BitFieldTypeResetDescription
31-0SIGNATURER/W0hInternal. Only to be used through TI provided API.

9.7.1.27 FRDCTL Register (Offset = 2000h) [Reset = 00000200h]

FRDCTL is shown in Figure 9-35 and described in Table 9-31.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-35 FRDCTL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDRWAITRESERVED
R-0hR/W-2hR-0h
Table 9-31 FRDCTL Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-8RWAITR/W2hInternal. Only to be used through TI provided API.
7-0RESERVEDR0hReserved

9.7.1.28 FSPRD Register (Offset = 2004h) [Reset = 00000000h]

FSPRD is shown in Figure 9-36 and described in Table 9-32.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-36 FSPRD Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RMBSEMRESERVEDRM1RM0
R/W-0hR-0hR/W-0hR/W-0h
Table 9-32 FSPRD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8RMBSEMR/W0hInternal. Only to be used through TI provided API.
7-2RESERVEDR0hReserved
1RM1R/W0hInternal. Only to be used through TI provided API.
0RM0R/W0hInternal. Only to be used through TI provided API.

9.7.1.29 FEDACCTL1 Register (Offset = 2008h) [Reset = 00000000h]

FEDACCTL1 is shown in Figure 9-37 and described in Table 9-33.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-37 FEDACCTL1 Register
3130292827262524
RESERVEDSUSP_IGNR
R-0hR/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 9-33 FEDACCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24SUSP_IGNRR/W0hInternal. Only to be used through TI provided API.
23-0RESERVEDR0hReserved

9.7.1.30 FEDACSTAT Register (Offset = 201Ch) [Reset = 00000000h]

FEDACSTAT is shown in Figure 9-38 and described in Table 9-34.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-38 FEDACSTAT Register
3130292827262524
RESERVEDRVF_INTFSM_DONE
R-0hR/W1C-0hR/W1C-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 9-34 FEDACSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25RVF_INTR/W1C0hInternal. Only to be used through TI provided API.
24FSM_DONER/W1C0hInternal. Only to be used through TI provided API.
23-0RESERVEDR0hReserved

9.7.1.31 FBPROT Register (Offset = 2030h) [Reset = 00000000h]

FBPROT is shown in Figure 9-39 and described in Table 9-35.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-39 FBPROT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPROTL1DIS
R-0hR/W-0h
Table 9-35 FBPROT Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0PROTL1DISR/W0hInternal. Only to be used through TI provided API.

9.7.1.32 FBSE Register (Offset = 2034h) [Reset = 00000000h]

FBSE is shown in Figure 9-40 and described in Table 9-36.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-40 FBSE Register
313029282726252423222120191817161514131211109876543210
RESERVEDBSE
R-0hR/W-0h
Table 9-36 FBSE Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0BSER/W0hInternal. Only to be used through TI provided API.

9.7.1.33 FBBUSY Register (Offset = 2038h) [Reset = 000000FEh]

FBBUSY is shown in Figure 9-41 and described in Table 9-37.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-41 FBBUSY Register
313029282726252423222120191817161514131211109876543210
RESERVEDBUSY
R-0hR-FEh
Table 9-37 FBBUSY Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0BUSYRFEhInternal. Only to be used through TI provided API.

9.7.1.34 FBAC Register (Offset = 203Ch) [Reset = 0000000Fh]

FBAC is shown in Figure 9-42 and described in Table 9-38.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-42 FBAC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDOTPPROTDIS
R-0hR/W-0h
15141312111098
BAGP
R/W-0h
76543210
VREADS
R/W-Fh
Table 9-38 FBAC Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16OTPPROTDISR/W0hInternal. Only to be used through TI provided API.
15-8BAGPR/W0hInternal. Only to be used through TI provided API.
7-0VREADSR/WFhInternal. Only to be used through TI provided API.

9.7.1.35 FBFALLBACK Register (Offset = 2040h) [Reset = 0505FFFFh]

FBFALLBACK is shown in Figure 9-43 and described in Table 9-39.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-43 FBFALLBACK Register
3130292827262524
RESERVEDFSM_PWRSAV
R-0hR/W-5h
2322212019181716
RESERVEDREG_PWRSAV
R-0hR/W-5h
15141312111098
BANKPWR7BANKPWR6BANKPWR5BANKPWR4
R/W-3hR/W-3hR/W-3hR/W-3h
76543210
BANKPWR3BANKPWR2BANKPWR1BANKPWR0
R/W-3hR/W-3hR/W-3hR/W-3h
Table 9-39 FBFALLBACK Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27-24FSM_PWRSAVR/W5hInternal. Only to be used through TI provided API.
23-20RESERVEDR0hReserved
19-16REG_PWRSAVR/W5hInternal. Only to be used through TI provided API.
15-14BANKPWR7R/W3hInternal. Only to be used through TI provided API.
13-12BANKPWR6R/W3hInternal. Only to be used through TI provided API.
11-10BANKPWR5R/W3hInternal. Only to be used through TI provided API.
9-8BANKPWR4R/W3hInternal. Only to be used through TI provided API.
7-6BANKPWR3R/W3hInternal. Only to be used through TI provided API.
5-4BANKPWR2R/W3hInternal. Only to be used through TI provided API.
3-2BANKPWR1R/W3hInternal. Only to be used through TI provided API.
1-0BANKPWR0R/W3hInternal. Only to be used through TI provided API.

9.7.1.36 FBPRDY Register (Offset = 2044h) [Reset = 00FF00FEh]

FBPRDY is shown in Figure 9-44 and described in Table 9-40.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-44 FBPRDY Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDBANKBUSY
R-0hR-1h
15141312111098
PUMPRDYRESERVED
R-0hR-0h
76543210
RESERVEDBANKRDY
R-0hR-0h
Table 9-40 FBPRDY Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16BANKBUSYR1hInternal. Only to be used through TI provided API.
15PUMPRDYR0hInternal. Only to be used through TI provided API.
14-1RESERVEDR0hReserved
0BANKRDYR0hInternal. Only to be used through TI provided API.

9.7.1.37 FPAC1 Register (Offset = 2048h) [Reset = 02082081h]

FPAC1 is shown in Figure 9-45 and described in Table 9-41.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-45 FPAC1 Register
3130292827262524
RESERVEDPSLEEPTDIS
R-0hR/W-208h
2322212019181716
PSLEEPTDIS
R/W-208h
15141312111098
PUMPRESET_PW
R/W-208h
76543210
PUMPRESET_PWRESERVEDPUMPPWR
R/W-208hR-0hR/W-1h
Table 9-41 FPAC1 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27-16PSLEEPTDISR/W208hInternal. Only to be used through TI provided API.
15-4PUMPRESET_PWR/W208hInternal. Only to be used through TI provided API.
3-2RESERVEDR0hReserved
1-0PUMPPWRR/W1hInternal. Only to be used through TI provided API.

9.7.1.38 FPAC2 Register (Offset = 204Ch) [Reset = 00000000h]

FPAC2 is shown in Figure 9-46 and described in Table 9-42.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-46 FPAC2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPAGP
R-0hR/W-0h
Table 9-42 FPAC2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0PAGPR/W0hInternal. Only to be used through TI provided API.

9.7.1.39 FMAC Register (Offset = 2050h) [Reset = 00000000h]

FMAC is shown in Figure 9-47 and described in Table 9-43.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-47 FMAC Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDBANK
R-0hR/W-0h
Table 9-43 FMAC Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0BANKR/W0hInternal. Only to be used through TI provided API.

9.7.1.40 FMSTAT Register (Offset = 2054h) [Reset = 00000000h]

FMSTAT is shown in Figure 9-48 and described in Table 9-44.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-48 FMSTAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRVSUSPRDVER
R-0hR-0hR-0h
15141312111098
RVFILADBFPGVPCVEVCVBUSY
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
ERSPGMINVDATCSTATVOLSTATESUSPPSUSPSLOCK
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 9-44 FMSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17RVSUSPR0hInternal. Only to be used through TI provided API.
16RDVERR0hInternal. Only to be used through TI provided API.
15RVFR0hInternal. Only to be used through TI provided API.
14ILAR0hInternal. Only to be used through TI provided API.
13DBFR0hInternal. Only to be used through TI provided API.
12PGVR0hInternal. Only to be used through TI provided API.
11PCVR0hInternal. Only to be used through TI provided API.
10EVR0hInternal. Only to be used through TI provided API.
9CVR0hInternal. Only to be used through TI provided API.
8BUSYR0hInternal. Only to be used through TI provided API.
7ERSR0hInternal. Only to be used through TI provided API.
6PGMR0hInternal. Only to be used through TI provided API.
5INVDATR0hInternal. Only to be used through TI provided API.
4CSTATR0hInternal. Only to be used through TI provided API.
3VOLSTATR0hInternal. Only to be used through TI provided API.
2ESUSPR0hInternal. Only to be used through TI provided API.
1PSUSPR0hInternal. Only to be used through TI provided API.
0SLOCKR0hInternal. Only to be used through TI provided API.

9.7.1.41 FLOCK Register (Offset = 2064h) [Reset = 000055AAh]

FLOCK is shown in Figure 9-49 and described in Table 9-45.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-49 FLOCK Register
313029282726252423222120191817161514131211109876543210
RESERVEDENCOM
R-0hR/W-55AAh
Table 9-45 FLOCK Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0ENCOMR/W55AAhInternal. Only to be used through TI provided API.

9.7.1.42 FVREADCT Register (Offset = 2080h) [Reset = 00000008h]

FVREADCT is shown in Figure 9-50 and described in Table 9-46.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-50 FVREADCT Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDVREADCT
R-0hR/W-8h
Table 9-46 FVREADCT Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VREADCTR/W8hInternal. Only to be used through TI provided API.

9.7.1.43 FVHVCT1 Register (Offset = 2084h) [Reset = 00840088h]

FVHVCT1 is shown in Figure 9-51 and described in Table 9-47.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-51 FVHVCT1 Register
31302928272625242322212019181716
RESERVEDTRIM13_EVHVCT_E
R-0hR/W-8hR/W-4h
1514131211109876543210
RESERVEDTRIM13_PVVHVCT_PV
R-0hR/W-8hR/W-8h
Table 9-47 FVHVCT1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-20TRIM13_ER/W8hInternal. Only to be used through TI provided API.
19-16VHVCT_ER/W4hInternal. Only to be used through TI provided API.
15-8RESERVEDR0hReserved
7-4TRIM13_PVR/W8hInternal. Only to be used through TI provided API.
3-0VHVCT_PVR/W8hInternal. Only to be used through TI provided API.

9.7.1.44 FVHVCT2 Register (Offset = 2088h) [Reset = 00A20000h]

FVHVCT2 is shown in Figure 9-52 and described in Table 9-48.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-52 FVHVCT2 Register
31302928272625242322212019181716
RESERVEDTRIM13_PVHVCT_P
R-0hR/W-AhR/W-2h
1514131211109876543210
RESERVED
R-0h
Table 9-48 FVHVCT2 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-20TRIM13_PR/WAhInternal. Only to be used through TI provided API.
19-16VHVCT_PR/W2hInternal. Only to be used through TI provided API.
15-0RESERVEDR0hReserved

9.7.1.45 FVHVCT3 Register (Offset = 208Ch) [Reset = 000F0000h]

FVHVCT3 is shown in Figure 9-53 and described in Table 9-49.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-53 FVHVCT3 Register
31302928272625242322212019181716
RESERVEDWCT
R-0hR/W-Fh
1514131211109876543210
RESERVEDVHVCT_READ
R-0hR/W-0h
Table 9-49 FVHVCT3 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16WCTR/WFhInternal. Only to be used through TI provided API.
15-4RESERVEDR0hReserved
3-0VHVCT_READR/W0hInternal. Only to be used through TI provided API.

9.7.1.46 FVNVCT Register (Offset = 2090h) [Reset = 00000800h]

FVNVCT is shown in Figure 9-54 and described in Table 9-50.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-54 FVNVCT Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDVCG2P5CTRESERVEDVIN_CT
R-0hR/W-8hR-0hR/W-0h
Table 9-50 FVNVCT Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0hReserved
12-8VCG2P5CTR/W8hInternal. Only to be used through TI provided API.
7-5RESERVEDR0hReserved
4-0VIN_CTR/W0hInternal. Only to be used through TI provided API.

9.7.1.47 FVSLP Register (Offset = 2094h) [Reset = 00008000h]

FVSLP is shown in Figure 9-55 and described in Table 9-51.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-55 FVSLP Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
VSL_PRESERVED
R/W-8hR-0h
Table 9-51 FVSLP Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-12VSL_PR/W8hInternal. Only to be used through TI provided API.
11-0RESERVEDR0hReserved

9.7.1.48 FVWLCT Register (Offset = 2098h) [Reset = 00000008h]

FVWLCT is shown in Figure 9-56 and described in Table 9-52.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-56 FVWLCT Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDVWLCT_P
R-0hR/W-8h
Table 9-52 FVWLCT Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4-0VWLCT_PR/W8hInternal. Only to be used through TI provided API.

9.7.1.49 FEFUSECTL Register (Offset = 209Ch) [Reset = 0701010Ah]

FEFUSECTL is shown in Figure 9-57 and described in Table 9-53.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-57 FEFUSECTL Register
3130292827262524
RESERVEDCHAIN_SEL
R-0hR/W-7h
2322212019181716
RESERVEDWRITE_ENBP_SEL
R-0hR/W-0hR/W-1h
15141312111098
RESERVEDEF_CLRZ
R-0hR/W-1h
76543210
RESERVEDEF_TESTEFUSE_EN
R-0hR/W-0hR/W-Ah
Table 9-53 FEFUSECTL Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR0hReserved
26-24CHAIN_SELR/W7hInternal. Only to be used through TI provided API.
23-18RESERVEDR0hReserved
17WRITE_ENR/W0hInternal. Only to be used through TI provided API.
16BP_SELR/W1hInternal. Only to be used through TI provided API.
15-9RESERVEDR0hReserved
8EF_CLRZR/W1hInternal. Only to be used through TI provided API.
7-5RESERVEDR0hReserved
4EF_TESTR/W0hInternal. Only to be used through TI provided API.
3-0EFUSE_ENR/WAhInternal. Only to be used through TI provided API.

9.7.1.50 FEFUSESTAT Register (Offset = 20A0h) [Reset = 00000000h]

FEFUSESTAT is shown in Figure 9-58 and described in Table 9-54.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-58 FEFUSESTAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSHIFT_DONE
R-0hR/W1C-0h
Table 9-54 FEFUSESTAT Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0SHIFT_DONER/W1C0hInternal. Only to be used through TI provided API.

9.7.1.51 FEFUSEDATA Register (Offset = 20A4h) [Reset = 00000000h]

FEFUSEDATA is shown in Figure 9-59 and described in Table 9-55.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-59 FEFUSEDATA Register
313029282726252423222120191817161514131211109876543210
FEFUSEDATA
R/W-0h
Table 9-55 FEFUSEDATA Register Field Descriptions
BitFieldTypeResetDescription
31-0FEFUSEDATAR/W0hInternal. Only to be used through TI provided API.

9.7.1.52 FSEQPMP Register (Offset = 20A8h) [Reset = 85080000h]

FSEQPMP is shown in Figure 9-60 and described in Table 9-56.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-60 FSEQPMP Register
3130292827262524
RESERVEDTRIM_3P4
R/W-8hR/W-5h
2322212019181716
RESERVEDTRIM_1P7TRIM_0P8
R-0hR/W-0hR/W-8h
15141312111098
RESERVEDVIN_AT_XRESERVEDVIN_BY_PASS
R-0hR/W-0hR-0hR/W-0h
76543210
RESERVED
R-0h
Table 9-56 FSEQPMP Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W8hInternal. Only to be used through TI provided API.
27-24TRIM_3P4R/W5hInternal. Only to be used through TI provided API.
23-22RESERVEDR0hReserved
21-20TRIM_1P7R/W0hInternal. Only to be used through TI provided API.
19-16TRIM_0P8R/W8hInternal. Only to be used through TI provided API.
15RESERVEDR0hReserved
14-12VIN_AT_XR/W0hInternal. Only to be used through TI provided API.
11-9RESERVEDR0hReserved
8VIN_BY_PASSR/W0hInternal. Only to be used through TI provided API.
7-0RESERVEDR0hReserved

9.7.1.53 FBSTROBES Register (Offset = 2100h) [Reset = 00000104h]

FBSTROBES is shown in Figure 9-61 and described in Table 9-57.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-61 FBSTROBES Register
3130292827262524
RESERVEDECBIT
R-0hR/W-0h
2322212019181716
RESERVEDRWAIT2_FLCLKRWAIT_FLCLKFLCLKEN
R-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDCTRLENZ
R-0hR/W-1h
76543210
RESERVEDNOCOLREDPRECOLTI_OTPOTPTEZRESERVED
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR-0h
Table 9-57 FBSTROBES Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24ECBITR/W0hInternal. Only to be used through TI provided API.
23-19RESERVEDR0hReserved
18RWAIT2_FLCLKR/W0hInternal. Only to be used through TI provided API.
17RWAIT_FLCLKR/W0hInternal. Only to be used through TI provided API.
16FLCLKENR/W0hInternal. Only to be used through TI provided API.
15-9RESERVEDR0hReserved
8CTRLENZR/W1hInternal. Only to be used through TI provided API.
7RESERVEDR0hReserved
6NOCOLREDR/W0hInternal. Only to be used through TI provided API.
5PRECOLR/W0hInternal. Only to be used through TI provided API.
4TI_OTPR/W0hInternal. Only to be used through TI provided API.
3OTPR/W0hInternal. Only to be used through TI provided API.
2TEZR/W1hInternal. Only to be used through TI provided API.
1-0RESERVEDR0hReserved

9.7.1.54 FPSTROBES Register (Offset = 2104h) [Reset = 00000103h]

FPSTROBES is shown in Figure 9-62 and described in Table 9-58.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-62 FPSTROBES Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDEXECUTEZ
R-0hR/W-1h
76543210
RESERVEDV3PWRDNZV5PWRDNZ
R-0hR/W-1hR/W-1h
Table 9-58 FPSTROBES Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8EXECUTEZR/W1hInternal. Only to be used through TI provided API.
7-2RESERVEDR0hReserved
1V3PWRDNZR/W1hInternal. Only to be used through TI provided API.
0V5PWRDNZR/W1hInternal. Only to be used through TI provided API.

9.7.1.55 FBMODE Register (Offset = 2108h) [Reset = 00000000h]

FBMODE is shown in Figure 9-63 and described in Table 9-59.

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Internal. Only to be used through TI provided API.

Figure 9-63 FBMODE Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDMODE
R-0hR/W-0h
Table 9-59 FBMODE Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0MODER/W0hInternal. Only to be used through TI provided API.

9.7.1.56 FTCR Register (Offset = 210Ch) [Reset = 00000000h]

FTCR is shown in Figure 9-64 and described in Table 9-60.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-64 FTCR Register
313029282726252423222120191817161514131211109876543210
RESERVEDTCR
R-0hR/W-0h
Table 9-60 FTCR Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0TCRR/W0hInternal. Only to be used through TI provided API.

9.7.1.57 FADDR Register (Offset = 2110h) [Reset = 00000000h]

FADDR is shown in Figure 9-65 and described in Table 9-61.

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Internal. Only to be used through TI provided API.

Figure 9-65 FADDR Register
313029282726252423222120191817161514131211109876543210
FADDR
R/W-0h
Table 9-61 FADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0FADDRR/W0hInternal. Only to be used through TI provided API.

9.7.1.58 FTCTL Register (Offset = 211Ch) [Reset = 00000000h]

FTCTL is shown in Figure 9-66 and described in Table 9-62.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-66 FTCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDWDATA_BLK_CLR
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTEST_ENRESERVED
R-0hR/W-0hR-0h
Table 9-62 FTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16WDATA_BLK_CLRR/W0hInternal. Only to be used through TI provided API.
15-2RESERVEDR0hReserved
1TEST_ENR/W0hInternal. Only to be used through TI provided API.
0RESERVEDR0hReserved

9.7.1.59 FWPWRITE0 Register (Offset = 2120h) [Reset = FFFFFFFFh]

FWPWRITE0 is shown in Figure 9-67 and described in Table 9-63.

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Internal. Only to be used through TI provided API.

Figure 9-67 FWPWRITE0 Register
313029282726252423222120191817161514131211109876543210
FWPWRITE0
R/W-FFFFFFFFh
Table 9-63 FWPWRITE0 Register Field Descriptions
BitFieldTypeResetDescription
31-0FWPWRITE0R/WFFFFFFFFhInternal. Only to be used through TI provided API.

9.7.1.60 FWPWRITE1 Register (Offset = 2124h) [Reset = FFFFFFFFh]

FWPWRITE1 is shown in Figure 9-68 and described in Table 9-64.

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Internal. Only to be used through TI provided API.

Figure 9-68 FWPWRITE1 Register
313029282726252423222120191817161514131211109876543210
FWPWRITE1
R/W-FFFFFFFFh
Table 9-64 FWPWRITE1 Register Field Descriptions
BitFieldTypeResetDescription
31-0FWPWRITE1R/WFFFFFFFFhInternal. Only to be used through TI provided API.

9.7.1.61 FWPWRITE2 Register (Offset = 2128h) [Reset = FFFFFFFFh]

FWPWRITE2 is shown in Figure 9-69 and described in Table 9-65.

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Internal. Only to be used through TI provided API.

Figure 9-69 FWPWRITE2 Register
313029282726252423222120191817161514131211109876543210
FWPWRITE2
R/W-FFFFFFFFh
Table 9-65 FWPWRITE2 Register Field Descriptions
BitFieldTypeResetDescription
31-0FWPWRITE2R/WFFFFFFFFhInternal. Only to be used through TI provided API.

9.7.1.62 FWPWRITE3 Register (Offset = 212Ch) [Reset = FFFFFFFFh]

FWPWRITE3 is shown in Figure 9-70 and described in Table 9-66.

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Internal. Only to be used through TI provided API.

Figure 9-70 FWPWRITE3 Register
313029282726252423222120191817161514131211109876543210
FWPWRITE3
R/W-FFFFFFFFh
Table 9-66 FWPWRITE3 Register Field Descriptions
BitFieldTypeResetDescription
31-0FWPWRITE3R/WFFFFFFFFhInternal. Only to be used through TI provided API.

9.7.1.63 FWPWRITE4 Register (Offset = 2130h) [Reset = FFFFFFFFh]

FWPWRITE4 is shown in Figure 9-71 and described in Table 9-67.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-71 FWPWRITE4 Register
313029282726252423222120191817161514131211109876543210
FWPWRITE4
R/W-FFFFFFFFh
Table 9-67 FWPWRITE4 Register Field Descriptions
BitFieldTypeResetDescription
31-0FWPWRITE4R/WFFFFFFFFhInternal. Only to be used through TI provided API.

9.7.1.64 FWPWRITE5 Register (Offset = 2134h) [Reset = FFFFFFFFh]

FWPWRITE5 is shown in Figure 9-72 and described in Table 9-68.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-72 FWPWRITE5 Register
313029282726252423222120191817161514131211109876543210
FWPWRITE5
R/W-FFFFFFFFh
Table 9-68 FWPWRITE5 Register Field Descriptions
BitFieldTypeResetDescription
31-0FWPWRITE5R/WFFFFFFFFhInternal. Only to be used through TI provided API.

9.7.1.65 FWPWRITE6 Register (Offset = 2138h) [Reset = FFFFFFFFh]

FWPWRITE6 is shown in Figure 9-73 and described in Table 9-69.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-73 FWPWRITE6 Register
313029282726252423222120191817161514131211109876543210
FWPWRITE6
R/W-FFFFFFFFh
Table 9-69 FWPWRITE6 Register Field Descriptions
BitFieldTypeResetDescription
31-0FWPWRITE6R/WFFFFFFFFhInternal. Only to be used through TI provided API.

9.7.1.66 FWPWRITE7 Register (Offset = 213Ch) [Reset = FFFFFFFFh]

FWPWRITE7 is shown in Figure 9-74 and described in Table 9-70.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-74 FWPWRITE7 Register
313029282726252423222120191817161514131211109876543210
FWPWRITE7
R/W-FFFFFFFFh
Table 9-70 FWPWRITE7 Register Field Descriptions
BitFieldTypeResetDescription
31-0FWPWRITE7R/WFFFFFFFFhInternal. Only to be used through TI provided API.

9.7.1.67 FWPWRITE_ECC Register (Offset = 2140h) [Reset = FFFFFFFFh]

FWPWRITE_ECC is shown in Figure 9-75 and described in Table 9-71.

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Internal. Only to be used through TI provided API.

Figure 9-75 FWPWRITE_ECC Register
31302928272625242322212019181716
ECCBYTES07_00ECCBYTES15_08
R/W-FFhR/W-FFh
1514131211109876543210
ECCBYTES23_16ECCBYTES31_24
R/W-FFhR/W-FFh
Table 9-71 FWPWRITE_ECC Register Field Descriptions
BitFieldTypeResetDescription
31-24ECCBYTES07_00R/WFFhInternal. Only to be used through TI provided API.
23-16ECCBYTES15_08R/WFFhInternal. Only to be used through TI provided API.
15-8ECCBYTES23_16R/WFFhInternal. Only to be used through TI provided API.
7-0ECCBYTES31_24R/WFFhInternal. Only to be used through TI provided API.

9.7.1.68 FSWSTAT Register (Offset = 2144h) [Reset = 00000001h]

FSWSTAT is shown in Figure 9-76 and described in Table 9-72.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-76 FSWSTAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSAFELV
R-0hR-1h
Table 9-72 FSWSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0SAFELVR1hInternal. Only to be used through TI provided API.

9.7.1.69 FSM_GLBCTL Register (Offset = 2200h) [Reset = 00000001h]

FSM_GLBCTL is shown in Figure 9-77 and described in Table 9-73.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-77 FSM_GLBCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLKSEL
R-0hR-1h
Table 9-73 FSM_GLBCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0CLKSELR1hInternal. Only to be used through TI provided API.

9.7.1.70 FSM_STATE Register (Offset = 2204h) [Reset = 00000C00h]

FSM_STATE is shown in Figure 9-78 and described in Table 9-74.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-78 FSM_STATE Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCTRLENZEXECUTEZRESERVEDFSM_ACT
R-0hR-1hR-1hR-0hR-0h
76543210
TIOTP_ACTOTP_ACTRESERVED
R-0hR-0hR-0h
Table 9-74 FSM_STATE Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11CTRLENZR1hInternal. Only to be used through TI provided API.
10EXECUTEZR1hInternal. Only to be used through TI provided API.
9RESERVEDR0hReserved
8FSM_ACTR0hInternal. Only to be used through TI provided API.
7TIOTP_ACTR0hInternal. Only to be used through TI provided API.
6OTP_ACTR0hInternal. Only to be used through TI provided API.
5-0RESERVEDR0hReserved

9.7.1.71 FSM_STAT Register (Offset = 2208h) [Reset = 00000004h]

FSM_STAT is shown in Figure 9-79 and described in Table 9-75.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-79 FSM_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDNON_OPOVR_PUL_CNTINV_DAT
R-0hR-1hR-0hR-0h
Table 9-75 FSM_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2NON_OPR1hInternal. Only to be used through TI provided API.
1OVR_PUL_CNTR0hInternal. Only to be used through TI provided API.
0INV_DATR0hInternal. Only to be used through TI provided API.

9.7.1.72 FSM_CMD Register (Offset = 220Ch) [Reset = 00000000h]

FSM_CMD is shown in Figure 9-80 and described in Table 9-76.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-80 FSM_CMD Register
313029282726252423222120191817161514131211109876543210
RESERVEDFSMCMD
R-0hR/W-0h
Table 9-76 FSM_CMD Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0FSMCMDR/W0hInternal. Only to be used through TI provided API.

9.7.1.73 FSM_PE_OSU Register (Offset = 2210h) [Reset = 00000000h]

FSM_PE_OSU is shown in Figure 9-81 and described in Table 9-77.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-81 FSM_PE_OSU Register
313029282726252423222120191817161514131211109876543210
RESERVEDPGM_OSUERA_OSU
R-0hR/W-0hR/W-0h
Table 9-77 FSM_PE_OSU Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8PGM_OSUR/W0hInternal. Only to be used through TI provided API.
7-0ERA_OSUR/W0hInternal. Only to be used through TI provided API.

9.7.1.74 FSM_VSTAT Register (Offset = 2214h) [Reset = 00003000h]

FSM_VSTAT is shown in Figure 9-82 and described in Table 9-78.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-82 FSM_VSTAT Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
VSTAT_CNTRESERVED
R/W-3hR-0h
Table 9-78 FSM_VSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-12VSTAT_CNTR/W3hInternal. Only to be used through TI provided API.
11-0RESERVEDR0hReserved

9.7.1.75 FSM_PE_VSU Register (Offset = 2218h) [Reset = 00000000h]

FSM_PE_VSU is shown in Figure 9-83 and described in Table 9-79.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-83 FSM_PE_VSU Register
313029282726252423222120191817161514131211109876543210
RESERVEDPGM_VSUERA_VSU
R-0hR/W-0hR/W-0h
Table 9-79 FSM_PE_VSU Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8PGM_VSUR/W0hInternal. Only to be used through TI provided API.
7-0ERA_VSUR/W0hInternal. Only to be used through TI provided API.

9.7.1.76 FSM_CMP_VSU Register (Offset = 221Ch) [Reset = 00000000h]

FSM_CMP_VSU is shown in Figure 9-84 and described in Table 9-80.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-84 FSM_CMP_VSU Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
ADD_EXZRESERVED
R/W-0hR-0h
Table 9-80 FSM_CMP_VSU Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-12ADD_EXZR/W0hInternal. Only to be used through TI provided API.
11-0RESERVEDR0hReserved

9.7.1.77 FSM_EX_VAL Register (Offset = 2220h) [Reset = 00000301h]

FSM_EX_VAL is shown in Figure 9-85 and described in Table 9-81.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-85 FSM_EX_VAL Register
313029282726252423222120191817161514131211109876543210
RESERVEDREP_VSUEXE_VALD
R-0hR/W-3hR/W-1h
Table 9-81 FSM_EX_VAL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8REP_VSUR/W3hInternal. Only to be used through TI provided API.
7-0EXE_VALDR/W1hInternal. Only to be used through TI provided API.

9.7.1.78 FSM_RD_H Register (Offset = 2224h) [Reset = 0000005Ah]

FSM_RD_H is shown in Figure 9-86 and described in Table 9-82.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-86 FSM_RD_H Register
313029282726252423222120191817161514131211109876543210
RESERVEDRD_H
R-0hR/W-5Ah
Table 9-82 FSM_RD_H Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0RD_HR/W5AhInternal. Only to be used through TI provided API.

9.7.1.79 FSM_P_OH Register (Offset = 2228h) [Reset = 00000100h]

FSM_P_OH is shown in Figure 9-87 and described in Table 9-83.

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Internal. Only to be used through TI provided API.

Figure 9-87 FSM_P_OH Register
313029282726252423222120191817161514131211109876543210
RESERVEDPGM_OHRESERVED
R-0hR/W-1hR-0h
Table 9-83 FSM_P_OH Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8PGM_OHR/W1hInternal. Only to be used through TI provided API.
7-0RESERVEDR0hReserved

9.7.1.80 FSM_ERA_OH Register (Offset = 222Ch) [Reset = 00000001h]

FSM_ERA_OH is shown in Figure 9-88 and described in Table 9-84.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-88 FSM_ERA_OH Register
313029282726252423222120191817161514131211109876543210
RESERVEDERA_OH
R-0hR/W-1h
Table 9-84 FSM_ERA_OH Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0ERA_OHR/W1hInternal. Only to be used through TI provided API.

9.7.1.81 FSM_SAV_PPUL Register (Offset = 2230h) [Reset = 00000000h]

FSM_SAV_PPUL is shown in Figure 9-89 and described in Table 9-85.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-89 FSM_SAV_PPUL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSAV_P_PUL
R-0hR-0h
Table 9-85 FSM_SAV_PPUL Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0SAV_P_PULR0hInternal. Only to be used through TI provided API.

9.7.1.82 FSM_PE_VH Register (Offset = 2234h) [Reset = 00000100h]

FSM_PE_VH is shown in Figure 9-90 and described in Table 9-86.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-90 FSM_PE_VH Register
313029282726252423222120191817161514131211109876543210
RESERVEDPGM_VHRESERVED
R-0hR/W-1hR-0h
Table 9-86 FSM_PE_VH Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8PGM_VHR/W1hInternal. Only to be used through TI provided API.
7-0RESERVEDR0hReserved

9.7.1.83 FSM_PRG_PW Register (Offset = 2240h) [Reset = 00000000h]

FSM_PRG_PW is shown in Figure 9-91 and described in Table 9-87.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-91 FSM_PRG_PW Register
313029282726252423222120191817161514131211109876543210
RESERVEDPROG_PUL_WIDTH
R-0hR/W-0h
Table 9-87 FSM_PRG_PW Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0PROG_PUL_WIDTHR/W0hInternal. Only to be used through TI provided API.

9.7.1.84 FSM_ERA_PW Register (Offset = 2244h) [Reset = 00000000h]

FSM_ERA_PW is shown in Figure 9-92 and described in Table 9-88.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-92 FSM_ERA_PW Register
313029282726252423222120191817161514131211109876543210
FSM_ERA_PW
R/W-0h
Table 9-88 FSM_ERA_PW Register Field Descriptions
BitFieldTypeResetDescription
31-0FSM_ERA_PWR/W0hInternal. Only to be used through TI provided API.

9.7.1.85 FSM_SAV_ERA_PUL Register (Offset = 2254h) [Reset = 00000000h]

FSM_SAV_ERA_PUL is shown in Figure 9-93 and described in Table 9-89.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-93 FSM_SAV_ERA_PUL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSAV_ERA_PUL
R-0hR-0h
Table 9-89 FSM_SAV_ERA_PUL Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hInternal. Only to be used through TI provided API.
11-0SAV_ERA_PULR0hInternal. Only to be used through TI provided API.

9.7.1.86 FSM_TIMER Register (Offset = 2258h) [Reset = 00000000h]

FSM_TIMER is shown in Figure 9-94 and described in Table 9-90.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-94 FSM_TIMER Register
313029282726252423222120191817161514131211109876543210
FSM_TIMER
R-0h
Table 9-90 FSM_TIMER Register Field Descriptions
BitFieldTypeResetDescription
31-0FSM_TIMERR0hInternal. Only to be used through TI provided API.

9.7.1.87 FSM_MODE Register (Offset = 225Ch) [Reset = 00000000h]

FSM_MODE is shown in Figure 9-95 and described in Table 9-91.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-95 FSM_MODE Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRDV_SUBMODEPGM_SUBMODE
R-0hR-0hR-0h
15141312111098
ERA_SUBMODESUBMODESAV_PGM_CMDSAV_ERA_MODE
R-0hR-0hR-0hR-0h
76543210
SAV_ERA_MODEMODECMD
R-0hR-0hR-0h
Table 9-91 FSM_MODE Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-18RDV_SUBMODER0hInternal. Only to be used through TI provided API.
17-16PGM_SUBMODER0hInternal. Only to be used through TI provided API.
15-14ERA_SUBMODER0hInternal. Only to be used through TI provided API.
13-12SUBMODER0hInternal. Only to be used through TI provided API.
11-9SAV_PGM_CMDR0hInternal. Only to be used through TI provided API.
8-6SAV_ERA_MODER0hInternal. Only to be used through TI provided API.
5-3MODER0hInternal. Only to be used through TI provided API.
2-0CMDR0hInternal. Only to be used through TI provided API.

9.7.1.88 FSM_PGM Register (Offset = 2260h) [Reset = 00000000h]

FSM_PGM is shown in Figure 9-96 and described in Table 9-92.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-96 FSM_PGM Register
31302928272625242322212019181716
RESERVEDPGM_BANKPGM_ADDR
R-0hR-0hR-0h
1514131211109876543210
PGM_ADDR
R-0h
Table 9-92 FSM_PGM Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-23PGM_BANKR0hInternal. Only to be used through TI provided API.
22-0PGM_ADDRR0hInternal. Only to be used through TI provided API.

9.7.1.89 FSM_ERA Register (Offset = 2264h) [Reset = 00000000h]

FSM_ERA is shown in Figure 9-97 and described in Table 9-93.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-97 FSM_ERA Register
31302928272625242322212019181716
RESERVEDERA_BANKERA_ADDR
R-0hR-0hR-0h
1514131211109876543210
ERA_ADDR
R-0h
Table 9-93 FSM_ERA Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-23ERA_BANKR0hInternal. Only to be used through TI provided API.
22-0ERA_ADDRR0hInternal. Only to be used through TI provided API.

9.7.1.90 FSM_PRG_PUL Register (Offset = 2268h) [Reset = 00040032h]

FSM_PRG_PUL is shown in Figure 9-98 and described in Table 9-94.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-98 FSM_PRG_PUL Register
31302928272625242322212019181716
RESERVEDBEG_EC_LEVEL
R-0hR/W-4h
1514131211109876543210
RESERVEDMAX_PRG_PUL
R-0hR/W-32h
Table 9-94 FSM_PRG_PUL Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16BEG_EC_LEVELR/W4hInternal. Only to be used through TI provided API.
15-12RESERVEDR0hReserved
11-0MAX_PRG_PULR/W32hInternal. Only to be used through TI provided API.

9.7.1.91 FSM_ERA_PUL Register (Offset = 226Ch) [Reset = 00040BB8h]

FSM_ERA_PUL is shown in Figure 9-99 and described in Table 9-95.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-99 FSM_ERA_PUL Register
31302928272625242322212019181716
RESERVEDMAX_EC_LEVEL
R-0hR/W-4h
1514131211109876543210
RESERVEDMAX_ERA_PUL
R-0hR/W-BB8h
Table 9-95 FSM_ERA_PUL Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16MAX_EC_LEVELR/W4hInternal. Only to be used through TI provided API.
15-12RESERVEDR0hReserved
11-0MAX_ERA_PULR/WBB8hInternal. Only to be used through TI provided API.

9.7.1.92 FSM_STEP_SIZE Register (Offset = 2270h) [Reset = 00000000h]

FSM_STEP_SIZE is shown in Figure 9-100 and described in Table 9-96.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-100 FSM_STEP_SIZE Register
31302928272625242322212019181716
RESERVEDEC_STEP_SIZE
R-0hR/W-0h
1514131211109876543210
RESERVED
R-0h
Table 9-96 FSM_STEP_SIZE Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-16EC_STEP_SIZER/W0hInternal. Only to be used through TI provided API.
15-0RESERVEDR0hReserved

9.7.1.93 FSM_PUL_CNTR Register (Offset = 2274h) [Reset = 00000000h]

FSM_PUL_CNTR is shown in Figure 9-101 and described in Table 9-97.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-101 FSM_PUL_CNTR Register
31302928272625242322212019181716
RESERVEDCUR_EC_LEVEL
R-0hR-0h
1514131211109876543210
RESERVEDPUL_CNTR
R-0hR-0h
Table 9-97 FSM_PUL_CNTR Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-16CUR_EC_LEVELR0hInternal. Only to be used through TI provided API.
15-12RESERVEDR0hReserved
11-0PUL_CNTRR0hInternal. Only to be used through TI provided API.

9.7.1.94 FSM_EC_STEP_HEIGHT Register (Offset = 2278h) [Reset = 00000000h]

FSM_EC_STEP_HEIGHT is shown in Figure 9-102 and described in Table 9-98.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-102 FSM_EC_STEP_HEIGHT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEC_STEP_HEIGHT
R-0hR/W-0h
Table 9-98 FSM_EC_STEP_HEIGHT Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0EC_STEP_HEIGHTR/W0hInternal. Only to be used through TI provided API.

9.7.1.95 FSM_ST_MACHINE Register (Offset = 227Ch) [Reset = 00800500h]

FSM_ST_MACHINE is shown in Figure 9-103 and described in Table 9-99.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-103 FSM_ST_MACHINE Register
3130292827262524
RESERVED
R-0h
2322212019181716
DO_PRECONDFSM_INT_ENALL_BANKSCMPV_ALLOWEDRANDOMRV_SEC_ENRV_RESRV_INT_EN
R/W-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDONE_TIME_GOODRESERVEDDO_REDU_COLDBG_SHORT_ROW
R-0hR/W-0hR-0hR/W-0hR/W-Ah
76543210
DBG_SHORT_ROWRESERVEDPGM_SEC_COF_ENPREC_STOP_ENDIS_TST_ENCMD_ENINV_DATAOVERRIDE
R/W-AhR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-99 FSM_ST_MACHINE Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23DO_PRECONDR/W1hInternal. Only to be used through TI provided API.
22FSM_INT_ENR/W0hInternal. Only to be used through TI provided API.
21ALL_BANKSR/W0hInternal. Only to be used through TI provided API.
20CMPV_ALLOWEDR/W0hInternal. Only to be used through TI provided API.
19RANDOMR/W0hInternal. Only to be used through TI provided API.
18RV_SEC_ENR/W0hInternal. Only to be used through TI provided API.
17RV_RESR/W0hInternal. Only to be used through TI provided API.
16RV_INT_ENR/W0hInternal. Only to be used through TI provided API.
15RESERVEDR0hReserved
14ONE_TIME_GOODR/W0hInternal. Only to be used through TI provided API.
13-12RESERVEDR0hReserved
11DO_REDU_COLR/W0hInternal. Only to be used through TI provided API.
10-7DBG_SHORT_ROWR/WAhInternal. Only to be used through TI provided API.
6RESERVEDR0hReserved
5PGM_SEC_COF_ENR/W0hInternal. Only to be used through TI provided API.
4PREC_STOP_ENR/W0hInternal. Only to be used through TI provided API.
3DIS_TST_ENR/W0hInternal. Only to be used through TI provided API.
2CMD_ENR/W0hInternal. Only to be used through TI provided API.
1INV_DATAR/W0hInternal. Only to be used through TI provided API.
0OVERRIDER/W0hInternal. Only to be used through TI provided API.

9.7.1.96 FSM_FLES Register (Offset = 2280h) [Reset = 00000000h]

FSM_FLES is shown in Figure 9-104 and described in Table 9-100.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-104 FSM_FLES Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDBLK_TIOTPBLK_OTP
R-0hR/W-0hR/W-0h
Table 9-100 FSM_FLES Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-8BLK_TIOTPR/W0hInternal. Only to be used through TI provided API.
7-0BLK_OTPR/W0hInternal. Only to be used through TI provided API.

9.7.1.97 FSM_WR_ENA Register (Offset = 2288h) [Reset = 00000002h]

FSM_WR_ENA is shown in Figure 9-105 and described in Table 9-101.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-105 FSM_WR_ENA Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDWR_ENA
R-0hR/W-2h
Table 9-101 FSM_WR_ENA Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0WR_ENAR/W2hInternal. Only to be used through TI provided API.

9.7.1.98 FSM_ACC_PP Register (Offset = 228Ch) [Reset = 00000000h]

FSM_ACC_PP is shown in Figure 9-106 and described in Table 9-102.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-106 FSM_ACC_PP Register
313029282726252423222120191817161514131211109876543210
FSM_ACC_PP
R-0h
Table 9-102 FSM_ACC_PP Register Field Descriptions
BitFieldTypeResetDescription
31-0FSM_ACC_PPR0hInternal. Only to be used through TI provided API.

9.7.1.99 FSM_ACC_EP Register (Offset = 2290h) [Reset = 00000000h]

FSM_ACC_EP is shown in Figure 9-107 and described in Table 9-103.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-107 FSM_ACC_EP Register
313029282726252423222120191817161514131211109876543210
RESERVEDACC_EP
R-0hR-0h
Table 9-103 FSM_ACC_EP Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0ACC_EPR0hInternal. Only to be used through TI provided API.

9.7.1.100 FSM_ADDR Register (Offset = 22A0h) [Reset = 00000000h]

FSM_ADDR is shown in Figure 9-108 and described in Table 9-104.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-108 FSM_ADDR Register
3130292827262524
RESERVEDBANKCUR_ADDR
R-0hR-0hR-0h
2322212019181716
CUR_ADDR
R-0h
15141312111098
CUR_ADDR
R-0h
76543210
CUR_ADDR
R-0h
Table 9-104 FSM_ADDR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30-28BANKR0hInternal. Only to be used through TI provided API.
27-0CUR_ADDRR0hInternal. Only to be used through TI provided API.

9.7.1.101 FSM_SECTOR Register (Offset = 22A4h) [Reset = FFFF0000h]

FSM_SECTOR is shown in Figure 9-109 and described in Table 9-105.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-109 FSM_SECTOR Register
31302928272625242322212019181716
SECT_ERASED
R/W-FFFFh
1514131211109876543210
FSM_SECTOR_EXTENSIONSECTORSEC_OUT
R-0hR-0hR-0h
Table 9-105 FSM_SECTOR Register Field Descriptions
BitFieldTypeResetDescription
31-16SECT_ERASEDR/WFFFFhInternal. Only to be used through TI provided API.
15-8FSM_SECTOR_EXTENSIONR0hInternal. Only to be used through TI provided API.
7-4SECTORR0hInternal. Only to be used through TI provided API.
3-0SEC_OUTR0hInternal. Only to be used through TI provided API.

9.7.1.102 FMC_REV_ID Register (Offset = 22A8h) [Reset = 00000000h]

FMC_REV_ID is shown in Figure 9-110 and described in Table 9-106.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-110 FMC_REV_ID Register
313029282726252423222120191817161514131211109876543210
MOD_VERSIONCONFIG_CRC
R-XR-X
Table 9-106 FMC_REV_ID Register Field Descriptions
BitFieldTypeResetDescription
31-12MOD_VERSIONRXInternal. Only to be used through TI provided API.
11-0CONFIG_CRCRXInternal. Only to be used through TI provided API.

9.7.1.103 FSM_ERR_ADDR Register (Offset = 22ACh) [Reset = 00000000h]

FSM_ERR_ADDR is shown in Figure 9-111 and described in Table 9-107.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-111 FSM_ERR_ADDR Register
31302928272625242322212019181716
FSM_ERR_ADDR
R-0h
1514131211109876543210
FSM_ERR_ADDRRESERVEDFSM_ERR_BANK
R-0hR-0hR-0h
Table 9-107 FSM_ERR_ADDR Register Field Descriptions
BitFieldTypeResetDescription
31-8FSM_ERR_ADDRR0hInternal. Only to be used through TI provided API.
7-4RESERVEDR0hReserved
3-0FSM_ERR_BANKR0hInternal. Only to be used through TI provided API.

9.7.1.104 FSM_PGM_MAXPUL Register (Offset = 22B0h) [Reset = 00000000h]

FSM_PGM_MAXPUL is shown in Figure 9-112 and described in Table 9-108.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-112 FSM_PGM_MAXPUL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDFSM_PGM_MAXPUL
R-0hR-0h
Table 9-108 FSM_PGM_MAXPUL Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0FSM_PGM_MAXPULR0hInternal. Only to be used through TI provided API.

9.7.1.105 FSM_EXECUTE Register (Offset = 22B4h) [Reset = 000A000Ah]

FSM_EXECUTE is shown in Figure 9-113 and described in Table 9-109.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-113 FSM_EXECUTE Register
31302928272625242322212019181716
RESERVEDSUSPEND_NOW
R-0hR/W-Ah
1514131211109876543210
RESERVEDFSMEXECUTE
R-0hR/W-Ah
Table 9-109 FSM_EXECUTE Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16SUSPEND_NOWR/WAhInternal. Only to be used through TI provided API.
15-5RESERVEDR0hReserved
4-0FSMEXECUTER/WAhInternal. Only to be used through TI provided API.

9.7.1.106 FSM_SECTOR1 Register (Offset = 22C0h) [Reset = FFFFFFFFh]

FSM_SECTOR1 is shown in Figure 9-114 and described in Table 9-110.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-114 FSM_SECTOR1 Register
313029282726252423222120191817161514131211109876543210
FSM_SECTOR1
R/W-FFFFFFFFh
Table 9-110 FSM_SECTOR1 Register Field Descriptions
BitFieldTypeResetDescription
31-0FSM_SECTOR1R/WFFFFFFFFhInternal. Only to be used through TI provided API.

9.7.1.107 FSM_SECTOR2 Register (Offset = 22C4h) [Reset = 00000FFFh]

FSM_SECTOR2 is shown in Figure 9-115 and described in Table 9-111.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-115 FSM_SECTOR2 Register
313029282726252423222120191817161514131211109876543210
FSM_SECTOR2
R/W-FFFh
Table 9-111 FSM_SECTOR2 Register Field Descriptions
BitFieldTypeResetDescription
31-0FSM_SECTOR2R/WFFFhInternal. Only to be used through TI provided API.

9.7.1.108 FSM_BSLE0 Register (Offset = 22E0h) [Reset = 00000000h]

FSM_BSLE0 is shown in Figure 9-116 and described in Table 9-112.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-116 FSM_BSLE0 Register
313029282726252423222120191817161514131211109876543210
FSM_BSLE0
R/W-0h
Table 9-112 FSM_BSLE0 Register Field Descriptions
BitFieldTypeResetDescription
31-0FSM_BSLE0R/W0hInternal. Only to be used through TI provided API.

9.7.1.109 FSM_BSLE1 Register (Offset = 22E4h) [Reset = 00000000h]

FSM_BSLE1 is shown in Figure 9-117 and described in Table 9-113.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-117 FSM_BSLE1 Register
313029282726252423222120191817161514131211109876543210
FSM_BSL1
R/W-0h
Table 9-113 FSM_BSLE1 Register Field Descriptions
BitFieldTypeResetDescription
31-0FSM_BSL1R/W0hInternal. Only to be used through TI provided API.

9.7.1.110 FSM_BSLP0 Register (Offset = 22F0h) [Reset = 00000000h]

FSM_BSLP0 is shown in Figure 9-118 and described in Table 9-114.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-118 FSM_BSLP0 Register
313029282726252423222120191817161514131211109876543210
FSM_BSLP0
R/W-0h
Table 9-114 FSM_BSLP0 Register Field Descriptions
BitFieldTypeResetDescription
31-0FSM_BSLP0R/W0hInternal. Only to be used through TI provided API.

9.7.1.111 FSM_BSLP1 Register (Offset = 22F4h) [Reset = 00000000h]

FSM_BSLP1 is shown in Figure 9-119 and described in Table 9-115.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-119 FSM_BSLP1 Register
313029282726252423222120191817161514131211109876543210
FSM_BSL1
R/W-0h
Table 9-115 FSM_BSLP1 Register Field Descriptions
BitFieldTypeResetDescription
31-0FSM_BSL1R/W0hInternal. Only to be used through TI provided API.

9.7.1.112 FSM_PGM128 Register (Offset = 22F8h) [Reset = 00000000h]

FSM_PGM128 is shown in Figure 9-120 and described in Table 9-116.

Return to the Summary Table.

FMC FSM Enable 128-bit Wide Programming

Figure 9-120 FSM_PGM128 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEN_PGM128
R-0hR/W-0h
Table 9-116 FSM_PGM128 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0EN_PGM128R/W0h1: Enables 128-bit wide programming. This mode requires programming supply voltage to be greater than 2.5v at the Flash Pump. The primary use case for this mode is manufacturing test for test time reduction.
0: 64-bit wide programming. Valid at any programming voltage. A 128-bit word is divided into two 64-bit words for programming. [default]
This register is write protected with the FSM_WR_ENA register.

9.7.1.113 FCFG_BANK Register (Offset = 2400h) [Reset = 00000801h]

FCFG_BANK is shown in Figure 9-121 and described in Table 9-117.

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Internal. Only to be used through TI provided API.

Figure 9-121 FCFG_BANK Register
3130292827262524
EE_BANK_WIDTH
R-0h
2322212019181716
EE_BANK_WIDTHEE_NUM_BANK
R-0hR-0h
15141312111098
MAIN_BANK_WIDTH
R-80h
76543210
MAIN_BANK_WIDTHMAIN_NUM_BANK
R-80hR-1h
Table 9-117 FCFG_BANK Register Field Descriptions
BitFieldTypeResetDescription
31-20EE_BANK_WIDTHR0hInternal. Only to be used through TI provided API.
19-16EE_NUM_BANKR0hInternal. Only to be used through TI provided API.
15-4MAIN_BANK_WIDTHR80hInternal. Only to be used through TI provided API.
3-0MAIN_NUM_BANKR1hInternal. Only to be used through TI provided API.

9.7.1.114 FCFG_WRAPPER Register (Offset = 2404h) [Reset = 50009007h]

FCFG_WRAPPER is shown in Figure 9-122 and described in Table 9-118.

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Internal. Only to be used through TI provided API.

Figure 9-122 FCFG_WRAPPER Register
3130292827262524
FAMILY_TYPE
R-50h
2322212019181716
RESERVEDMEM_MAPCPU2
R-0hR-0hR-0h
15141312111098
EE_IN_MAINROMIFLUSHSIL3ECCA
R-9hR-0hR-0hR-0hR-0h
76543210
AUTO_SUSPUERRCPU_TYPE1
R-0hR-0hR-7h
Table 9-118 FCFG_WRAPPER Register Field Descriptions
BitFieldTypeResetDescription
31-24FAMILY_TYPER50hInternal. Only to be used through TI provided API.
23-21RESERVEDR0hReserved
20MEM_MAPR0hInternal. Only to be used through TI provided API.
19-16CPU2R0hInternal. Only to be used through TI provided API.
15-12EE_IN_MAINR9hInternal. Only to be used through TI provided API.
11ROMR0hInternal. Only to be used through TI provided API.
10IFLUSHR0hInternal. Only to be used through TI provided API.
9SIL3R0hInternal. Only to be used through TI provided API.
8ECCAR0hInternal. Only to be used through TI provided API.
7-6AUTO_SUSPR0hInternal. Only to be used through TI provided API.
5-4UERRR0hInternal. Only to be used through TI provided API.
3-0CPU_TYPE1R7hInternal. Only to be used through TI provided API.

9.7.1.115 FCFG_BNK_TYPE Register (Offset = 2408h) [Reset = 00000004h]

FCFG_BNK_TYPE is shown in Figure 9-123 and described in Table 9-119.

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Internal. Only to be used through TI provided API.

Figure 9-123 FCFG_BNK_TYPE Register
31302928272625242322212019181716
B7_TYPEB6_TYPEB5_TYPEB4_TYPE
R-0hR-0hR-0hR-0h
1514131211109876543210
B3_TYPEB2_TYPEB1_TYPEB0_TYPE
R-0hR-0hR-0hR-4h
Table 9-119 FCFG_BNK_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31-28B7_TYPER0hInternal. Only to be used through TI provided API.
27-24B6_TYPER0hInternal. Only to be used through TI provided API.
23-20B5_TYPER0hInternal. Only to be used through TI provided API.
19-16B4_TYPER0hInternal. Only to be used through TI provided API.
15-12B3_TYPER0hInternal. Only to be used through TI provided API.
11-8B2_TYPER0hInternal. Only to be used through TI provided API.
7-4B1_TYPER0hInternal. Only to be used through TI provided API.
3-0B0_TYPER4hInternal. Only to be used through TI provided API.

9.7.1.116 FCFG_B0_START Register (Offset = 2410h) [Reset = 02000000h]

FCFG_B0_START is shown in Figure 9-124 and described in Table 9-120.

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Internal. Only to be used through TI provided API.

Figure 9-124 FCFG_B0_START Register
3130292827262524
B0_MAX_SECTORB0_MUX_FACTOR
R-0hR-2h
2322212019181716
B0_START_ADDR
R-0h
15141312111098
B0_START_ADDR
R-0h
76543210
B0_START_ADDR
R-0h
Table 9-120 FCFG_B0_START Register Field Descriptions
BitFieldTypeResetDescription
31-28B0_MAX_SECTORR0hInternal. Only to be used through TI provided API.
27-24B0_MUX_FACTORR2hInternal. Only to be used through TI provided API.
23-0B0_START_ADDRR0hInternal. Only to be used through TI provided API.

9.7.1.117 FCFG_B1_START Register (Offset = 2414h) [Reset = 00000000h]

FCFG_B1_START is shown in Figure 9-125 and described in Table 9-121.

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Internal. Only to be used through TI provided API.

Figure 9-125 FCFG_B1_START Register
3130292827262524
B1_MAX_SECTORB1_MUX_FACTOR
R-0hR-0h
2322212019181716
B1_START_ADDR
R-0h
15141312111098
B1_START_ADDR
R-0h
76543210
B1_START_ADDR
R-0h
Table 9-121 FCFG_B1_START Register Field Descriptions
BitFieldTypeResetDescription
31-28B1_MAX_SECTORR0hInternal. Only to be used through TI provided API.
27-24B1_MUX_FACTORR0hInternal. Only to be used through TI provided API.
23-0B1_START_ADDRR0hInternal. Only to be used through TI provided API.

9.7.1.118 FCFG_B2_START Register (Offset = 2418h) [Reset = 00000000h]

FCFG_B2_START is shown in Figure 9-126 and described in Table 9-122.

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Internal. Only to be used through TI provided API.

Figure 9-126 FCFG_B2_START Register
3130292827262524
B2_MAX_SECTORB2_MUX_FACTOR
R-0hR-0h
2322212019181716
B2_START_ADDR
R-0h
15141312111098
B2_START_ADDR
R-0h
76543210
B2_START_ADDR
R-0h
Table 9-122 FCFG_B2_START Register Field Descriptions
BitFieldTypeResetDescription
31-28B2_MAX_SECTORR0hInternal. Only to be used through TI provided API.
27-24B2_MUX_FACTORR0hInternal. Only to be used through TI provided API.
23-0B2_START_ADDRR0hInternal. Only to be used through TI provided API.

9.7.1.119 FCFG_B3_START Register (Offset = 241Ch) [Reset = 00000000h]

FCFG_B3_START is shown in Figure 9-127 and described in Table 9-123.

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Internal. Only to be used through TI provided API.

Figure 9-127 FCFG_B3_START Register
3130292827262524
B3_MAX_SECTORB3_MUX_FACTOR
R-0hR-0h
2322212019181716
B3_START_ADDR
R-0h
15141312111098
B3_START_ADDR
R-0h
76543210
B3_START_ADDR
R-0h
Table 9-123 FCFG_B3_START Register Field Descriptions
BitFieldTypeResetDescription
31-28B3_MAX_SECTORR0hInternal. Only to be used through TI provided API.
27-24B3_MUX_FACTORR0hInternal. Only to be used through TI provided API.
23-0B3_START_ADDRR0hInternal. Only to be used through TI provided API.

9.7.1.120 FCFG_B4_START Register (Offset = 2420h) [Reset = 00000000h]

FCFG_B4_START is shown in Figure 9-128 and described in Table 9-124.

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Internal. Only to be used through TI provided API.

Figure 9-128 FCFG_B4_START Register
3130292827262524
B4_MAX_SECTORB4_MUX_FACTOR
R-0hR-0h
2322212019181716
B4_START_ADDR
R-0h
15141312111098
B4_START_ADDR
R-0h
76543210
B4_START_ADDR
R-0h
Table 9-124 FCFG_B4_START Register Field Descriptions
BitFieldTypeResetDescription
31-28B4_MAX_SECTORR0hInternal. Only to be used through TI provided API.
27-24B4_MUX_FACTORR0hInternal. Only to be used through TI provided API.
23-0B4_START_ADDRR0hInternal. Only to be used through TI provided API.

9.7.1.121 FCFG_B5_START Register (Offset = 2424h) [Reset = 00000000h]

FCFG_B5_START is shown in Figure 9-129 and described in Table 9-125.

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Internal. Only to be used through TI provided API.

Figure 9-129 FCFG_B5_START Register
3130292827262524
B5_MAX_SECTORB5_MUX_FACTOR
R-0hR-0h
2322212019181716
B5_START_ADDR
R-0h
15141312111098
B5_START_ADDR
R-0h
76543210
B5_START_ADDR
R-0h
Table 9-125 FCFG_B5_START Register Field Descriptions
BitFieldTypeResetDescription
31-28B5_MAX_SECTORR0hInternal. Only to be used through TI provided API.
27-24B5_MUX_FACTORR0hInternal. Only to be used through TI provided API.
23-0B5_START_ADDRR0hInternal. Only to be used through TI provided API.

9.7.1.122 FCFG_B6_START Register (Offset = 2428h) [Reset = 00000000h]

FCFG_B6_START is shown in Figure 9-130 and described in Table 9-126.

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Internal. Only to be used through TI provided API.

Figure 9-130 FCFG_B6_START Register
3130292827262524
B6_MAX_SECTORB6_MUX_FACTOR
R-0hR-0h
2322212019181716
B6_START_ADDR
R-0h
15141312111098
B6_START_ADDR
R-0h
76543210
B6_START_ADDR
R-0h
Table 9-126 FCFG_B6_START Register Field Descriptions
BitFieldTypeResetDescription
31-28B6_MAX_SECTORR0hInternal. Only to be used through TI provided API.
27-24B6_MUX_FACTORR0hInternal. Only to be used through TI provided API.
23-0B6_START_ADDRR0hInternal. Only to be used through TI provided API.

9.7.1.123 FCFG_B7_START Register (Offset = 242Ch) [Reset = 00000000h]

FCFG_B7_START is shown in Figure 9-131 and described in Table 9-127.

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Internal. Only to be used through TI provided API.

Figure 9-131 FCFG_B7_START Register
3130292827262524
B7_MAX_SECTORB7_MUX_FACTOR
R-0hR-0h
2322212019181716
B7_START_ADDR
R-0h
15141312111098
B7_START_ADDR
R-0h
76543210
B7_START_ADDR
R-0h
Table 9-127 FCFG_B7_START Register Field Descriptions
BitFieldTypeResetDescription
31-28B7_MAX_SECTORR0hInternal. Only to be used through TI provided API.
27-24B7_MUX_FACTORR0hInternal. Only to be used through TI provided API.
23-0B7_START_ADDRR0hInternal. Only to be used through TI provided API.

9.7.1.124 FCFG_B0_SSIZE0 Register (Offset = 2430h) [Reset = 002C0008h]

FCFG_B0_SSIZE0 is shown in Figure 9-132 and described in Table 9-128.

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Internal. Only to be used through TI provided API.

Figure 9-132 FCFG_B0_SSIZE0 Register
31302928272625242322212019181716
RESERVEDB0_NUM_SECTORS
R-0hR-2Ch
1514131211109876543210
RESERVEDB0_SECT_SIZE
R-0hR-8h
Table 9-128 FCFG_B0_SSIZE0 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27-16B0_NUM_SECTORSR2ChInternal. Only to be used through TI provided API.
15-4RESERVEDR0hReserved
3-0B0_SECT_SIZER8hInternal. Only to be used through TI provided API.