SWCU185F january   2018  – march 2023 CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5. 1.1 Trademarks
  2. 2 Architectural Overview
    1. 2.1 Target Applications
    2. 2.2 Overview
    3. 2.3 Functional Overview
      1. 2.3.1  Arm® Cortex®-M4F
        1. 2.3.1.1 Processor Core
        2. 2.3.1.2 System Timer (SysTick)
        3. 2.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 2.3.1.4 System Control Block
      2. 2.3.2  On-Chip Memory
        1. 2.3.2.1 SRAM
        2. 2.3.2.2 Flash Memory
        3. 2.3.2.3 ROM
      3. 2.3.3  Radio
      4. 2.3.4  Security Core
      5. 2.3.5  General-Purpose Timers
        1. 2.3.5.1 Watchdog Timer
        2. 2.3.5.2 Always-On Domain
      6. 2.3.6  Direct Memory Access
      7. 2.3.7  System Control and Clock
      8. 2.3.8  Serial Communication Peripherals
        1. 2.3.8.1 UART
        2. 2.3.8.2 I2C
        3. 2.3.8.3 I2S
        4. 2.3.8.4 SSI
      9. 2.3.9  Programmable I/Os
      10. 2.3.10 Sensor Controller
      11. 2.3.11 Random Number Generator
      12. 2.3.12 cJTAG and JTAG
      13. 2.3.13 Power Supply System
        1. 2.3.13.1 Supply System
          1. 2.3.13.1.1 VDDS
          2. 2.3.13.1.2 VDDR
          3. 2.3.13.1.3 Digital Core Supply
          4. 2.3.13.1.4 Other Internal Supplies
        2. 2.3.13.2 DC/DC Converter
  3. 3 Arm® Cortex®-M4F Processor
    1. 3.1 Arm® Cortex®-M4F Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 Overview
      1. 3.3.1 System-Level Interface
      2. 3.3.2 Integrated Configurable Debug
      3. 3.3.3 Trace Port Interface Unit
      4. 3.3.4 Floating Point Unit (FPU)
      5. 3.3.5 Memory Protection Unit (MPU)
      6. 3.3.6 Arm® Cortex®-M4F System Component Details
    4. 3.4 Programming Model
      1. 3.4.1 Processor Mode and Privilege Levels for Software Execution
      2. 3.4.2 Stacks
      3. 3.4.3 Exceptions and Interrupts
      4. 3.4.4 Data Types
    5. 3.5 Arm® Cortex®-M4F Core Registers
      1. 3.5.1 Core Register Map
      2. 3.5.2 Core Register Descriptions
        1. 3.5.2.1  Cortex®General-Purpose Register 0 (R0)
        2. 3.5.2.2  Cortex® General-Purpose Register 1 (R1)
        3. 3.5.2.3  Cortex® General-Purpose Register 2 (R2)
        4. 3.5.2.4  Cortex® General-Purpose Register 3 (R3)
        5. 3.5.2.5  Cortex® General-Purpose Register 4 (R4)
        6. 3.5.2.6  Cortex® General-Purpose Register 5 (R5)
        7. 3.5.2.7  Cortex® General-Purpose Register 6 (R6)
        8. 3.5.2.8  Cortex® General-Purpose Register 7 (R7)
        9. 3.5.2.9  Cortex® General-Purpose Register 8 (R8)
        10. 3.5.2.10 Cortex® General-Purpose Register 9 (R9)
        11. 3.5.2.11 Cortex® General-Purpose Register 10 (R10)
        12. 3.5.2.12 Cortex® General-Purpose Register 11 (R11)
        13. 3.5.2.13 Cortex® General-Purpose Register 12 (R12)
        14. 3.5.2.14 Stack Pointer (SP)
        15. 3.5.2.15 Link Register (LR)
        16. 3.5.2.16 Program Counter (PC)
        17. 3.5.2.17 Program Status Register (PSR)
        18. 3.5.2.18 Priority Mask Register (PRIMASK)
        19. 3.5.2.19 Fault Mask Register (FAULTMASK)
        20. 3.5.2.20 Base Priority Mask Register (BASEPRI)
        21. 3.5.2.21 Control Register (CONTROL)
    6. 3.6 Instruction Set Summary
      1. 3.6.1 Arm® Cortex®-M4F Instructions
      2. 3.6.2 Load and Store Timings
      3. 3.6.3 Binary Compatibility With Other Cortex® Processors
    7. 3.7 Floating Point Unit (FPU)
      1. 3.7.1 About the FPU
      2. 3.7.2 FPU Functional Description
        1. 3.7.2.1 FPU Views of the Register Bank
        2. 3.7.2.2 Modes of Operation
          1. 3.7.2.2.1 Full-Compliance Mode
          2. 3.7.2.2.2 Flush-to-Zero Mode
          3. 3.7.2.2.3 Default NaN Mode
        3. 3.7.2.3 FPU Instruction Set
        4. 3.7.2.4 Compliance With the IEEE 754 Standard
        5. 3.7.2.5 Complete Implementation of the IEEE 754 Standard
        6. 3.7.2.6 IEEE 754 Standard Implementation Choices
          1. 3.7.2.6.1 NaN Handling
          2. 3.7.2.6.2 Comparisons
          3. 3.7.2.6.3 Underflow
        7. 3.7.2.7 Exceptions
      3. 3.7.3 FPU Programmers Model
        1. 3.7.3.1 Enabling the FPU
          1. 3.7.3.1.1 Enabling the FPU
    8. 3.8 Memory Protection Unit (MPU)
      1. 3.8.1 About the MPU
      2. 3.8.2 MPU Functional Description
      3. 3.8.3 MPU Programmers Model
    9. 3.9 Arm® Cortex®-M4F Processor Registers
      1. 3.9.1 CPU_DWT Registers
      2. 3.9.2 CPU_FPB Registers
      3. 3.9.3 CPU_ITM Registers
      4. 3.9.4 CPU_SCS Registers
      5. 3.9.5 CPU_TPIU Registers
  4. 4 Memory Map
    1. 4.1 Memory Map
  5. 5 Arm® Cortex®-M4F Peripherals
    1. 5.1 Arm® Cortex®-M4F Peripherals Introduction
    2. 5.2 Functional Description
      1. 5.2.1 SysTick
      2. 5.2.2 NVIC
        1. 5.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 5.2.2.2 Hardware and Software Control of Interrupts
      3. 5.2.3 SCB
      4. 5.2.4 ITM
      5. 5.2.5 FPB
      6. 5.2.6 TPIU
      7. 5.2.7 DWT
  6. 6 Interrupts and Events
    1. 6.1 Exception Model
      1. 6.1.1 Exception States
      2. 6.1.2 Exception Types
      3. 6.1.3 Exception Handlers
      4. 6.1.4 Vector Table
      5. 6.1.5 Exception Priorities
      6. 6.1.6 Interrupt Priority Grouping
      7. 6.1.7 Exception Entry and Return
        1. 6.1.7.1 Exception Entry
        2. 6.1.7.2 Exception Return
    2. 6.2 Fault Handling
      1. 6.2.1 Fault Types
      2. 6.2.2 Fault Escalation and Hard Faults
      3. 6.2.3 Fault Status Registers and Fault Address Registers
      4. 6.2.4 Lockup
    3. 6.3 Event Fabric
      1. 6.3.1 Introduction
      2. 6.3.2 Event Fabric Overview
        1. 6.3.2.1 Registers
    4. 6.4 AON Event Fabric
      1. 6.4.1 Common Input Event List
      2. 6.4.2 Event Subscribers
        1. 6.4.2.1 Wake-Up Controller (WUC)
        2. 6.4.2.2 Real-Time Clock
        3. 6.4.2.3 MCU Event Fabric
    5. 6.5 MCU Event Fabric
      1. 6.5.1 Common Input Event List
      2. 6.5.2 Event Subscribers
        1. 6.5.2.1 System CPU
        2. 6.5.2.2 NMI
        3. 6.5.2.3 Freeze
    6. 6.6 AON Events
    7. 6.7 Interrupts and Events Registers
      1. 6.7.1 AON_EVENT Registers
      2. 6.7.2 EVENT Registers
  7. 7 JTAG Interface
    1. 7.1  Top-Level Debug System
    2. 7.2  cJTAG
      1. 7.2.1 cJTAG Commands
        1. 7.2.1.1 Mandatory Commands
      2. 7.2.2 Programming Sequences
        1. 7.2.2.1 Opening Command Window
        2. 7.2.2.2 Changing to 4-Pin Mode
        3. 7.2.2.3 Close Command Window
    3. 7.3  ICEPick
      1. 7.3.1 Secondary TAPs
        1. 7.3.1.1 Slave DAP (CPU DAP)
        2. 7.3.1.2 Ordering Slave TAPs and DAPs
      2. 7.3.2 ICEPick Registers
        1. 7.3.2.1 IR Instructions
        2. 7.3.2.2 Data Shift Register
        3. 7.3.2.3 Instruction Register
        4. 7.3.2.4 Bypass Register
        5. 7.3.2.5 Device Identification Register
        6. 7.3.2.6 User Code Register
        7. 7.3.2.7 ICEPick Identification Register
        8. 7.3.2.8 Connect Register
      3. 7.3.3 Router Scan Chain
      4. 7.3.4 TAP Routing Registers
        1. 7.3.4.1 ICEPick Control Block
          1. 7.3.4.1.1 All0s Register
          2. 7.3.4.1.2 ICEPick Control Register
          3. 7.3.4.1.3 Linking Mode Register
        2. 7.3.4.2 Test TAP Linking Block
          1. 7.3.4.2.1 Secondary Test TAP Register
        3. 7.3.4.3 Debug TAP Linking Block
          1. 7.3.4.3.1 Secondary Debug TAP Register
    4. 7.4  ICEMelter
    5. 7.5  Serial Wire Viewer (SWV)
    6. 7.6  Halt In Boot (HIB)
    7. 7.7  Debug and Shutdown
    8. 7.8  Debug Features Supported Through WUC TAP
    9. 7.9  Profiler Register
    10. 7.10 Boundary Scan
  8. 8 Power, Reset, and Clock Management (PRCM)
    1. 8.1 Introduction
    2. 8.2 System CPU Mode
    3. 8.3 Supply System
      1. 8.3.1 Internal DC/DC Converter and Global LDO
    4. 8.4 Digital Power Partitioning
      1. 8.4.1 MCU_VD
        1. 8.4.1.1 MCU_VD Power Domains
      2. 8.4.2 AON_VD
        1. 8.4.2.1 AON_VD Power Domains
    5. 8.5 Clock Management
      1. 8.5.1 System Clocks
        1. 8.5.1.1 Controlling the Oscillators
      2. 8.5.2 Clocks in MCU_VD
        1. 8.5.2.1 Clock Gating
        2. 8.5.2.2 Scaler to GPTs
        3. 8.5.2.3 Scaler to WDT
      3. 8.5.3 Clocks in AON_VD
    6. 8.6 Power Modes
      1. 8.6.1 Start-Up State
      2. 8.6.2 Active Mode
      3. 8.6.3 Idle Mode
      4. 8.6.4 Standby Mode
      5. 8.6.5 Shutdown Mode
    7. 8.7 Reset
      1. 8.7.1 System Resets
        1. 8.7.1.1 Clock Loss Detection
        2. 8.7.1.2 Software-Initiated System Reset
        3. 8.7.1.3 Warm Reset Converted to System Reset
      2. 8.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 8.7.3 Reset of AON_VD
    8. 8.8 PRCM Registers
      1. 8.8.1 DDI_0_OSC Registers
      2. 8.8.2 PRCM Registers
      3. 8.8.3 AON_PMCTL Registers
  9. 9 Versatile Instruction Memory System (VIMS)
    1. 9.1 Introduction
    2. 9.2 VIMS Configurations
      1. 9.2.1 VIMS Modes
        1. 9.2.1.1 GPRAM Mode
        2. 9.2.1.2 Off Mode
        3. 9.2.1.3 Cache Mode
      2. 9.2.2 VIMS FLASH Line Buffers
      3. 9.2.3 VIMS Arbitration
      4. 9.2.4 VIMS Cache TAG Prefetch
    3. 9.3 VIMS Software Remarks
      1. 9.3.1 FLASH Program or Update
      2. 9.3.2 VIMS Retention
        1. 9.3.2.1 Mode 1
        2. 9.3.2.2 Mode 2
        3. 9.3.2.3 Mode 3
    4. 9.4 ROM
    5. 9.5 FLASH
      1. 9.5.1 FLASH Memory Protection
      2. 9.5.2 Memory Programming
      3. 9.5.3 FLASH Memory Programming
      4. 9.5.4 Power Management Requirements
    6. 9.6 ROM Functions
    7. 9.7 VIMS Registers
      1. 9.7.1 FLASH Registers
      2. 9.7.2 VIMS Registers
  10. 10SRAM
    1. 10.1 Introduction
    2. 10.2 Main Features
    3. 10.3 Data Retention
    4. 10.4 Parity and SRAM Error Support
    5. 10.5 SRAM Auto-Initialization
    6. 10.6 Parity Debug Behavior
    7. 10.7 SRAM Registers
      1. 10.7.1 SRAM_MMR Registers
      2. 10.7.2 SRAM Registers
  11. 11Bootloader
    1. 11.1 Bootloader Functionality
      1. 11.1.1 Bootloader Disabling
      2. 11.1.2 Bootloader Backdoor
    2. 11.2 Bootloader Interfaces
      1. 11.2.1 Packet Handling
        1. 11.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 11.2.2 Transport Layer
        1. 11.2.2.1 UART Transport
          1. 11.2.2.1.1 UART Baud Rate Automatic Detection
        2. 11.2.2.2 SSI Transport
      3. 11.2.3 Serial Bus Commands
        1. 11.2.3.1  COMMAND_PING
        2. 11.2.3.2  COMMAND_DOWNLOAD
        3. 11.2.3.3  COMMAND_SEND_DATA
        4. 11.2.3.4  COMMAND_SECTOR_ERASE
        5. 11.2.3.5  COMMAND_GET_STATUS
        6. 11.2.3.6  COMMAND_RESET
        7. 11.2.3.7  COMMAND_GET_CHIP_ID
        8. 11.2.3.8  COMMAND_CRC32
        9. 11.2.3.9  COMMAND_BANK_ERASE
        10. 11.2.3.10 COMMAND_MEMORY_READ
        11. 11.2.3.11 COMMAND_MEMORY_WRITE
        12. 11.2.3.12 COMMAND_SET_CCFG
        13. 11.2.3.13 COMMAND_DOWNLOAD_CRC
  12. 12Device Configuration
    1. 12.1 Customer Configuration (CCFG)
    2. 12.2 CCFG Registers
      1. 12.2.1 CCFG Registers
    3. 12.3 Factory Configuration (FCFG)
    4. 12.4 FCFG Registers
      1. 12.4.1 FCFG1 Registers
  13. 13Cryptography
    1. 13.1 AES and Hash Cryptoprocessor Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Debug Capabilities
      2. 13.2.2 Exception Handling
    3. 13.3 Power Management and Sleep Modes
    4. 13.4 Hardware Description
      1. 13.4.1 AHB Slave Bus
      2. 13.4.2 AHB Master Bus
      3. 13.4.3 Interrupts
    5. 13.5 Module Description
      1. 13.5.1 Introduction
      2. 13.5.2 Module Memory Map
      3. 13.5.3 DMA Controller
        1. 13.5.3.1 Internal Operation
        2. 13.5.3.2 Supported DMA Operations
      4. 13.5.4 Master Control and Select Module
        1. 13.5.4.1 Algorithm Select Register
          1. 13.5.4.1.1 Algorithm Select
        2. 13.5.4.2 Master PROT Enable
          1. 13.5.4.2.1 Master PROT-Privileged Access-Enable
        3. 13.5.4.3 Software Reset
      5. 13.5.5 AES Engine
        1. 13.5.5.1 Second Key Registers (Internal, But Clearable)
        2. 13.5.5.2 AES Initialization Vector (IV) Registers
        3. 13.5.5.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 13.5.5.4 Data Input and Output Registers
        5. 13.5.5.5 TAG Registers
      6. 13.5.6 Key Area Registers
        1. 13.5.6.1 Key Write Area Register
        2. 13.5.6.2 Key Written Area Register
        3. 13.5.6.3 Key Size Register
        4. 13.5.6.4 Key Store Read Area Register
        5. 13.5.6.5 Hash Engine
    6. 13.6 AES Module Performance
      1. 13.6.1 Introduction
      2. 13.6.2 Performance for DMA-Based Operations
    7. 13.7 Programming Guidelines
      1. 13.7.1 One-Time Initialization After a Reset
      2. 13.7.2 DMAC and Master Control
        1. 13.7.2.1 Regular Use
        2. 13.7.2.2 Interrupting DMA Transfers
        3. 13.7.2.3 Interrupts, Hardware, and Software Synchronization
      3. 13.7.3 Hashing
        1. 13.7.3.1 Data Format and Byte Order
        2. 13.7.3.2 Basic Hash With Data From DMA
          1. 13.7.3.2.1 New Hash Session With Digest Read Through Slave
          2. 13.7.3.2.2 New Hash Session With Digest to External Memory
          3. 13.7.3.2.3 Resumed Hash Session
        3. 13.7.3.3 HMAC
          1. 13.7.3.3.1 Secure HMAC
        4. 13.7.3.4 Alternative Basic Hash Where Data Originates From Slave Interface
          1. 13.7.3.4.1 New Hash Session
          2. 13.7.3.4.2 Resumed Hash Session
      4. 13.7.4 Encryption and Decryption
        1. 13.7.4.1 Data Format and Byte Order
        2. 13.7.4.2 Key Store
          1. 13.7.4.2.1 Load Keys From External Memory
        3. 13.7.4.3 Basic AES Modes
          1. 13.7.4.3.1 AES-ECB
          2. 13.7.4.3.2 AES-CBC
          3. 13.7.4.3.3 AES-CTR
          4. 13.7.4.3.4 Programming Sequence With DMA Data
        4. 13.7.4.4 CBC-MAC
          1. 13.7.4.4.1 Programming Sequence for CBC-MAC
        5. 13.7.4.5 AES-CCM
          1. 13.7.4.5.1 Programming Sequence for AES-CCM
        6. 13.7.4.6 AES-GCM
          1. 13.7.4.6.1 Programming Sequence for AES-GCM
      5. 13.7.5 Exceptions Handling
        1. 13.7.5.1 Soft Reset
        2. 13.7.5.2 External Port Errors
        3. 13.7.5.3 Key Store Errors
          1. 13.7.5.3.1 PKA Engine
          2. 13.7.5.3.2 Functional Description
            1. 13.7.5.3.2.1 Module Architecture
          3. 13.7.5.3.3 PKA RAM
            1. 13.7.5.3.3.1 PKCP Operations
            2. 13.7.5.3.3.2 Sequencer Operations
              1. 13.7.5.3.3.2.1 Modular Exponentiation Operations
              2. 13.7.5.3.3.2.2 Modular Inversion Operation
              3. 13.7.5.3.3.2.3 Performance
              4. 13.7.5.3.3.2.4 ECC Operations
              5. 13.7.5.3.3.2.5 Performance
              6. 13.7.5.3.3.2.6 ExpMod Performance
              7. 13.7.5.3.3.2.7 Modular Inversion Performance
              8. 13.7.5.3.3.2.8 ECC Operation Performance
            3. 13.7.5.3.3.3 Sequencer ROM Behavior and Interfaces
            4. 13.7.5.3.3.4 Register Configurations
            5. 13.7.5.3.3.5 Operation Sequence
    8. 13.8 Conventions and Compliances
      1. 13.8.1 Conventions Used in This Manual
        1. 13.8.1.1 Terminology
        2. 13.8.1.2 Formulas and Nomenclature
      2. 13.8.2 Compliance
    9. 13.9 Cryptography Registers
      1. 13.9.1 CRYPTO Registers
  14. 14I/O Controller (IOC)
    1. 14.1  Introduction
    2. 14.2  IOC Overview
    3. 14.3  I/O Mapping and Configuration
      1. 14.3.1 Basic I/O Mapping
      2. 14.3.2 Mapping AUXIOs to DIO Pins
      3. 14.3.3 Control External LNA/PA (Range Extender) With I/Os
      4. 14.3.4 Map the 32 kHz System Clock (LF Clock) to DIO
    4. 14.4  Edge Detection on DIO Pins
      1. 14.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT
    5. 14.5  Unused I/O Pins
    6. 14.6  GPIO
    7. 14.7  I/O Pin Capability
    8. 14.8  Peripheral PORTIDs
    9. 14.9  I/O Pins
      1. 14.9.1 Input/Output Modes
        1. 14.9.1.1 Physical Pin
        2. 14.9.1.2 Pin Configuration
    10. 14.10 IOC Registers
      1. 14.10.1 AON_IOC Registers
      2. 14.10.2 GPIO Registers
      3. 14.10.3 IOC Registers
  15. 15Micro Direct Memory Access (µDMA)
    1. 15.1 μDMA Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
    4. 15.4 Initialization and Configuration
      1. 15.4.1 Module Initialization
      2. 15.4.2 Configuring a Memory-to-Memory Transfer
        1. 15.4.2.1 Configure the Channel Attributes
        2. 15.4.2.2 Configure the Channel Control Structure
        3. 15.4.2.3 Start the Transfer
    5. 15.5 µDMA Registers
      1. 15.5.1 UDMA Registers
  16. 16Timers
    1. 16.1 General-Purpose Timers
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1 GPTM Reset Conditions
      2. 16.3.2 Timer Modes
        1. 16.3.2.1 One-Shot or Periodic Timer Mode
        2. 16.3.2.2 Input Edge-Count Mode
        3. 16.3.2.3 Input Edge-Time Mode
        4. 16.3.2.4 PWM Mode
        5. 16.3.2.5 Wait-for-Trigger Mode
      3. 16.3.3 Synchronizing GPT Blocks
      4. 16.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 16.4 Initialization and Configuration
      1. 16.4.1 One-Shot and Periodic Timer Modes
      2. 16.4.2 Input Edge-Count Mode
      3. 16.4.3 Input Edge-Timing Mode
      4. 16.4.4 PWM Mode
      5. 16.4.5 Producing DMA Trigger Events
    5. 16.5 GPTM Registers
      1. 16.5.1 GPT Registers
  17. 17Real-Time Clock (RTC)
    1. 17.1 Introduction
    2. 17.2 Functional Specifications
      1. 17.2.1 Functional Overview
      2. 17.2.2 Free-Running Counter
      3. 17.2.3 Channels
        1. 17.2.3.1 Capture and Compare
      4. 17.2.4 Events
    3. 17.3 RTC Register Information
      1. 17.3.1 Register Access
      2. 17.3.2 Entering Sleep and Wakeup From Sleep
      3. 17.3.3 AON_RTC:SYNC Register
    4. 17.4 RTC Registers
      1. 17.4.1 AON_RTC Registers
  18. 18Watchdog Timer (WDT)
    1. 18.1 Introduction
    2. 18.2 Functional Description
    3. 18.3 Initialization and Configuration
    4. 18.4 WDT Registers
      1. 18.4.1 WDT Registers
  19. 19True Random Number Generator (TRNG)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 TRNG Software Reset
    4. 19.4 Interrupt Requests
    5. 19.5 TRNG Operation Description
      1. 19.5.1 TRNG Shutdown
      2. 19.5.2 TRNG Alarms
      3. 19.5.3 TRNG Entropy
    6. 19.6 TRNG Low-Level Programing Guide
      1. 19.6.1 Initialization
        1. 19.6.1.1 Interfacing Modules
        2. 19.6.1.2 TRNG Main Sequence
        3. 19.6.1.3 TRNG Operating Modes
          1. 19.6.1.3.1 Polling Mode
          2. 19.6.1.3.2 Interrupt Mode
    7. 19.7 TRNG Registers
      1. 19.7.1 TRNG Registers
  20. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 AIODIO
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 SMPH
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPIM
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
              1. 20.4.7.2.5.1.1 Timer Period and Pulse Width Capture
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.2.1 Center-Aligned PWM Generation by Channel 0
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.3.1 Edge-Aligned PWM Generation by Channel 0
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 COMPA
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 COMPB
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference DAC
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 ISRC
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  21. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 BATMON Registers
      1. 21.3.1 AON_BATMON Registers
  22. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud-rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to DMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
      1. 22.7.1 UART Registers
  23. 23Synchronous Serial Interface (SSI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
        2. 23.4.2.2 Receive FIFO
      3. 23.4.3 Interrupts
      4. 23.4.4 Frame Formats
        1. 23.4.4.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.4.2 Motorola SPI Frame Format
          1. 23.4.4.2.1 SPO Clock Polarity Bit
          2. 23.4.4.2.2 SPH Phase-Control Bit
        3. 23.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
        4. 23.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
        5. 23.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
        6. 23.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
        7. 23.4.4.7 MICROWIRE Frame Format
    5. 23.5 DMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SSI Registers
      1. 23.7.1 SSI Registers
  24. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format With 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
      1. 24.5.1 I2C Registers
  25. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
      1. 25.9.1 I2S Registers
  26. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization With Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond With Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration (Depricated)
          19. 26.3.3.2.19 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          20. 26.3.3.2.20 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® low energy
      1. 26.6.1 Bluetooth® low energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® low energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® low energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Nonconnectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  27. 27Revision History

13.9.1 CRYPTO Registers

Table 13-50 lists the memory-mapped registers for the CRYPTO registers. All register offset addresses not listed in Table 13-50 should be considered as reserved locations and the register contents should not be modified.

Table 13-50 CRYPTO Registers
OffsetAcronymRegister NameSection
0hDMACH0CTLChannel 0 ControlDMACH0CTL Register (Offset = 0h) [Reset = 00000000h]
4hDMACH0EXTADDRChannel 0 External AddressDMACH0EXTADDR Register (Offset = 4h) [Reset = 00000000h]
ChDMACH0LENChannel 0 DMA LengthDMACH0LEN Register (Offset = Ch) [Reset = 00000000h]
18hDMASTATDMAC StatusDMASTAT Register (Offset = 18h) [Reset = 00000000h]
1ChDMASWRESETDMAC Software ResetDMASWRESET Register (Offset = 1Ch) [Reset = 00000000h]
20hDMACH1CTLChannel 1 ControlDMACH1CTL Register (Offset = 20h) [Reset = 00000000h]
24hDMACH1EXTADDRChannel 1 External AddressDMACH1EXTADDR Register (Offset = 24h) [Reset = 00000000h]
2ChDMACH1LENChannel 1 DMA LengthDMACH1LEN Register (Offset = 2Ch) [Reset = 00000000h]
78hDMABUSCFGDMAC Master Run-time ParametersDMABUSCFG Register (Offset = 78h) [Reset = 00002400h]
7ChDMAPORTERRDMAC Port Error Raw StatusDMAPORTERR Register (Offset = 7Ch) [Reset = 00000000h]
FChDMAHWVERDMAC VersionDMAHWVER Register (Offset = FCh) [Reset = 01012ED1h]
400hKEYWRITEAREAKey Store Write AreaKEYWRITEAREA Register (Offset = 400h) [Reset = 00000000h]
404hKEYWRITTENAREAKey Store Written AreaKEYWRITTENAREA Register (Offset = 404h) [Reset = 00000000h]
408hKEYSIZEKey Store SizeKEYSIZE Register (Offset = 408h) [Reset = 00000001h]
40ChKEYREADAREAKey Store Read AreaKEYREADAREA Register (Offset = 40Ch) [Reset = 00000008h]
500h + formulaAESKEY2_yAES_KEY2_0 / AES_GHASH_H_IN_0AESKEY2_y Register (Offset = 500h + formula) [Reset = 00000000h]
510h + formulaAESKEY3_yAES_KEY3_0 / AES_KEY2_4AESKEY3_y Register (Offset = 510h + formula) [Reset = 00000000h]
540h + formulaAESIV_yAES initialization vector registersAESIV_y Register (Offset = 540h + formula) [Reset = 00000000h]
550hAESCTLAES ControlAESCTL Register (Offset = 550h) [Reset = 80000000h]
554hAESDATALEN0AES Crypto Length 0 (LSW)AESDATALEN0 Register (Offset = 554h) [Reset = 00000000h]
558hAESDATALEN1AES Crypto Length 1 (MSW)AESDATALEN1 Register (Offset = 558h) [Reset = 00000000h]
55ChAESAUTHLENAES Authentication LengthAESAUTHLEN Register (Offset = 55Ch) [Reset = 00000000h]
560hAESDATAOUT0Data Input/OutputAESDATAOUT0 Register (Offset = 560h) [Reset = 00000000h]
560hAESDATAIN0AES Data Input_Output 0AESDATAIN0 Register (Offset = 560h) [Reset = 00000000h]
564hAESDATAOUT1Data Input/OutputAESDATAOUT1 Register (Offset = 564h) [Reset = 00000000h]
564hAESDATAIN1AES Data Input_Output 0AESDATAIN1 Register (Offset = 564h) [Reset = 00000000h]
568hAESDATAOUT2Data Input/OutputAESDATAOUT2 Register (Offset = 568h) [Reset = 00000000h]
568hAESDATAIN2AES Data Input_Output 2AESDATAIN2 Register (Offset = 568h) [Reset = 00000000h]
56ChAESDATAOUT3Data Input/OutputAESDATAOUT3 Register (Offset = 56Ch) [Reset = 00000000h]
56ChAESDATAIN3AES Data Input_Output 3AESDATAIN3 Register (Offset = 56Ch) [Reset = 00000000h]
570h + formulaAESTAGOUT_yAES Tag Out 0AESTAGOUT_y Register (Offset = 570h + formula) [Reset = 00000000h]
604hHASHDATAIN1HASH Data Input 1HASHDATAIN1 Register (Offset = 604h) [Reset = 00000000h]
608hHASHDATAIN2HASH Data Input 2HASHDATAIN2 Register (Offset = 608h) [Reset = 00000000h]
60ChHASHDATAIN3HASH Data Input 3HASHDATAIN3 Register (Offset = 60Ch) [Reset = 00000000h]
610hHASHDATAIN4HASH Data Input 4HASHDATAIN4 Register (Offset = 610h) [Reset = 00000000h]
614hHASHDATAIN5HASH Data Input 5HASHDATAIN5 Register (Offset = 614h) [Reset = 00000000h]
618hHASHDATAIN6HASH Data Input 6HASHDATAIN6 Register (Offset = 618h) [Reset = 00000000h]
61ChHASHDATAIN7HASH Data Input 7HASHDATAIN7 Register (Offset = 61Ch) [Reset = 00000000h]
620hHASHDATAIN8HASH Data Input 8HASHDATAIN8 Register (Offset = 620h) [Reset = 00000000h]
624hHASHDATAIN9HASH Data Input 9HASHDATAIN9 Register (Offset = 624h) [Reset = 00000000h]
628hHASHDATAIN10HASH Data Input 10HASHDATAIN10 Register (Offset = 628h) [Reset = 00000000h]
62ChHASHDATAIN11HASH Data Input 11HASHDATAIN11 Register (Offset = 62Ch) [Reset = 00000000h]
630hHASHDATAIN12HASH Data Input 12HASHDATAIN12 Register (Offset = 630h) [Reset = 00000000h]
634hHASHDATAIN13HASH Data Input 13HASHDATAIN13 Register (Offset = 634h) [Reset = 00000000h]
638hHASHDATAIN14HASH Data Input 14HASHDATAIN14 Register (Offset = 638h) [Reset = 00000000h]
63ChHASHDATAIN15HASH Data Input 15HASHDATAIN15 Register (Offset = 63Ch) [Reset = 00000000h]
640hHASHDATAIN16HASH Data Input 16HASHDATAIN16 Register (Offset = 640h) [Reset = 00000000h]
644hHASHDATAIN17HASH Data Input 17HASHDATAIN17 Register (Offset = 644h) [Reset = 00000000h]
648hHASHDATAIN18HASH Data Input 18HASHDATAIN18 Register (Offset = 648h) [Reset = 00000000h]
64ChHASHDATAIN19HASH Data Input 19HASHDATAIN19 Register (Offset = 64Ch) [Reset = 00000000h]
650hHASHDATAIN20HASH Data Input 20HASHDATAIN20 Register (Offset = 650h) [Reset = 00000000h]
654hHASHDATAIN21HASH Data Input 21HASHDATAIN21 Register (Offset = 654h) [Reset = 00000000h]
658hHASHDATAIN22HASH Data Input 22HASHDATAIN22 Register (Offset = 658h) [Reset = 00000000h]
65ChHASHDATAIN23HASH Data Input 23HASHDATAIN23 Register (Offset = 65Ch) [Reset = 00000000h]
660hHASHDATAIN24HASH Data Input 24HASHDATAIN24 Register (Offset = 660h) [Reset = 00000000h]
664hHASHDATAIN25HASH Data Input 25HASHDATAIN25 Register (Offset = 664h) [Reset = 00000000h]
668hHASHDATAIN26HASH Data Input 26HASHDATAIN26 Register (Offset = 668h) [Reset = 00000000h]
66ChHASHDATAIN27HASH Data Input 27HASHDATAIN27 Register (Offset = 66Ch) [Reset = 00000000h]
670hHASHDATAIN28HASH Data Input 28HASHDATAIN28 Register (Offset = 670h) [Reset = 00000000h]
674hHASHDATAIN29HASH Data Input 29HASHDATAIN29 Register (Offset = 674h) [Reset = 00000000h]
678hHASHDATAIN30HASH Data Input 30HASHDATAIN30 Register (Offset = 678h) [Reset = 00000000h]
67ChHASHDATAIN31HASH Data Input 31HASHDATAIN31 Register (Offset = 67Ch) [Reset = 00000000h]
680hHASHIOBUFCTRLHASH Input_Output Buffer ControlHASHIOBUFCTRL Register (Offset = 680h) [Reset = 00000004h]
684hHASHMODEHASH ModeHASHMODE Register (Offset = 684h) [Reset = 00000000h]
688hHASHINLENLHASH Input Length LSBHASHINLENL Register (Offset = 688h) [Reset = 00000000h]
68ChHASHINLENHHASH Input Length MSBHASHINLENH Register (Offset = 68Ch) [Reset = 00000000h]
6C0hHASHDIGESTAHASH Digest AHASHDIGESTA Register (Offset = 6C0h) [Reset = 00000000h]
6C4hHASHDIGESTBHASH Digest BHASHDIGESTB Register (Offset = 6C4h) [Reset = 00000000h]
6C8hHASHDIGESTCHASH Digest CHASHDIGESTC Register (Offset = 6C8h) [Reset = 00000000h]
6CChHASHDIGESTDHASH Digest DHASHDIGESTD Register (Offset = 6CCh) [Reset = 00000000h]
6D0hHASHDIGESTEHASH Digest EHASHDIGESTE Register (Offset = 6D0h) [Reset = 00000000h]
6D4hHASHDIGESTFHASH Digest FHASHDIGESTF Register (Offset = 6D4h) [Reset = 00000000h]
6D8hHASHDIGESTGHASH Digest GHASHDIGESTG Register (Offset = 6D8h) [Reset = 00000000h]
6DChHASHDIGESTHHASH Digest HHASHDIGESTH Register (Offset = 6DCh) [Reset = 00000000h]
6E0hHASHDIGESTIHASH Digest IHASHDIGESTI Register (Offset = 6E0h) [Reset = 00000000h]
6E4hHASHDIGESTJHASH Digest JHASHDIGESTJ Register (Offset = 6E4h) [Reset = 00000000h]
6E8hHASHDIGESTKHASH Digest KHASHDIGESTK Register (Offset = 6E8h) [Reset = 00000000h]
6EChHASHDIGESTLHASH Digest LHASHDIGESTL Register (Offset = 6ECh) [Reset = 00000000h]
6F0hHASHDIGESTMHASH Digest MHASHDIGESTM Register (Offset = 6F0h) [Reset = 00000000h]
6F4hHASHDIGESTNHASH Digest NHASHDIGESTN Register (Offset = 6F4h) [Reset = 00000000h]
6F8hHASHDIGESTOHASH Digest 0HASHDIGESTO Register (Offset = 6F8h) [Reset = 00000000h]
6FChHASHDIGESTPHASH Digest PHASHDIGESTP Register (Offset = 6FCh) [Reset = 00000000h]
700hALGSELAlgorithm SelectALGSEL Register (Offset = 700h) [Reset = 000000000h]
704hDMAPROTCTLDMA Protection ControlDMAPROTCTL Register (Offset = 704h) [Reset = 00000000h]
740hSWRESETSoftware ResetSWRESET Register (Offset = 740h) [Reset = 00000000h]
780hIRQTYPEControl Interrupt ConfigurationIRQTYPE Register (Offset = 780h) [Reset = 00000000h]
784hIRQENControl Interrupt EnableIRQEN Register (Offset = 784h) [Reset = 00000000h]
788hIRQCLRControl Interrupt ClearIRQCLR Register (Offset = 788h) [Reset = 00000000h]
78ChIRQSETControl Interrupt SetIRQSET Register (Offset = 78Ch) [Reset = 00000000h]
790hIRQSTATControl Interrupt StatusIRQSTAT Register (Offset = 790h) [Reset = 00000000h]
7FChHWVERHardware VersionHWVER Register (Offset = 7FCh) [Reset = 92008778h]

Complex bit access types are encoded to fit into small table cells. Table 13-51 shows the codes that are used for access types in this section.

Table 13-51 CRYPTO Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

13.9.1.1 DMACH0CTL Register (Offset = 0h) [Reset = 00000000h]

DMACH0CTL is shown in Figure 13-8 and described in Table 13-52.

Return to the Summary Table.

Channel 0 Control
This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished.

Figure 13-8 DMACH0CTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPRIOEN
R-0hR/W-0hR/W-0h
Table 13-52 DMACH0CTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1PRIOR/W0hChannel priority
0: Low
1: High
If both channels have the same priority, access of the channels to the external port is arbitrated using the round robin scheme. If one channel has a high priority and another one low, the channel with the high priority is served first, in case of simultaneous access requests.
0ENR/W0hChannel enable
0: Disabled
1: Enable
Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested.

13.9.1.2 DMACH0EXTADDR Register (Offset = 4h) [Reset = 00000000h]

DMACH0EXTADDR is shown in Figure 13-9 and described in Table 13-53.

Return to the Summary Table.

Channel 0 External Address

Figure 13-9 DMACH0EXTADDR Register
313029282726252423222120191817161514131211109876543210
ADDR
R/W-0h
Table 13-53 DMACH0EXTADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR/W0hChannel external address value
When read during operation, it holds the last updated external address after being sent to the master interface. Note: The crypto DMA copies out upto 3 bytes until it hits a word boundary, thus the address need not be word aligned.

13.9.1.3 DMACH0LEN Register (Offset = Ch) [Reset = 00000000h]

DMACH0LEN is shown in Figure 13-10 and described in Table 13-54.

Return to the Summary Table.

Channel 0 DMA Length

Figure 13-10 DMACH0LEN Register
313029282726252423222120191817161514131211109876543210
RESERVEDDMALEN
R-0hR/W-0h
Table 13-54 DMACH0LEN Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DMALENR/W0hChannel DMA length in bytes
During configuration, this register contains the DMA transfer length in bytes. During operation, it contains the last updated value of the DMA transfer length after being sent to the master interface.
Note: Setting this register to a nonzero value starts the transfer if the channel is enabled. Therefore, this register must be written last when setting up a DMA channel.

13.9.1.4 DMASTAT Register (Offset = 18h) [Reset = 00000000h]

DMASTAT is shown in Figure 13-11 and described in Table 13-55.

Return to the Summary Table.

DMAC Status
This register provides the actual state of each DMA channel. It also reports port errors in case these were received by the master interface module during the data transfer.

Figure 13-11 DMASTAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDPORT_ERRRESERVED
R-0hR-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCH1_ACTCH0_ACT
R-0hR-0hR-0h
Table 13-55 DMASTAT Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17PORT_ERRR0hReflects possible transfer errors on the AHB port.
16-2RESERVEDR0hReserved
1CH1_ACTR0hA value of 1 indicates that channel 1 is active (DMA transfer on-going).
0CH0_ACTR0hA value of 1 indicates that channel 0 is active (DMA transfer on-going).

13.9.1.5 DMASWRESET Register (Offset = 1Ch) [Reset = 00000000h]

DMASWRESET is shown in Figure 13-12 and described in Table 13-56.

Return to the Summary Table.

DMAC Software Reset
Software reset is used to reset the DMAC to stop all transfers and clears the port error status register. After the software reset is performed, all the channels are disabled and no new requests are performed by the channels. The DMAC waits for the existing (active) requests to finish and accordingly sets the DMASTAT.

Figure 13-12 DMASWRESET Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSWRES
R-0hW-0h
Table 13-56 DMASWRESET Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0SWRESW0hSoftware reset enable
0 : Disabled
1 : Enabled (self-cleared to 0)
Completion of the software reset must be checked through the DMASTAT

13.9.1.6 DMACH1CTL Register (Offset = 20h) [Reset = 00000000h]

DMACH1CTL is shown in Figure 13-13 and described in Table 13-57.

Return to the Summary Table.

Channel 1 Control
This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished.

Figure 13-13 DMACH1CTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPRIOEN
R-0hR/W-0hR/W-0h
Table 13-57 DMACH1CTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1PRIOR/W0hChannel priority
0: Low
1: High
If both channels have the same priority, access of the channels to the external port is arbitrated using the round robin scheme. If one channel has a high priority and another one low, the channel with the high priority is served first, in case of simultaneous access requests.
0ENR/W0hChannel enable
0: Disabled
1: Enable
Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested.

13.9.1.7 DMACH1EXTADDR Register (Offset = 24h) [Reset = 00000000h]

DMACH1EXTADDR is shown in Figure 13-14 and described in Table 13-58.

Return to the Summary Table.

Channel 1 External Address

Figure 13-14 DMACH1EXTADDR Register
313029282726252423222120191817161514131211109876543210
ADDR
R/W-0h
Table 13-58 DMACH1EXTADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR/W0hChannel external address value.
When read during operation, it holds the last updated external address after being sent to the master interface. Note: The crypto DMA copies out upto 3 bytes until it hits a word boundary, thus the address need not be word aligned.

13.9.1.8 DMACH1LEN Register (Offset = 2Ch) [Reset = 00000000h]

DMACH1LEN is shown in Figure 13-15 and described in Table 13-59.

Return to the Summary Table.

Channel 1 DMA Length

Figure 13-15 DMACH1LEN Register
313029282726252423222120191817161514131211109876543210
RESERVEDDMALEN
R-0hR/W-0h
Table 13-59 DMACH1LEN Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DMALENR/W0hChannel DMA length in bytes.
During configuration, this register contains the DMA transfer length in bytes. During operation, it contains the last updated value of the DMA transfer length after being sent to the master interface.
Note: Setting this register to a nonzero value starts the transfer if the channel is enabled. Therefore, this register must be written last when setting up a DMA channel.

13.9.1.9 DMABUSCFG Register (Offset = 78h) [Reset = 00002400h]

DMABUSCFG is shown in Figure 13-16 and described in Table 13-60.

Return to the Summary Table.

DMAC Master Run-time Parameters
This register defines all the run-time parameters for the AHB master interface port. These parameters are required for the proper functioning of the EIP-101m AHB master adapter.

Figure 13-16 DMABUSCFG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AHB_MST1_BURST_SIZEAHB_MST1_IDLE_ENAHB_MST1_INCR_ENAHB_MST1_LOCK_ENAHB_MST1_BIGEND
R/W-2hR/W-0hR/W-1hR/W-0hR/W-0h
76543210
RESERVED
R-0h
Table 13-60 DMABUSCFG Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-12AHB_MST1_BURST_SIZER/W2hMaximum burst size that can be performed on the AHB bus
2h = 4_BYTE : 4 bytes
3h = 8_BYTE : 8 bytes
4h = 16_BYTE : 16 bytes
5h = 32_BYTE : 32 bytes
6h = 64_BYTE : 64 bytes
11AHB_MST1_IDLE_ENR/W0hIdle insertion between consecutive burst transfers on AHB
0h = Do not insert idle transfers.
1h = Idle transfer insertion enabled
10AHB_MST1_INCR_ENR/W1hBurst length type of AHB transfer
0h = Unspecified length burst transfers
1h = Fixed length bursts or single transfers
9AHB_MST1_LOCK_ENR/W0hLocked transform on AHB
0h = Transfers are not locked
1h = Transfers are locked
8AHB_MST1_BIGENDR/W0hEndianess for the AHB master
0h = Little Endian
1h = Big Endian
7-0RESERVEDR0hReserved

13.9.1.10 DMAPORTERR Register (Offset = 7Ch) [Reset = 00000000h]

DMAPORTERR is shown in Figure 13-17 and described in Table 13-61.

Return to the Summary Table.

DMAC Port Error Raw Status
This register provides the actual status of individual port errors. It also indicates which channel is serviced by an external AHB port (which is frozen by a port error). A port error aborts operations on all serviced channels (channel enable bit is forced to 0) and prevents further transfers via that port until the error is cleared by writing to the DMASWRESET register.

Figure 13-17 DMAPORTERR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDPORT1_AHB_ERRORRESERVEDPORT1_CHANNELRESERVED
R-0hR-0hR-0hR-0hR-0h
76543210
RESERVED
R-0h
Table 13-61 DMAPORTERR Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0hReserved
12PORT1_AHB_ERRORR0hA value of 1 indicates that the EIP-101 has detected an AHB bus error
11-10RESERVEDR0hReserved
9PORT1_CHANNELR0hIndicates which channel has serviced last (channel 0 or channel 1) by AHB master port.
8-0RESERVEDR0hReserved

13.9.1.11 DMAHWVER Register (Offset = FCh) [Reset = 01012ED1h]

DMAHWVER is shown in Figure 13-18 and described in Table 13-62.

Return to the Summary Table.

DMAC Version
This register contains an indication (or signature) of the EIP type of this DMAC, as well as the hardware version/patch numbers.

Figure 13-18 DMAHWVER Register
3130292827262524
RESERVEDHW_MAJOR_VERSION
R-0hR-1h
2322212019181716
HW_MINOR_VERSIONHW_PATCH_LEVEL
R-0hR-1h
15141312111098
EIP_NUMBER_COMPL
R-2Eh
76543210
EIP_NUMBER
R-D1h
Table 13-62 DMAHWVER Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27-24HW_MAJOR_VERSIONR1hMajor version number
23-20HW_MINOR_VERSIONR0hMinor version number
19-16HW_PATCH_LEVELR1hPatch level
Starts at 0 at first delivery of this version
15-8EIP_NUMBER_COMPLR2EhBit-by-bit complement of the EIP_NUMBER field bits.
7-0EIP_NUMBERRD1hBinary encoding of the EIP-number of this DMA controller (209)

13.9.1.12 KEYWRITEAREA Register (Offset = 400h) [Reset = 00000000h]

KEYWRITEAREA is shown in Figure 13-19 and described in Table 13-63.

Return to the Summary Table.

Key Store Write Area
This register defines where the keys should be written in the key store RAM. After writing this register, the key store module is ready to receive the keys through a DMA operation. In case the key data transfer triggered an error in the key store, the error will be available in the interrupt status register after the DMA is finished. The key store write-error is asserted when the programmed/selected area is not completely written. This error is also asserted when the DMA operation writes to ram areas that are not selected.
The key store RAM is divided into 8 areas of 128 bits.
192-bit keys written in the key store RAM should start on boundaries of 256 bits. This means that writing a 192-bit key to the key store RAM must be done by writing 256 bits of data with the 64 most-significant bits set to 0. These bits are ignored by the AES engine.

Figure 13-19 KEYWRITEAREA Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RAM_AREA7RAM_AREA6RAM_AREA5RAM_AREA4RAM_AREA3RAM_AREA2RAM_AREA1RAM_AREA0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 13-63 KEYWRITEAREA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7RAM_AREA7R/W0hEach RAM_AREAx represents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written
0: RAM_AREA7 is not selected to be written.
1: RAM_AREA7 is selected to be written.
Writing to multiple RAM locations is possible only when the selected RAM areas are sequential.
Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written
6RAM_AREA6R/W0hEach RAM_AREAx represents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written
0: RAM_AREA6 is not selected to be written.
1: RAM_AREA6 is selected to be written.
Writing to multiple RAM locations is possible only when the selected RAM areas are sequential.
Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written
5RAM_AREA5R/W0hEach RAM_AREAx represents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written
0: RAM_AREA5 is not selected to be written.
1: RAM_AREA5 is selected to be written.
Writing to multiple RAM locations is possible only when the selected RAM areas are sequential.
Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written
4RAM_AREA4R/W0hEach RAM_AREAx represents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written
0: RAM_AREA4 is not selected to be written.
1: RAM_AREA4 is selected to be written.
Writing to multiple RAM locations is possible only when the selected RAM areas are sequential.
Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written
3RAM_AREA3R/W0hEach RAM_AREAx represents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written
0: RAM_AREA3 is not selected to be written.
1: RAM_AREA3 is selected to be written.
Writing to multiple RAM locations is possible only when the selected RAM areas are sequential.
Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written
2RAM_AREA2R/W0hEach RAM_AREAx represents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written
0: RAM_AREA2 is not selected to be written.
1: RAM_AREA2 is selected to be written.
Writing to multiple RAM locations is possible only when the selected RAM areas are sequential.
Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written
1RAM_AREA1R/W0hEach RAM_AREAx represents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written
0: RAM_AREA1 is not selected to be written.
1: RAM_AREA1 is selected to be written.
Writing to multiple RAM locations is possible only when the selected RAM areas are sequential.
Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written
0RAM_AREA0R/W0hEach RAM_AREAx represents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be written
0: RAM_AREA0 is not selected to be written.
1: RAM_AREA0 is selected to be written.
Writing to multiple RAM locations is possible only when the selected RAM areas are sequential.
Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written

13.9.1.13 KEYWRITTENAREA Register (Offset = 404h) [Reset = 00000000h]

KEYWRITTENAREA is shown in Figure 13-20 and described in Table 13-64.

Return to the Summary Table.

Key Store Written Area
This register shows which areas of the key store RAM contain valid written keys.
When a new key needs to be written to the key store, on a location that is already occupied by a valid key, this key area must be cleared first. This can be done by writing this register before the new key is written to the key store memory.
Attempting to write to a key area that already contains a valid key is not allowed and results in an error.

Figure 13-20 KEYWRITTENAREA Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RAM_AREA_WRITTEN7RAM_AREA_WRITTEN6RAM_AREA_WRITTEN5RAM_AREA_WRITTEN4RAM_AREA_WRITTEN3RAM_AREA_WRITTEN2RAM_AREA_WRITTEN1RAM_AREA_WRITTEN0
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 13-64 KEYWRITTENAREA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7RAM_AREA_WRITTEN7R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information
6RAM_AREA_WRITTEN6R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information
5RAM_AREA_WRITTEN5R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information
4RAM_AREA_WRITTEN4R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information
3RAM_AREA_WRITTEN3R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information
2RAM_AREA_WRITTEN2R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information
1RAM_AREA_WRITTEN1R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information
0RAM_AREA_WRITTEN0R/W1C0hOn read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key store memory.

13.9.1.14 KEYSIZE Register (Offset = 408h) [Reset = 00000001h]

KEYSIZE is shown in Figure 13-21 and described in Table 13-65.

Return to the Summary Table.

Key Store Size
This register defines the size of the keys that are written with DMA. This register should be configured before writing to the KEY_STORE_WRITE_AREA register.

Figure 13-21 KEYSIZE Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSIZE
R-0hR/W-1h
Table 13-65 KEYSIZE Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0SIZER/W1hKey size:
00: Reserved
When writing this to this register, the KEY_STORE_WRITTEN_AREA register is reset.
1h = 128_BIT : 128 bits
2h = 192_BIT : 192 bits
3h = 256_BIT : 256 bits

13.9.1.15 KEYREADAREA Register (Offset = 40Ch) [Reset = 00000008h]

KEYREADAREA is shown in Figure 13-22 and described in Table 13-66.

Return to the Summary Table.

Key Store Read Area
This register selects the key store RAM area from where the key needs to be read that will be used for an AES operation. The operation directly starts after writing this register. When the operation is finished, the status of the key store read operation is available in the interrupt status register. Key store read error is asserted when a RAM area is selected which does not contain valid written key.

Figure 13-22 KEYREADAREA Register
3130292827262524
BUSYRESERVED
R-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRAM_AREA
R-0hR/W-8h
Table 13-66 KEYREADAREA Register Field Descriptions
BitFieldTypeResetDescription
31BUSYR0hKey store operation busy status flag (read only):
0: Operation is complete.
1: Operation is not completed and the key store is busy.
30-4RESERVEDR0hReserved
3-0RAM_AREAR/W8hSelects the area of the key store RAM from where the key needs to be read that will be writen to the AES engine
RAM_AREA:
RAM areas RAM_AREA0, RAM_AREA2, RAM_AREA4 and RAM_AREA6 are the only valid read areas for 192 and 256 bits key sizes.
Only RAM areas that contain valid written keys can be selected.
0h = RAM Area 0
1h = RAM Area 1
2h = RAM Area 2
3h = RAM Area 3
4h = RAM Area 4
5h = RAM Area 5
6h = RAM Area 6
7h = RAM Area 7
8h = No RAM

13.9.1.16 AESKEY2_y Register (Offset = 500h + formula) [Reset = 00000000h]

AESKEY2_y is shown in Figure 13-23 and described in Table 13-67.

Return to the Summary Table.

AES_KEY2_0 / AES_GHASH_H_IN_0
Second Key / GHASH Key (internal, but clearable)
The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s.
The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register.

Offset = 500h + (y * 4h); where y = 0h to 3h

Figure 13-23 AESKEY2_y Register
313029282726252423222120191817161514131211109876543210
AES_KEY2
W-0h
Table 13-67 AESKEY2_y Register Field Descriptions
BitFieldTypeResetDescription
31-0AES_KEY2W0hAES_KEY2/AES_GHASH_H[31:0]
For GCM:
-[127:0] - GHASH_H - The internally calculated GHASH key is stored in these registers. Only used for modes that use the GHASH function (GCM).
-[255:128] - This register is used to store intermediate values and is initialized with 0s when loading a new key.
For CCM:
-[255:0] - This register is used to store intermediate values.
For CBC-MAC:
-[255:0] - ZEROES - This register must remain 0.

13.9.1.17 AESKEY3_y Register (Offset = 510h + formula) [Reset = 00000000h]

AESKEY3_y is shown in Figure 13-24 and described in Table 13-68.

Return to the Summary Table.

AES_KEY3_0 / AES_KEY2_4
Third Key / Second Key (internal, but clearable)
The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s.
The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register.

Offset = 510h + (y * 4h); where y = 0h to 3h

Figure 13-24 AESKEY3_y Register
313029282726252423222120191817161514131211109876543210
AES_KEY3
W-0h
Table 13-68 AESKEY3_y Register Field Descriptions
BitFieldTypeResetDescription
31-0AES_KEY3W0hAES_KEY3[31:0]/AES_KEY2[159:128]
For GCM:
-[127:0] - GHASH_H - The internally calculated GHASH key is stored in these registers. Only used for modes that use the GHASH function (GCM).
-[255:128] - This register is used to store intermediate values and is initialized with 0s when loading a new key.
For CCM:
-[255:0] - This register is used to store intermediate values.
For CBC-MAC:
-[255:0] - ZEROES - This register must remain 0.

13.9.1.18 AESIV_y Register (Offset = 540h + formula) [Reset = 00000000h]

AESIV_y is shown in Figure 13-25 and described in Table 13-69.

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AES initialization vector registers
These registers are used to provide and read the IV from the AES engine.

Offset = 540h + (y * 4h); where y = 0h to 3h

Figure 13-25 AESIV_y Register
313029282726252423222120191817161514131211109876543210
AES_IV
R/W-0h
Table 13-69 AESIV_y Register Field Descriptions
BitFieldTypeResetDescription
31-0AES_IVR/W0hAES_IV[31:0]
Initialization vector
Used for regular non-ECB modes (CBC/CTR):
-[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers must be written with a new 128-bit IV. After an operation, these registers contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode is selected, this value is incremented with 0x1: After first use - When a new data block is submitted to the engine
For GCM:
-[127:0] - AES_IV - For GCM operations, these registers must be written with a new 128-bit IV.
After an operation, these registers contain the updated 128-bit result IV, generated by the EIP-120t. Note that bits [127:96] of the IV represent the initial counter value (which is 1 for GCM) and must therefore be initialized to 0x01000000. This value is incremented with 0x1: After first use - When a new data block is submitted to the engine.
For CCM:
-[127:0] - A0: For CCM this field must be written with value A0, this value is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and counter value. 'L' must be a copy from the 'L' value of the AES_CTRL register. This 'L' indicates the width of the Nonce and counter. The loaded counter must be initialized to 0. The total width of A0 is 128-bit.
For CBC-MAC:
-[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the start of each operation. After an operation, these registers contain the 128-bit TAG output, generated by the EIP-120t.

13.9.1.19 AESCTL Register (Offset = 550h) [Reset = 80000000h]

AESCTL is shown in Figure 13-26 and described in Table 13-70.

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AES Control
AES input/output buffer control and mode register
This register specifies the AES mode of operation for the EIP-120t.
Electronic codebook (ECB) mode is automatically selected if bits [28:5] of this register are all 0.

Figure 13-26 AESCTL Register
3130292827262524
CONTEXT_READYSAVED_CONTEXT_RDYSAVE_CONTEXTRESERVEDCCM_M
R-1hR/W-0hR/W-0hR-0hR/W-0h
2322212019181716
CCM_MCCM_LCCMGCM
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
CBC_MACRESERVEDCTR_WIDTH
R/W-0hR-0hR/W-0h
76543210
CTR_WIDTHCTRCBCKEY_SIZEDIRINPUT_READYOUTPUT_READY
R/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 13-70 AESCTL Register Field Descriptions
BitFieldTypeResetDescription
31CONTEXT_READYR1hIf 1, this read-only status bit indicates that the context data registers can be overwritten and the host is permitted to write the next context.
30SAVED_CONTEXT_RDYR/W0hIf 1, this status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the host to retrieve. This bit is only asserted if the save_context bit is set to 1. The bit is mutual exclusive with the context_ready bit.
Writing one clears the bit to 0, indicating the AES core can start its next operation. This bit is also cleared when the 4th word of the output TAG and/or IV is read.
Note: All other mode bit writes are ignored when this mode bit is written with 1.
Note: This bit is controlled automatically by the EIP-120t for TAG read DMA operations.
29SAVE_CONTEXTR/W0hThis bit indicates that an authentication TAG or result IV needs to be stored as a result context.
Typically this bit must be set for authentication modes returning a TAG (CBC-MAC, GCM and CCM), or for basic encryption modes that require future continuation with the current result IV.
If this bit is set, the engine retains its full context until the TAG and/or IV registers are read.
The TAG or IV must be read before the AES engine can start a new operation.
28-25RESERVEDR0hReserved
24-22CCM_MR/W0hDefines M, which indicates the length of the authentication field for CCM operations
the authentication field length equals two times (the value of CCM-M plus one).
Note: The EIP-120t always returns a 128-bit authentication field, of which the M least significant bytes are valid. All values are supported.
21-19CCM_LR/W0hDefines L, which indicates the width of the length field for CCM operations
the length field in bytes equals the value of CMM-L plus one. All values are supported.
18CCMR/W0hIf set to 1, AES-CCM is selected
AES-CCM is a combined mode, using AES for authentication and encryption.
Note: Selecting AES-CCM mode requires writing of the AAD length register after all other registers.
Note: The CTR mode bit in this register must also be set to 1 to enable AES-CTR
selecting other AES modes than CTR mode is invalid.
17-16GCMR/W0hSet these bits to 11 to select AES-GCM mode.
AES-GCM is a combined mode, using the Galois field multiplier GF(2 to the power of 128) for authentication and AES-CTR mode for encryption.
Note: The CTR mode bit in this register must also be set to 1 to enable AES-CTR
Bit combination description:
00 = No GCM mode
01 = Reserved, do not select
10 = Reserved, do not select
11 = Autonomous GHASH (both H- and Y0-encrypted calculated internally)
Note: The EIP-120t-1 configuration only supports mode 11 (autonomous GHASH), other GCM modes are not allowed.
15CBC_MACR/W0hSet to 1 to select AES-CBC MAC mode.
The direction bit must be set to 1 for this mode.
Selecting this mode requires writing the length register after all other registers.
14-9RESERVEDR0hReserved
8-7CTR_WIDTHR/W0hSpecifies the counter width for AES-CTR mode
00 = 32-bit counter
01 = 64-bit counter
10 = 96-bit counter
11 = 128-bit counter
0h = 32_BIT : 32 bits
1h = 64_BIT : 64 bits
2h = 96_BIT : 96 bits
3h = 128_BIT : 128 bits
6CTRR/W0hIf set to 1, AES counter mode (CTR) is selected.
Note: This bit must also be set for GCM and CCM, when encryption/decryption is required.
5CBCR/W0hIf set to 1, cipher-block-chaining (CBC) mode is selected.
4-3KEY_SIZER0hThis read-only field specifies the key size.
The key size is automatically configured when a new key is loaded through the key store module.
00 = N/A - Reserved
01 = 128-bit
10 = 192-bit
11 = 256-bit
2DIRR/W0hIf set to 1 an encrypt operation is performed.
If set to 0 a decrypt operation is performed.
This bit must be written with a 1 when CBC-MAC is selected.
1INPUT_READYR/W0hIf 1, this status bit indicates that the 16-byte AES input buffer is empty. The host is permitted to write the next block of data.
Writing 0 clears the bit to 0 and indicates that the AES core can use the provided input data block.
Writing 1 to this bit is ignored.
Note: For DMA operations, this bit is automatically controlled by the EIP-120t.
After reset, this bit is 0. After writing a context, this bit becomes 1.
0OUTPUT_READYR/W0hIf 1, this status bit indicates that an AES output block is available to be retrieved by the host.
Writing 0 clears the bit to 0 and indicates that output data is read by the host. The AES core can provide a next output data block.
Writing 1 to this bit is ignored.
Note: For DMA operations, this bit is automatically controlled by the EIP-120t.

13.9.1.20 AESDATALEN0 Register (Offset = 554h) [Reset = 00000000h]

AESDATALEN0 is shown in Figure 13-27 and described in Table 13-71.

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AES Crypto Length 0 (LSW)
These registers are used to write the Length values to the EIP-120t. While processing, the length values decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need to be processed with the same key. Writing 0 length results in continued data requests until a new context is written. For the other modes (CBC-MAC, GCM, and CCM) no (new) data requests are done if the length decrements to or equals 0.
It is advised to write a new length per packet. If the length registers decrement to 0, no new data is processed until a new context or length value is written.
When writing a new mode without writing the length registers, the length register values from the previous context is reused.

Figure 13-27 AESDATALEN0 Register
313029282726252423222120191817161514131211109876543210
C_LENGTH
W-0h
Table 13-71 AESDATALEN0 Register Field Descriptions
BitFieldTypeResetDescription
31-0C_LENGTHW0hC_LENGTH[31:0]
Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to 0. Data lengths up to (261: 1) bytes are allowed.
For GCM, any value up to 236 - 32 bytes can be used. This is because a 32-bit counter mode is used
the maximum number of 128-bit blocks is 232 - 2, resulting in a maximum number of bytes of 236 - 32.
A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM.
Note: For the combined modes (GCM and CCM), this length does not include the authentication only data
the authentication length is specified in the AESAUTHLEN register
All modes must have a length greater than 0. For the combined modes, it is allowed to have one of the lengths equal to 0.
For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program zero to the length field
in that case the length is assumed infinite.
All data must be byte (8-bit) aligned for stream cipher modes
bit aligned data streams are not supported by the EIP-120t. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes.
For a host read operation, these registers return all-0s.

13.9.1.21 AESDATALEN1 Register (Offset = 558h) [Reset = 00000000h]

AESDATALEN1 is shown in Figure 13-28 and described in Table 13-72.

Return to the Summary Table.

AES Crypto Length 1 (MSW)
These registers are used to write the Length values to the EIP-120t. While processing, the length values decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need to be processed with the same key. Writing 0 length results in continued data requests until a new context is written. For the other modes (CBC-MAC, GCM and CCM) no (new) data requests are done if the length decrements to or equals 0.
It is advised to write a new length per packet. If the length registers decrement to 0, no new data is processed until a new context or length value is written.
When writing a new mode without writing the length registers, the length register values from the previous context is reused.

Figure 13-28 AESDATALEN1 Register
31302928272625242322212019181716
RESERVEDC_LENGTH
R-0hW-0h
1514131211109876543210
C_LENGTH
W-0h
Table 13-72 AESDATALEN1 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-0C_LENGTHW0hC_LENGTH[60:32]
Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to 0. Data lengths up to (261: 1) bytes are allowed.
For GCM, any value up to 236 - 32 bytes can be used. This is because a 32-bit counter mode is used
the maximum number of 128-bit blocks is 232 - 2, resulting in a maximum number of bytes of 236 - 32.
A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM.
Note: For the combined modes (GCM and CCM), this length does not include the authentication only data
the authentication length is specified in the AESAUTHLEN register
All modes must have a length greater than 0. For the combined modes, it is allowed to have one of the lengths equal to 0.
For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program zero to the length field
in that case the length is assumed infinite.
All data must be byte (8-bit) aligned for stream cipher modes
bit aligned data streams are not supported by the EIP-120t. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes.
For a host read operation, these registers return all-0s.

13.9.1.22 AESAUTHLEN Register (Offset = 55Ch) [Reset = 00000000h]

AESAUTHLEN is shown in Figure 13-29 and described in Table 13-73.

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AES Authentication Length

Figure 13-29 AESAUTHLEN Register
313029282726252423222120191817161514131211109876543210
AUTH_LENGTH
W-0h
Table 13-73 AESAUTHLEN Register Field Descriptions
BitFieldTypeResetDescription
31-0AUTH_LENGTHW0hBits [31:0] of the authentication length register store the authentication data length in bytes for combined modes only (GCM or CCM).
Supported AAD-lengths for CCM are from 0 to (216 - 28) bytes. For GCM any value up to (232 - 1) bytes can be used. Once processing with this context is started, this length decrements to 0.
A write to this register triggers the engine to start using this context for GCM and CCM.
For a host read operation, these registers return all-0s.

13.9.1.23 AESDATAOUT0 Register (Offset = 560h) [Reset = 00000000h]

AESDATAOUT0 is shown in Figure 13-30 and described in Table 13-74.

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Data Input/Output

Figure 13-30 AESDATAOUT0 Register
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 13-74 AESDATAOUT0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hData register 0 for output block data from the Crypto peripheral.
These bits = AES Output Data[31:0] of {127:0]
For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA.
For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written.
For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data.
Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication.

13.9.1.24 AESDATAIN0 Register (Offset = 560h) [Reset = 00000000h]

AESDATAIN0 is shown in Figure 13-31 and described in Table 13-75.

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AES Data Input_Output 0
The data registers are typically accessed through the DMA and not with host writes and/or reads. However, for debugging purposes the data input/output registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t.
Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations.
Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written
for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers
these can be mixed with other host transfers over the external interface.

Figure 13-31 AESDATAIN0 Register
313029282726252423222120191817161514131211109876543210
AES_DATA_IN_OUT
W-0h
Table 13-75 AESDATAIN0 Register Field Descriptions
BitFieldTypeResetDescription
31-0AES_DATA_IN_OUTW0hAES input data[31:0] / AES output data[31:0]
Data registers for input/output block data to/from the EIP-120t.
For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register.
For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written.
For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data.
Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored.
Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication.

13.9.1.25 AESDATAOUT1 Register (Offset = 564h) [Reset = 00000000h]

AESDATAOUT1 is shown in Figure 13-32 and described in Table 13-76.

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Data Input/Output

Figure 13-32 AESDATAOUT1 Register
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 13-76 AESDATAOUT1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hData register 0 for output block data from the Crypto peripheral.
These bits = AES Output Data[31:0] of {127:0]
For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA.
For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written.
For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data.
Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication.

13.9.1.26 AESDATAIN1 Register (Offset = 564h) [Reset = 00000000h]

AESDATAIN1 is shown in Figure 13-33 and described in Table 13-77.

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AES Data Input_Output 0
The data registers are typically accessed through the DMA and not with host writes and/or reads. However, for debugging purposes the data input/output registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t.
Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations.
Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written
for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers
these can be mixed with other host transfers over the external interface.

Figure 13-33 AESDATAIN1 Register
313029282726252423222120191817161514131211109876543210
AES_DATA_IN_OUT
W-0h
Table 13-77 AESDATAIN1 Register Field Descriptions
BitFieldTypeResetDescription
31-0AES_DATA_IN_OUTW0hAES input data[31:0] / AES output data[63:32]
Data registers for input/output block data to/from the EIP-120t.
For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register.
For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written.
For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data.
Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored.
Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication.

13.9.1.27 AESDATAOUT2 Register (Offset = 568h) [Reset = 00000000h]

AESDATAOUT2 is shown in Figure 13-34 and described in Table 13-78.

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Data Input/Output

Figure 13-34 AESDATAOUT2 Register
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 13-78 AESDATAOUT2 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hData register 0 for output block data from the Crypto peripheral.
These bits = AES Output Data[31:0] of {127:0]
For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA.
For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written.
For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data.
Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication.

13.9.1.28 AESDATAIN2 Register (Offset = 568h) [Reset = 00000000h]

AESDATAIN2 is shown in Figure 13-35 and described in Table 13-79.

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AES Data Input_Output 2
The data registers are typically accessed via DMA and not with host writes and/or reads. However, for debugging purposes the Data Input/Output Registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t.
Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations.
Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written
for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers
these can be mixed with other host transfers over the external interface.

Figure 13-35 AESDATAIN2 Register
313029282726252423222120191817161514131211109876543210
AES_DATA_IN_OUT
W-0h
Table 13-79 AESDATAIN2 Register Field Descriptions
BitFieldTypeResetDescription
31-0AES_DATA_IN_OUTW0hAES input data[95:64] / AES output data[95:64]
Data registers for input/output block data to/from the EIP-120t.
For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register.
For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written.
For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data.
Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored.
Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication.

13.9.1.29 AESDATAOUT3 Register (Offset = 56Ch) [Reset = 00000000h]

AESDATAOUT3 is shown in Figure 13-36 and described in Table 13-80.

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Data Input/Output

Figure 13-36 AESDATAOUT3 Register
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 13-80 AESDATAOUT3 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hData register 0 for output block data from the Crypto peripheral.
These bits = AES Output Data[31:0] of {127:0]
For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA.
For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY must be written.
For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data.
Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication.

13.9.1.30 AESDATAIN3 Register (Offset = 56Ch) [Reset = 00000000h]

AESDATAIN3 is shown in Figure 13-37 and described in Table 13-81.

Return to the Summary Table.

AES Data Input_Output 3
The data registers are typically accessed via DMA and not with host writes and/or reads. However, for debugging purposes the Data Input/Output Registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t.
Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations.
Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written
for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers
these can be mixed with other host transfers over the external interface.

Figure 13-37 AESDATAIN3 Register
313029282726252423222120191817161514131211109876543210
AES_DATA_IN_OUT
W-0h
Table 13-81 AESDATAIN3 Register Field Descriptions
BitFieldTypeResetDescription
31-0AES_DATA_IN_OUTW0hAES input data[127:96] / AES output data[127:96]
Data registers for input/output block data to/from the EIP-120t.
For normal operations, this register is not used, since data input and output is transferred from and to the AES core via DMA. For a host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range stores the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to the input_ready flag of the AES_CTRL register.
For a host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, the output_ready flag of the AES_CTRL register must be written.
For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data.
Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored.
Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication.

13.9.1.31 AESTAGOUT_y Register (Offset = 570h + formula) [Reset = 00000000h]

AESTAGOUT_y is shown in Figure 13-38 and described in Table 13-82.

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AES Tag Out 0
The tag registers can be accessed via DMA or directly with host reads.
These registers buffer the TAG from the EIP-120t. The registers are shared with the intermediate authentication result registers, but cannot be read until the processing is finished. While processing, a read from these registers returns 0s. If an operation does not return a TAG, reading from these registers returns an IV. If an operation returns a TAG plus an IV and both need to be read by the host, the host must first read the TAG followed by the IV. Reading these in reverse order will return the IV twice.

Offset = 570h + (y * 4h); where y = 0h to 3h

Figure 13-38 AESTAGOUT_y Register
313029282726252423222120191817161514131211109876543210
AES_TAG
R-0h
Table 13-82 AESTAGOUT_y Register Field Descriptions
BitFieldTypeResetDescription
31-0AES_TAGR0hAES_TAG[31:0]
Bits [31:0] of this register stores the authentication value for the combined and authentication only modes.
For a host read operation, these registers contain the last 128-bit TAG output of the EIP-120t
the TAG is available until the next context is written.
This register will only contain valid data if the TAG is available and when the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for operations/modes that do not return a TAG, reads from this register return data from the IV register.

13.9.1.32 HASHDATAIN1 Register (Offset = 604h) [Reset = 00000000h]

HASHDATAIN1 is shown in Figure 13-39 and described in Table 13-83.

Return to the Summary Table.

HASH Data Input 1
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-39 HASHDATAIN1 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-83 HASHDATAIN1 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[63:32]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.33 HASHDATAIN2 Register (Offset = 608h) [Reset = 00000000h]

HASHDATAIN2 is shown in Figure 13-40 and described in Table 13-84.

Return to the Summary Table.

HASH Data Input 2
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-40 HASHDATAIN2 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-84 HASHDATAIN2 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[95:64]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.34 HASHDATAIN3 Register (Offset = 60Ch) [Reset = 00000000h]

HASHDATAIN3 is shown in Figure 13-41 and described in Table 13-85.

Return to the Summary Table.

HASH Data Input 3
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-41 HASHDATAIN3 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-85 HASHDATAIN3 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[127:96]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when the rfd_in bit of the HASH_IO_BUF_CTRL register is high. If the rfd_in bit is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASH_IO_BUF_CTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.35 HASHDATAIN4 Register (Offset = 610h) [Reset = 00000000h]

HASHDATAIN4 is shown in Figure 13-42 and described in Table 13-86.

Return to the Summary Table.

HASH Data Input 4
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-42 HASHDATAIN4 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-86 HASHDATAIN4 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[159:128]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is '1'. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.36 HASHDATAIN5 Register (Offset = 614h) [Reset = 00000000h]

HASHDATAIN5 is shown in Figure 13-43 and described in Table 13-87.

Return to the Summary Table.

HASH Data Input 5
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-43 HASHDATAIN5 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-87 HASHDATAIN5 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[191:160]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.37 HASHDATAIN6 Register (Offset = 618h) [Reset = 00000000h]

HASHDATAIN6 is shown in Figure 13-44 and described in Table 13-88.

Return to the Summary Table.

HASH Data Input 6
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-44 HASHDATAIN6 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-88 HASHDATAIN6 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[223:192]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.38 HASHDATAIN7 Register (Offset = 61Ch) [Reset = 00000000h]

HASHDATAIN7 is shown in Figure 13-45 and described in Table 13-89.

Return to the Summary Table.

HASH Data Input 7
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-45 HASHDATAIN7 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-89 HASHDATAIN7 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[255:224]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.39 HASHDATAIN8 Register (Offset = 620h) [Reset = 00000000h]

HASHDATAIN8 is shown in Figure 13-46 and described in Table 13-90.

Return to the Summary Table.

HASH Data Input 8
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-46 HASHDATAIN8 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-90 HASHDATAIN8 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[287:256]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.40 HASHDATAIN9 Register (Offset = 624h) [Reset = 00000000h]

HASHDATAIN9 is shown in Figure 13-47 and described in Table 13-91.

Return to the Summary Table.

HASH Data Input 9
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-47 HASHDATAIN9 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-91 HASHDATAIN9 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[319:288]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.41 HASHDATAIN10 Register (Offset = 628h) [Reset = 00000000h]

HASHDATAIN10 is shown in Figure 13-48 and described in Table 13-92.

Return to the Summary Table.

HASH Data Input 10
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-48 HASHDATAIN10 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-92 HASHDATAIN10 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[351:320]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.42 HASHDATAIN11 Register (Offset = 62Ch) [Reset = 00000000h]

HASHDATAIN11 is shown in Figure 13-49 and described in Table 13-93.

Return to the Summary Table.

HASH Data Input 11
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-49 HASHDATAIN11 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-93 HASHDATAIN11 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[383:352]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.43 HASHDATAIN12 Register (Offset = 630h) [Reset = 00000000h]

HASHDATAIN12 is shown in Figure 13-50 and described in Table 13-94.

Return to the Summary Table.

HASH Data Input 12
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-50 HASHDATAIN12 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-94 HASHDATAIN12 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[415:384]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.44 HASHDATAIN13 Register (Offset = 634h) [Reset = 00000000h]

HASHDATAIN13 is shown in Figure 13-51 and described in Table 13-95.

Return to the Summary Table.

HASH Data Input 13
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-51 HASHDATAIN13 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-95 HASHDATAIN13 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[447:416]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.45 HASHDATAIN14 Register (Offset = 638h) [Reset = 00000000h]

HASHDATAIN14 is shown in Figure 13-52 and described in Table 13-96.

Return to the Summary Table.

HASH Data Input 14
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-52 HASHDATAIN14 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-96 HASHDATAIN14 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[479:448]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.46 HASHDATAIN15 Register (Offset = 63Ch) [Reset = 00000000h]

HASHDATAIN15 is shown in Figure 13-53 and described in Table 13-97.

Return to the Summary Table.

HASH Data Input 15
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-53 HASHDATAIN15 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-97 HASHDATAIN15 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[511:480]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.47 HASHDATAIN16 Register (Offset = 640h) [Reset = 00000000h]

HASHDATAIN16 is shown in Figure 13-54 and described in Table 13-98.

Return to the Summary Table.

HASH Data Input 16
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-54 HASHDATAIN16 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-98 HASHDATAIN16 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[543:512]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.48 HASHDATAIN17 Register (Offset = 644h) [Reset = 00000000h]

HASHDATAIN17 is shown in Figure 13-55 and described in Table 13-99.

Return to the Summary Table.

HASH Data Input 17
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-55 HASHDATAIN17 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-99 HASHDATAIN17 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[575:544]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.49 HASHDATAIN18 Register (Offset = 648h) [Reset = 00000000h]

HASHDATAIN18 is shown in Figure 13-56 and described in Table 13-100.

Return to the Summary Table.

HASH Data Input 18
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-56 HASHDATAIN18 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-100 HASHDATAIN18 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[607:576]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.50 HASHDATAIN19 Register (Offset = 64Ch) [Reset = 00000000h]

HASHDATAIN19 is shown in Figure 13-57 and described in Table 13-101.

Return to the Summary Table.

HASH Data Input 19
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-57 HASHDATAIN19 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-101 HASHDATAIN19 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[639:608]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.51 HASHDATAIN20 Register (Offset = 650h) [Reset = 00000000h]

HASHDATAIN20 is shown in Figure 13-58 and described in Table 13-102.

Return to the Summary Table.

HASH Data Input 20
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-58 HASHDATAIN20 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-102 HASHDATAIN20 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[671:640]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.52 HASHDATAIN21 Register (Offset = 654h) [Reset = 00000000h]

HASHDATAIN21 is shown in Figure 13-59 and described in Table 13-103.

Return to the Summary Table.

HASH Data Input 21
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-59 HASHDATAIN21 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-103 HASHDATAIN21 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[703:672]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.53 HASHDATAIN22 Register (Offset = 658h) [Reset = 00000000h]

HASHDATAIN22 is shown in Figure 13-60 and described in Table 13-104.

Return to the Summary Table.

HASH Data Input 22
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-60 HASHDATAIN22 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-104 HASHDATAIN22 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[735:704]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.54 HASHDATAIN23 Register (Offset = 65Ch) [Reset = 00000000h]

HASHDATAIN23 is shown in Figure 13-61 and described in Table 13-105.

Return to the Summary Table.

HASH Data Input 23
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-61 HASHDATAIN23 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-105 HASHDATAIN23 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[767:736]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.55 HASHDATAIN24 Register (Offset = 660h) [Reset = 00000000h]

HASHDATAIN24 is shown in Figure 13-62 and described in Table 13-106.

Return to the Summary Table.

HASH Data Input 24
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-62 HASHDATAIN24 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-106 HASHDATAIN24 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[799:768]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.56 HASHDATAIN25 Register (Offset = 664h) [Reset = 00000000h]

HASHDATAIN25 is shown in Figure 13-63 and described in Table 13-107.

Return to the Summary Table.

HASH Data Input 25
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-63 HASHDATAIN25 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-107 HASHDATAIN25 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[831:800]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.57 HASHDATAIN26 Register (Offset = 668h) [Reset = 00000000h]

HASHDATAIN26 is shown in Figure 13-64 and described in Table 13-108.

Return to the Summary Table.

HASH Data Input 26
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-64 HASHDATAIN26 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-108 HASHDATAIN26 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[863:832]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.58 HASHDATAIN27 Register (Offset = 66Ch) [Reset = 00000000h]

HASHDATAIN27 is shown in Figure 13-65 and described in Table 13-109.

Return to the Summary Table.

HASH Data Input 27
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-65 HASHDATAIN27 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-109 HASHDATAIN27 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[895:864]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.59 HASHDATAIN28 Register (Offset = 670h) [Reset = 00000000h]

HASHDATAIN28 is shown in Figure 13-66 and described in Table 13-110.

Return to the Summary Table.

HASH Data Input 28
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-66 HASHDATAIN28 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-110 HASHDATAIN28 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[923:896]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.60 HASHDATAIN29 Register (Offset = 674h) [Reset = 00000000h]

HASHDATAIN29 is shown in Figure 13-67 and described in Table 13-111.

Return to the Summary Table.

HASH Data Input 29
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-67 HASHDATAIN29 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-111 HASHDATAIN29 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[959:924]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.61 HASHDATAIN30 Register (Offset = 678h) [Reset = 00000000h]

HASHDATAIN30 is shown in Figure 13-68 and described in Table 13-112.

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HASH Data Input 30
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-68 HASHDATAIN30 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-112 HASHDATAIN30 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[991:960]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.62 HASHDATAIN31 Register (Offset = 67Ch) [Reset = 00000000h]

HASHDATAIN31 is shown in Figure 13-69 and described in Table 13-113.

Return to the Summary Table.

HASH Data Input 31
The data input registers should be used to provide input data to the hash module through the slave interface.

Figure 13-69 HASHDATAIN31 Register
313029282726252423222120191817161514131211109876543210
HASH_DATA_IN
W-0h
Table 13-113 HASHDATAIN31 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DATA_INW0hHASH_DATA_IN[1023:992]
These registers must be written with the 512-bit input data. The data lines are connected directly to the data input of the hash module and hence into the engine's internal data buffer. Writing to each of the registers triggers a corresponding 32-bit write enable to the internal buffer.
Note: The host may only write the input data buffer when HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is busy with processing. During processing, it is not allowed to write new input data.
For message lengths larger than 64 bytes, multiple blocks of data are written to this input buffer using a handshake through flags of the HASHIOBUFCTRL register. All blocks except the last are required to be 512 bits in size. If the last block is not 512 bits long, only the least significant bits of data must be written, but they must be padded with 0s to the next 32-bit boundary.
Host read operations from these register addresses return 0s.

13.9.1.63 HASHIOBUFCTRL Register (Offset = 680h) [Reset = 00000004h]

HASHIOBUFCTRL is shown in Figure 13-70 and described in Table 13-114.

Return to the Summary Table.

HASH Input_Output Buffer Control
This register pair shares a single address location and contains bits that control and monitor the data flow between the host and the hash engine.

Figure 13-70 HASHIOBUFCTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
PAD_DMA_MESSAGEGET_DIGESTPAD_MESSAGERESERVEDRFD_INDATA_IN_AVOUTPUT_FULL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0h
Table 13-114 HASHIOBUFCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7PAD_DMA_MESSAGER/W0hNote: This bit must only be used when data is supplied through the DMA. It should not be used when data is supplied through the slave interface.
This bit indicates whether the hash engine has to pad the message, received through the DMA and finalize the hash.
When set to 1, the hash engine pads the last block using the programmed length. After padding, the final hash result is calculated.
When set to 0, the hash engine treats the last written block as block-size aligned and calculates the intermediate digest.
This bit is automatically cleared when the last DMA data block is arrived in the hash engine.
6GET_DIGESTR/W0hNote: The bit description below is only applicable when data is sent through the slave interface. This bit must be set to 0 when data is received through the DMA.
This bit indicates whether the hash engine should provide the hash digest.
When provided simultaneously with data_in_av, the hash digest is provided after processing the data that is currently in the HASHDATAINn register. When provided without data_in_av, the current internal digest buffer value is copied to the HASHDIGESTn registers.
The host must write a 1 to this bit to make the intermediate hash digest available.
Writing 0 to this bit has no effect.
This bit is automatically cleared (that is, reads 0) when the hash engine has processed the contents of the HASHDATAINn register. In the period between this bit is set by the host and the actual HASHDATAINn processing, this bit reads 1.
5PAD_MESSAGER/W0hNote: The bit description below is only applicable when data is sent through the slave interface. This bit must be set to 0 when data is received through the DMA.
This bit indicates that the HASHDATAINn registers hold the last data of the message and hash padding must be applied.
The host must write this bit to 1 in order to indicate to the hash engine that the HASHDATAINn register currently holds the last data of the message. When pad_message is set to 1, the hash engine will add padding bits to the data currently in the HASHDATAINn register.
When the last message block is smaller than 512 bits, the pad_message bit must be set to 1 together with the data_in_av bit.
When the last message block is equal to 512 bits, pad_message may be set together with data_in_av. In this case the pad_message bit may also be set after the last data block has been written to the hash engine (so when the rfd_in bit has become 1 again after writing the last data block).
Writing 0 to this bit has no effect.
This bit is automatically cleared (i.e. reads 0) by the hash engine. This bit reads 1 between the time it was set by the host and the hash engine interpreted its value.
4-3RESERVEDR/W0hWrite 0s and ignore on reading
2RFD_INR/W1hNote: The bit description below is only applicable when data is sent through the slave interface. This bit can be ignored when data is received through the DMA.
Read-only status of the input buffer of the hash engine.
When 1, the input buffer of the hash engine can accept new data
the HASHDATAINn registers can safely be populated with new data.
When 0, the input buffer of the hash engine is processing the data that is currently in HASHDATAINn
writing new data to these registers is not allowed.
1DATA_IN_AVR/W0hNote: The bit description below is only applicable when data is sent through the slave interface. This bit must be set to 0 when data is received through the DMA.
This bit indicates that the HASHDATAINn registers contain new input data for processing.
The host must write a 1 to this bit to start processing the data in HASHDATAINn
the hash engine will process the new data as soon as it is ready for it (rfd_in bit is 1).
Writing 0 to this bit has no effect.
This bit is automatically cleared (i.e. reads as 0) when the hash engine starts processing the HASHDATAINn contents. This bit reads 1 between the time it was set by the host and the hash engine actually starts processing the input data block.
0OUTPUT_FULLR/W0hIndicates that the output buffer registers (HASHDIGESTn) are available for reading by the host.
When this bit reads 0, the output buffer registers are released
the hash engine is allowed to write new data to it. In this case, the registers should not be read by the host.
When this bit reads 1, the hash engine has stored the result of the latest hash operation in the output buffer registers. As long as this bit reads 1, the host may read output buffer registers and the hash engine is prevented from writing new data to the output buffer.
After retrieving the hash result data from the output buffer, the host must write a 1 to this bit to clear it. This makes the digest output buffer available for the hash engine to store new hash results.
Writing 0 to this bit has no effect.
Note: If this bit is asserted (1) no new operation should be started before the digest is retrieved from the hash engine and this bit is cleared (0).

13.9.1.64 HASHMODE Register (Offset = 684h) [Reset = 00000000h]

HASHMODE is shown in Figure 13-71 and described in Table 13-115.

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HASH Mode

Figure 13-71 HASHMODE Register
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDSHA384_MODESHA512_MODESHA224_MODESHA256_MODERESERVEDNEW_HASH
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 13-115 HASHMODE Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDW0hWrite 0s and ignore on reading
6SHA384_MODEW0hThe host must write this bit with 1 prior to processing a SHA 384 session.
5SHA512_MODEW0hThe host must write this bit with 1 prior to processing a SHA 512 session.
4SHA224_MODEW0hThe host must write this bit with 1 prior to processing a SHA 224 session.
3SHA256_MODEW0hThe host must write this bit with 1 prior to processing a SHA 256 session.
2-1RESERVEDW0hWrite 0s and ignore on reading
0NEW_HASHW0hWhen set to 1, it indicates that the hash engine must start processing a new hash session. The [HASHDIGESTn.* ] registers will automatically be loaded with the initial hash algorithm constants of the selected hash algorithm.
When this bit is 0 while the hash processing is started, the initial hash algorithm constants are not loaded in the HASHDIGESTn registers. The hash engine will start processing with the digest that is currently in its internal HASHDIGESTn registers.
This bit is automatically cleared when hash processing is started.

13.9.1.65 HASHINLENL Register (Offset = 688h) [Reset = 00000000h]

HASHINLENL is shown in Figure 13-72 and described in Table 13-116.

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HASH Input Length LSB

Figure 13-72 HASHINLENL Register
313029282726252423222120191817161514131211109876543210
LENGTH_IN
W-0h
Table 13-116 HASHINLENL Register Field Descriptions
BitFieldTypeResetDescription
31-0LENGTH_INW0hLENGTH_IN[31:0]
Message length registers. The content of these registers is used by the hash engine during the message padding phase of the hash session. The data lines of this registers are directly connected to the interface of the hash engine.
For a write operation by the host, these registers should be written with the message length in bits.
Final hash operations:
The total input data length must be programmed for new hash operations that require finalization (padding). The input data must be provided through the slave or DMA interface.
Continued hash operations (finalized):
For continued hash operations that require finalization, the total message length must be programmed, including the length of previously hashed data that corresponds to the written input digest.
Non-final hash operations:
For hash operations that do not require finalization (input data length is multiple of 512-bits which is SHA-256 data block size), the length field does not need to be programmed since not used by the operation.
If the message length in bits is below (232-1), then only this register needs to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s in this case.
The host may write the length register at any time during the hash session when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written before the last data of the active hash session is written into the hash engine.
host read operations from these register locations will return 0s.
Note: When getting data from DMA, this register must be programmed before DMA is programmed to start.

13.9.1.66 HASHINLENH Register (Offset = 68Ch) [Reset = 00000000h]

HASHINLENH is shown in Figure 13-73 and described in Table 13-117.

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HASH Input Length MSB

Figure 13-73 HASHINLENH Register
313029282726252423222120191817161514131211109876543210
LENGTH_IN
W-0h
Table 13-117 HASHINLENH Register Field Descriptions
BitFieldTypeResetDescription
31-0LENGTH_INW0hLENGTH_IN[63:32]
Message length registers. The content of these registers is used by the hash engine during the message padding phase of the hash session. The data lines of this registers are directly connected to the interface of the hash engine.
For a write operation by the host, these registers should be written with the message length in bits.
Final hash operations:
The total input data length must be programmed for new hash operations that require finalization (padding). The input data must be provided through the slave or DMA interface.
Continued hash operations (finalized):
For continued hash operations that require finalization, the total message length must be programmed, including the length of previously hashed data that corresponds to the written input digest.
Non-final hash operations:
For hash operations that do not require finalization (input data length is multiple of 512-bits which is SHA-256 data block size), the length field does not need to be programmed since not used by the operation.
If the message length in bits is below (232-1), then only HASHINLENL needs to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s in this case.
The host may write the length register at any time during the hash session when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written before the last data of the active hash session is written into the hash engine.
host read operations from these register locations will return 0s.
Note: When getting data from DMA, this register must be programmed before DMA is programmed to start.

13.9.1.67 HASHDIGESTA Register (Offset = 6C0h) [Reset = 00000000h]

HASHDIGESTA is shown in Figure 13-74 and described in Table 13-118.

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HASH Digest A
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-74 HASHDIGESTA Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-118 HASHDIGESTA Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[31:0]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.68 HASHDIGESTB Register (Offset = 6C4h) [Reset = 00000000h]

HASHDIGESTB is shown in Figure 13-75 and described in Table 13-119.

Return to the Summary Table.

HASH Digest B
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-75 HASHDIGESTB Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-119 HASHDIGESTB Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[63:32]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.69 HASHDIGESTC Register (Offset = 6C8h) [Reset = 00000000h]

HASHDIGESTC is shown in Figure 13-76 and described in Table 13-120.

Return to the Summary Table.

HASH Digest C
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-76 HASHDIGESTC Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-120 HASHDIGESTC Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[95:64]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.70 HASHDIGESTD Register (Offset = 6CCh) [Reset = 00000000h]

HASHDIGESTD is shown in Figure 13-77 and described in Table 13-121.

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HASH Digest D
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-77 HASHDIGESTD Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-121 HASHDIGESTD Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[127:96]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.71 HASHDIGESTE Register (Offset = 6D0h) [Reset = 00000000h]

HASHDIGESTE is shown in Figure 13-78 and described in Table 13-122.

Return to the Summary Table.

HASH Digest E
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-78 HASHDIGESTE Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-122 HASHDIGESTE Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[159:128]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.72 HASHDIGESTF Register (Offset = 6D4h) [Reset = 00000000h]

HASHDIGESTF is shown in Figure 13-79 and described in Table 13-123.

Return to the Summary Table.

HASH Digest F
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-79 HASHDIGESTF Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-123 HASHDIGESTF Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[191:160]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.73 HASHDIGESTG Register (Offset = 6D8h) [Reset = 00000000h]

HASHDIGESTG is shown in Figure 13-80 and described in Table 13-124.

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HASH Digest G
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-80 HASHDIGESTG Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-124 HASHDIGESTG Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[223:192]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.74 HASHDIGESTH Register (Offset = 6DCh) [Reset = 00000000h]

HASHDIGESTH is shown in Figure 13-81 and described in Table 13-125.

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HASH Digest H
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-81 HASHDIGESTH Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-125 HASHDIGESTH Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[255:224]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.75 HASHDIGESTI Register (Offset = 6E0h) [Reset = 00000000h]

HASHDIGESTI is shown in Figure 13-82 and described in Table 13-126.

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HASH Digest I
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-82 HASHDIGESTI Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-126 HASHDIGESTI Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[287:256]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.76 HASHDIGESTJ Register (Offset = 6E4h) [Reset = 00000000h]

HASHDIGESTJ is shown in Figure 13-83 and described in Table 13-127.

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HASH Digest J
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-83 HASHDIGESTJ Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-127 HASHDIGESTJ Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[319:288]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.77 HASHDIGESTK Register (Offset = 6E8h) [Reset = 00000000h]

HASHDIGESTK is shown in Figure 13-84 and described in Table 13-128.

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HASH Digest K
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-84 HASHDIGESTK Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-128 HASHDIGESTK Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[351:320]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.78 HASHDIGESTL Register (Offset = 6ECh) [Reset = 00000000h]

HASHDIGESTL is shown in Figure 13-85 and described in Table 13-129.

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HASH Digest L
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-85 HASHDIGESTL Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-129 HASHDIGESTL Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[383:352]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.79 HASHDIGESTM Register (Offset = 6F0h) [Reset = 00000000h]

HASHDIGESTM is shown in Figure 13-86 and described in Table 13-130.

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HASH Digest M
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-86 HASHDIGESTM Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-130 HASHDIGESTM Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[415:384]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.80 HASHDIGESTN Register (Offset = 6F4h) [Reset = 00000000h]

HASHDIGESTN is shown in Figure 13-87 and described in Table 13-131.

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HASH Digest N
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-87 HASHDIGESTN Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-131 HASHDIGESTN Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[447:416]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.81 HASHDIGESTO Register (Offset = 6F8h) [Reset = 00000000h]

HASHDIGESTO is shown in Figure 13-88 and described in Table 13-132.

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HASH Digest 0
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-88 HASHDIGESTO Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-132 HASHDIGESTO Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[479:448]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.82 HASHDIGESTP Register (Offset = 6FCh) [Reset = 00000000h]

HASHDIGESTP is shown in Figure 13-89 and described in Table 13-133.

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HASH Digest P
The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

Figure 13-89 HASHDIGESTP Register
313029282726252423222120191817161514131211109876543210
HASH_DIGEST
R/W-0h
Table 13-133 HASHDIGESTP Register Field Descriptions
BitFieldTypeResetDescription
31-0HASH_DIGESTR/W0hHASH_DIGEST[511:480]
Hash digest registers
Write operation:
Continued hash:
These registers should be written with the context data, before the start of a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash session).
New hash:
When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the internal digest registers are automatically set to the SHA-256 algorithm constant and these register should not be written.
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing.

13.9.1.83 ALGSEL Register (Offset = 700h) [Reset = 000000000h]

ALGSEL is shown in Table 13-134.

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Algorithm Select
This algorithm selection register configures the internal destination of the DMA controller.

Table 13-134 ALGSEL Register Field Descriptions
BitFieldTypeResetDescription
32HASH_SHA_512R/W0hIf set to one, selects the hash engine in 512B mode as destination for the DMA
The maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out through the DMA).
31TAGR/W0hIf this bit is cleared to 0, the DMA operation involves only data.
If this bit is set, the DMA operation includes a TAG (Authentication Result / Digest).
For SHA-256 operation, a DMA must be set up for both input data and TAG. For any other selected module, setting this bit only allows a DMA that reads the TAG. No data allowed to be transferred to or from the selected module via the DMA.
30-4RESERVEDR0hReserved
3RESERVEDR/W0h
2HASH_SHA_256R/W0hIf set to one, selects the hash engine in 256B mode as destination for the DMA
The maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out through the DMA).
1AESR/W0hIf set to one, selects the AES engine as source/destination for the DMA
The read and write maximum transfer size to the DMA engine is set to 16 bytes.
0KEY_STORER/W0hIf set to one, selects the Key Store as destination for the DMA
The maximum transfer size to DMA engine is set to 32 bytes (however transfers of 16, 24 and 32 bytes are allowed)

13.9.1.84 DMAPROTCTL Register (Offset = 704h) [Reset = 00000000h]

DMAPROTCTL is shown in Figure 13-90 and described in Table 13-135.

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DMA Protection Control
Master PROT privileged access enable
This register enables the second bit (bit [1]) of the AHB HPROT bus of the AHB master interface when a read action of key(s) is performed on the AHB master interface for writing keys into the store module.

Figure 13-90 DMAPROTCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPROT_EN
R-0hR/W-0h
Table 13-135 DMAPROTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0PROT_ENR/W0hSelect AHB transfer protection control for DMA transfers using the key store area as destination.
0 : transfers use 'USER' type access.
1 : transfers use 'PRIVILEGED' type access.

13.9.1.85 SWRESET Register (Offset = 740h) [Reset = 00000000h]

SWRESET is shown in Figure 13-91 and described in Table 13-136.

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Software Reset

Figure 13-91 SWRESET Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSW_RESET
R-0hR/W-0h
Table 13-136 SWRESET Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0SW_RESETR/W0hIf this bit is set to 1, the following modules are reset:
- Master control internal state is reset. That includes interrupt, error status register, and result available interrupt generation FSM.
- Key store module state is reset. That includes clearing the written area flags
therefore, the keys must be reloaded to the key store module.
Writing 0 has no effect.
The bit is self cleared after executing the reset.

13.9.1.86 IRQTYPE Register (Offset = 780h) [Reset = 00000000h]

IRQTYPE is shown in Figure 13-92 and described in Table 13-137.

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Control Interrupt Configuration

Figure 13-92 IRQTYPE Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDLEVEL
R-0hR/W-0h
Table 13-137 IRQTYPE Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0LEVELR/W0hIf this bit is 0, the interrupt output is a pulse.
If this bit is set to 1, the interrupt is a level interrupt that must be cleared by writing the interrupt clear register.
This bit is applicable for both interrupt output signals.

13.9.1.87 IRQEN Register (Offset = 784h) [Reset = 00000000h]

IRQEN is shown in Figure 13-93 and described in Table 13-138.

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Control Interrupt Enable

Figure 13-93 IRQEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA_IN_DONERESULT_AVAIL
R-0hR/W-0hR/W-0h
Table 13-138 IRQEN Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1DMA_IN_DONER/W0hIf this bit is set to 0, the DMA input done (irq_dma_in_done) interrupt output is disabled and remains 0.
If this bit is set to 1, the DMA input done interrupt output is enabled.
0RESULT_AVAILR/W0hIf this bit is set to 0, the result available (irq_result_av) interrupt output is disabled and remains 0.
If this bit is set to 1, the result available interrupt output is enabled.

13.9.1.88 IRQCLR Register (Offset = 788h) [Reset = 00000000h]

IRQCLR is shown in Figure 13-94 and described in Table 13-139.

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Control Interrupt Clear

Figure 13-94 IRQCLR Register
3130292827262524
DMA_BUS_ERRKEY_ST_WR_ERRKEY_ST_RD_ERRRESERVED
W-0hW-0hW-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA_IN_DONERESULT_AVAIL
R-0hW-0hW-0h
Table 13-139 IRQCLR Register Field Descriptions
BitFieldTypeResetDescription
31DMA_BUS_ERRW0hIf 1 is written to this bit, the DMA bus error status is cleared.
Writing 0 has no effect.
30KEY_ST_WR_ERRW0hIf 1 is written to this bit, the key store write error status is cleared.
Writing 0 has no effect.
29KEY_ST_RD_ERRW0hIf 1 is written to this bit, the key store read error status is cleared.
Writing 0 has no effect.
28-2RESERVEDR0hReserved
1DMA_IN_DONEW0hIf 1 is written to this bit, the DMA in done (irq_dma_in_done) interrupt output is cleared.
Writing 0 has no effect.
Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE).
0RESULT_AVAILW0hIf 1 is written to this bit, the result available (irq_result_av) interrupt output is cleared.
Writing 0 has no effect.
Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE).

13.9.1.89 IRQSET Register (Offset = 78Ch) [Reset = 00000000h]

IRQSET is shown in Figure 13-95 and described in Table 13-140.

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Control Interrupt Set

Figure 13-95 IRQSET Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA_IN_DONERESULT_AVAIL
R-0hW-0hW-0h
Table 13-140 IRQSET Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1DMA_IN_DONEW0hIf 1 is written to this bit, the DMA data in done (irq_dma_in_done) interrupt output is set to one.
Writing 0 has no effect.
If the interrupt configuration register is programmed to pulse, clearing the DMA data in done (irq_dma_in_done) interrupt is not needed. If it is programmed to level, clearing the interrupt output should be done by writing the interrupt clear register (IRQCLR.DMA_IN_DONE).
0RESULT_AVAILW0hIf 1 is written to this bit, the result available (irq_result_av) interrupt output is set to one.
Writing 0 has no effect.
If the interrupt configuration register is programmed to pulse, clearing the result available (irq_result_av) interrupt is not needed. If it is programmed to level, clearing the interrupt output should be done by writing the interrupt clear register (IRQCLR.RESULT_AVAIL).

13.9.1.90 IRQSTAT Register (Offset = 790h) [Reset = 00000000h]

IRQSTAT is shown in Figure 13-96 and described in Table 13-141.

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Control Interrupt Status

Figure 13-96 IRQSTAT Register
3130292827262524
DMA_BUS_ERRKEY_ST_WR_ERRKEY_ST_RD_ERRRESERVED
R-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA_IN_DONERESULT_AVAIL
R-0hR-0hR-0h
Table 13-141 IRQSTAT Register Field Descriptions
BitFieldTypeResetDescription
31DMA_BUS_ERRR0hThis bit is set when a DMA bus error is detected during a DMA operation. The value of this register is held until it is cleared through the IRQCLR.DMA_BUS_ERR
Note: This error is asserted if an error is detected on the AHB master interface during a DMA operation.
30KEY_ST_WR_ERRR0hThis bit is set when a write error is detected during the DMA write operation to the key store memory. The value of this register is held until it is cleared through the IRQCLR.KEY_ST_WR_ERR register.
Note: This error is asserted if a DMA operation does not cover a full key area or more areas are written than expected.
29KEY_ST_RD_ERRR0hThis bit is set when a read error is detected during the read of a key from the key store, while copying it to the AES core. The value of this register is held until it is cleared through the IRQCLR.KEY_ST_RD_ERR register.
Note: This error is asserted if a key location is selected in the key store that is not available.
28-2RESERVEDR0hReserved
1DMA_IN_DONER0hThis read only bit returns the actual DMA data in done (irq_data_in_done) interrupt status of the DMA data in done interrupt output pin (irq_data_in_done).
0RESULT_AVAILR0hThis read only bit returns the actual result available (irq_result_av) interrupt status of the result available interrupt output pin (irq_result_av).

13.9.1.91 HWVER Register (Offset = 7FCh) [Reset = 92008778h]

HWVER is shown in Figure 13-97 and described in Table 13-142.

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Hardware Version

Figure 13-97 HWVER Register
31302928272625242322212019181716
RESERVEDHW_MAJOR_VERHW_MINOR_VERHW_PATCH_LVL
R-0hR-2hR-0hR-0h
1514131211109876543210
VER_NUM_COMPLVER_NUM
R-87hR-78h
Table 13-142 HWVER Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27-24HW_MAJOR_VERR2hMajor version number
23-20HW_MINOR_VERR0hMinor version number
19-16HW_PATCH_LVLR0hPatch level
Starts at 0 at first delivery of this version
15-8VER_NUM_COMPLR87hThese bits simply contain the complement of bits [7:0] (0x87), used by a driver to ascertain that the EIP-120t register is indeed read.
7-0VER_NUMR78hThese bits encode the EIP number for the EIP-120t, this field contains the value 120 (decimal) or 0x78.