SWCU185F january   2018  – march 2023 CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5. 1.1 Trademarks
  2. 2 Architectural Overview
    1. 2.1 Target Applications
    2. 2.2 Overview
    3. 2.3 Functional Overview
      1. 2.3.1  Arm® Cortex®-M4F
        1. 2.3.1.1 Processor Core
        2. 2.3.1.2 System Timer (SysTick)
        3. 2.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 2.3.1.4 System Control Block
      2. 2.3.2  On-Chip Memory
        1. 2.3.2.1 SRAM
        2. 2.3.2.2 Flash Memory
        3. 2.3.2.3 ROM
      3. 2.3.3  Radio
      4. 2.3.4  Security Core
      5. 2.3.5  General-Purpose Timers
        1. 2.3.5.1 Watchdog Timer
        2. 2.3.5.2 Always-On Domain
      6. 2.3.6  Direct Memory Access
      7. 2.3.7  System Control and Clock
      8. 2.3.8  Serial Communication Peripherals
        1. 2.3.8.1 UART
        2. 2.3.8.2 I2C
        3. 2.3.8.3 I2S
        4. 2.3.8.4 SSI
      9. 2.3.9  Programmable I/Os
      10. 2.3.10 Sensor Controller
      11. 2.3.11 Random Number Generator
      12. 2.3.12 cJTAG and JTAG
      13. 2.3.13 Power Supply System
        1. 2.3.13.1 Supply System
          1. 2.3.13.1.1 VDDS
          2. 2.3.13.1.2 VDDR
          3. 2.3.13.1.3 Digital Core Supply
          4. 2.3.13.1.4 Other Internal Supplies
        2. 2.3.13.2 DC/DC Converter
  3. 3 Arm® Cortex®-M4F Processor
    1. 3.1 Arm® Cortex®-M4F Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 Overview
      1. 3.3.1 System-Level Interface
      2. 3.3.2 Integrated Configurable Debug
      3. 3.3.3 Trace Port Interface Unit
      4. 3.3.4 Floating Point Unit (FPU)
      5. 3.3.5 Memory Protection Unit (MPU)
      6. 3.3.6 Arm® Cortex®-M4F System Component Details
    4. 3.4 Programming Model
      1. 3.4.1 Processor Mode and Privilege Levels for Software Execution
      2. 3.4.2 Stacks
      3. 3.4.3 Exceptions and Interrupts
      4. 3.4.4 Data Types
    5. 3.5 Arm® Cortex®-M4F Core Registers
      1. 3.5.1 Core Register Map
      2. 3.5.2 Core Register Descriptions
        1. 3.5.2.1  Cortex®General-Purpose Register 0 (R0)
        2. 3.5.2.2  Cortex® General-Purpose Register 1 (R1)
        3. 3.5.2.3  Cortex® General-Purpose Register 2 (R2)
        4. 3.5.2.4  Cortex® General-Purpose Register 3 (R3)
        5. 3.5.2.5  Cortex® General-Purpose Register 4 (R4)
        6. 3.5.2.6  Cortex® General-Purpose Register 5 (R5)
        7. 3.5.2.7  Cortex® General-Purpose Register 6 (R6)
        8. 3.5.2.8  Cortex® General-Purpose Register 7 (R7)
        9. 3.5.2.9  Cortex® General-Purpose Register 8 (R8)
        10. 3.5.2.10 Cortex® General-Purpose Register 9 (R9)
        11. 3.5.2.11 Cortex® General-Purpose Register 10 (R10)
        12. 3.5.2.12 Cortex® General-Purpose Register 11 (R11)
        13. 3.5.2.13 Cortex® General-Purpose Register 12 (R12)
        14. 3.5.2.14 Stack Pointer (SP)
        15. 3.5.2.15 Link Register (LR)
        16. 3.5.2.16 Program Counter (PC)
        17. 3.5.2.17 Program Status Register (PSR)
        18. 3.5.2.18 Priority Mask Register (PRIMASK)
        19. 3.5.2.19 Fault Mask Register (FAULTMASK)
        20. 3.5.2.20 Base Priority Mask Register (BASEPRI)
        21. 3.5.2.21 Control Register (CONTROL)
    6. 3.6 Instruction Set Summary
      1. 3.6.1 Arm® Cortex®-M4F Instructions
      2. 3.6.2 Load and Store Timings
      3. 3.6.3 Binary Compatibility With Other Cortex® Processors
    7. 3.7 Floating Point Unit (FPU)
      1. 3.7.1 About the FPU
      2. 3.7.2 FPU Functional Description
        1. 3.7.2.1 FPU Views of the Register Bank
        2. 3.7.2.2 Modes of Operation
          1. 3.7.2.2.1 Full-Compliance Mode
          2. 3.7.2.2.2 Flush-to-Zero Mode
          3. 3.7.2.2.3 Default NaN Mode
        3. 3.7.2.3 FPU Instruction Set
        4. 3.7.2.4 Compliance With the IEEE 754 Standard
        5. 3.7.2.5 Complete Implementation of the IEEE 754 Standard
        6. 3.7.2.6 IEEE 754 Standard Implementation Choices
          1. 3.7.2.6.1 NaN Handling
          2. 3.7.2.6.2 Comparisons
          3. 3.7.2.6.3 Underflow
        7. 3.7.2.7 Exceptions
      3. 3.7.3 FPU Programmers Model
        1. 3.7.3.1 Enabling the FPU
          1. 3.7.3.1.1 Enabling the FPU
    8. 3.8 Memory Protection Unit (MPU)
      1. 3.8.1 About the MPU
      2. 3.8.2 MPU Functional Description
      3. 3.8.3 MPU Programmers Model
    9. 3.9 Arm® Cortex®-M4F Processor Registers
      1. 3.9.1 CPU_DWT Registers
      2. 3.9.2 CPU_FPB Registers
      3. 3.9.3 CPU_ITM Registers
      4. 3.9.4 CPU_SCS Registers
      5. 3.9.5 CPU_TPIU Registers
  4. 4 Memory Map
    1. 4.1 Memory Map
  5. 5 Arm® Cortex®-M4F Peripherals
    1. 5.1 Arm® Cortex®-M4F Peripherals Introduction
    2. 5.2 Functional Description
      1. 5.2.1 SysTick
      2. 5.2.2 NVIC
        1. 5.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 5.2.2.2 Hardware and Software Control of Interrupts
      3. 5.2.3 SCB
      4. 5.2.4 ITM
      5. 5.2.5 FPB
      6. 5.2.6 TPIU
      7. 5.2.7 DWT
  6. 6 Interrupts and Events
    1. 6.1 Exception Model
      1. 6.1.1 Exception States
      2. 6.1.2 Exception Types
      3. 6.1.3 Exception Handlers
      4. 6.1.4 Vector Table
      5. 6.1.5 Exception Priorities
      6. 6.1.6 Interrupt Priority Grouping
      7. 6.1.7 Exception Entry and Return
        1. 6.1.7.1 Exception Entry
        2. 6.1.7.2 Exception Return
    2. 6.2 Fault Handling
      1. 6.2.1 Fault Types
      2. 6.2.2 Fault Escalation and Hard Faults
      3. 6.2.3 Fault Status Registers and Fault Address Registers
      4. 6.2.4 Lockup
    3. 6.3 Event Fabric
      1. 6.3.1 Introduction
      2. 6.3.2 Event Fabric Overview
        1. 6.3.2.1 Registers
    4. 6.4 AON Event Fabric
      1. 6.4.1 Common Input Event List
      2. 6.4.2 Event Subscribers
        1. 6.4.2.1 Wake-Up Controller (WUC)
        2. 6.4.2.2 Real-Time Clock
        3. 6.4.2.3 MCU Event Fabric
    5. 6.5 MCU Event Fabric
      1. 6.5.1 Common Input Event List
      2. 6.5.2 Event Subscribers
        1. 6.5.2.1 System CPU
        2. 6.5.2.2 NMI
        3. 6.5.2.3 Freeze
    6. 6.6 AON Events
    7. 6.7 Interrupts and Events Registers
      1. 6.7.1 AON_EVENT Registers
      2. 6.7.2 EVENT Registers
  7. 7 JTAG Interface
    1. 7.1  Top-Level Debug System
    2. 7.2  cJTAG
      1. 7.2.1 cJTAG Commands
        1. 7.2.1.1 Mandatory Commands
      2. 7.2.2 Programming Sequences
        1. 7.2.2.1 Opening Command Window
        2. 7.2.2.2 Changing to 4-Pin Mode
        3. 7.2.2.3 Close Command Window
    3. 7.3  ICEPick
      1. 7.3.1 Secondary TAPs
        1. 7.3.1.1 Slave DAP (CPU DAP)
        2. 7.3.1.2 Ordering Slave TAPs and DAPs
      2. 7.3.2 ICEPick Registers
        1. 7.3.2.1 IR Instructions
        2. 7.3.2.2 Data Shift Register
        3. 7.3.2.3 Instruction Register
        4. 7.3.2.4 Bypass Register
        5. 7.3.2.5 Device Identification Register
        6. 7.3.2.6 User Code Register
        7. 7.3.2.7 ICEPick Identification Register
        8. 7.3.2.8 Connect Register
      3. 7.3.3 Router Scan Chain
      4. 7.3.4 TAP Routing Registers
        1. 7.3.4.1 ICEPick Control Block
          1. 7.3.4.1.1 All0s Register
          2. 7.3.4.1.2 ICEPick Control Register
          3. 7.3.4.1.3 Linking Mode Register
        2. 7.3.4.2 Test TAP Linking Block
          1. 7.3.4.2.1 Secondary Test TAP Register
        3. 7.3.4.3 Debug TAP Linking Block
          1. 7.3.4.3.1 Secondary Debug TAP Register
    4. 7.4  ICEMelter
    5. 7.5  Serial Wire Viewer (SWV)
    6. 7.6  Halt In Boot (HIB)
    7. 7.7  Debug and Shutdown
    8. 7.8  Debug Features Supported Through WUC TAP
    9. 7.9  Profiler Register
    10. 7.10 Boundary Scan
  8. 8 Power, Reset, and Clock Management (PRCM)
    1. 8.1 Introduction
    2. 8.2 System CPU Mode
    3. 8.3 Supply System
      1. 8.3.1 Internal DC/DC Converter and Global LDO
    4. 8.4 Digital Power Partitioning
      1. 8.4.1 MCU_VD
        1. 8.4.1.1 MCU_VD Power Domains
      2. 8.4.2 AON_VD
        1. 8.4.2.1 AON_VD Power Domains
    5. 8.5 Clock Management
      1. 8.5.1 System Clocks
        1. 8.5.1.1 Controlling the Oscillators
      2. 8.5.2 Clocks in MCU_VD
        1. 8.5.2.1 Clock Gating
        2. 8.5.2.2 Scaler to GPTs
        3. 8.5.2.3 Scaler to WDT
      3. 8.5.3 Clocks in AON_VD
    6. 8.6 Power Modes
      1. 8.6.1 Start-Up State
      2. 8.6.2 Active Mode
      3. 8.6.3 Idle Mode
      4. 8.6.4 Standby Mode
      5. 8.6.5 Shutdown Mode
    7. 8.7 Reset
      1. 8.7.1 System Resets
        1. 8.7.1.1 Clock Loss Detection
        2. 8.7.1.2 Software-Initiated System Reset
        3. 8.7.1.3 Warm Reset Converted to System Reset
      2. 8.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 8.7.3 Reset of AON_VD
    8. 8.8 PRCM Registers
      1. 8.8.1 DDI_0_OSC Registers
      2. 8.8.2 PRCM Registers
      3. 8.8.3 AON_PMCTL Registers
  9. 9 Versatile Instruction Memory System (VIMS)
    1. 9.1 Introduction
    2. 9.2 VIMS Configurations
      1. 9.2.1 VIMS Modes
        1. 9.2.1.1 GPRAM Mode
        2. 9.2.1.2 Off Mode
        3. 9.2.1.3 Cache Mode
      2. 9.2.2 VIMS FLASH Line Buffers
      3. 9.2.3 VIMS Arbitration
      4. 9.2.4 VIMS Cache TAG Prefetch
    3. 9.3 VIMS Software Remarks
      1. 9.3.1 FLASH Program or Update
      2. 9.3.2 VIMS Retention
        1. 9.3.2.1 Mode 1
        2. 9.3.2.2 Mode 2
        3. 9.3.2.3 Mode 3
    4. 9.4 ROM
    5. 9.5 FLASH
      1. 9.5.1 FLASH Memory Protection
      2. 9.5.2 Memory Programming
      3. 9.5.3 FLASH Memory Programming
      4. 9.5.4 Power Management Requirements
    6. 9.6 ROM Functions
    7. 9.7 VIMS Registers
      1. 9.7.1 FLASH Registers
      2. 9.7.2 VIMS Registers
  10. 10SRAM
    1. 10.1 Introduction
    2. 10.2 Main Features
    3. 10.3 Data Retention
    4. 10.4 Parity and SRAM Error Support
    5. 10.5 SRAM Auto-Initialization
    6. 10.6 Parity Debug Behavior
    7. 10.7 SRAM Registers
      1. 10.7.1 SRAM_MMR Registers
      2. 10.7.2 SRAM Registers
  11. 11Bootloader
    1. 11.1 Bootloader Functionality
      1. 11.1.1 Bootloader Disabling
      2. 11.1.2 Bootloader Backdoor
    2. 11.2 Bootloader Interfaces
      1. 11.2.1 Packet Handling
        1. 11.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 11.2.2 Transport Layer
        1. 11.2.2.1 UART Transport
          1. 11.2.2.1.1 UART Baud Rate Automatic Detection
        2. 11.2.2.2 SSI Transport
      3. 11.2.3 Serial Bus Commands
        1. 11.2.3.1  COMMAND_PING
        2. 11.2.3.2  COMMAND_DOWNLOAD
        3. 11.2.3.3  COMMAND_SEND_DATA
        4. 11.2.3.4  COMMAND_SECTOR_ERASE
        5. 11.2.3.5  COMMAND_GET_STATUS
        6. 11.2.3.6  COMMAND_RESET
        7. 11.2.3.7  COMMAND_GET_CHIP_ID
        8. 11.2.3.8  COMMAND_CRC32
        9. 11.2.3.9  COMMAND_BANK_ERASE
        10. 11.2.3.10 COMMAND_MEMORY_READ
        11. 11.2.3.11 COMMAND_MEMORY_WRITE
        12. 11.2.3.12 COMMAND_SET_CCFG
        13. 11.2.3.13 COMMAND_DOWNLOAD_CRC
  12. 12Device Configuration
    1. 12.1 Customer Configuration (CCFG)
    2. 12.2 CCFG Registers
      1. 12.2.1 CCFG Registers
    3. 12.3 Factory Configuration (FCFG)
    4. 12.4 FCFG Registers
      1. 12.4.1 FCFG1 Registers
  13. 13Cryptography
    1. 13.1 AES and Hash Cryptoprocessor Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Debug Capabilities
      2. 13.2.2 Exception Handling
    3. 13.3 Power Management and Sleep Modes
    4. 13.4 Hardware Description
      1. 13.4.1 AHB Slave Bus
      2. 13.4.2 AHB Master Bus
      3. 13.4.3 Interrupts
    5. 13.5 Module Description
      1. 13.5.1 Introduction
      2. 13.5.2 Module Memory Map
      3. 13.5.3 DMA Controller
        1. 13.5.3.1 Internal Operation
        2. 13.5.3.2 Supported DMA Operations
      4. 13.5.4 Master Control and Select Module
        1. 13.5.4.1 Algorithm Select Register
          1. 13.5.4.1.1 Algorithm Select
        2. 13.5.4.2 Master PROT Enable
          1. 13.5.4.2.1 Master PROT-Privileged Access-Enable
        3. 13.5.4.3 Software Reset
      5. 13.5.5 AES Engine
        1. 13.5.5.1 Second Key Registers (Internal, But Clearable)
        2. 13.5.5.2 AES Initialization Vector (IV) Registers
        3. 13.5.5.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 13.5.5.4 Data Input and Output Registers
        5. 13.5.5.5 TAG Registers
      6. 13.5.6 Key Area Registers
        1. 13.5.6.1 Key Write Area Register
        2. 13.5.6.2 Key Written Area Register
        3. 13.5.6.3 Key Size Register
        4. 13.5.6.4 Key Store Read Area Register
        5. 13.5.6.5 Hash Engine
    6. 13.6 AES Module Performance
      1. 13.6.1 Introduction
      2. 13.6.2 Performance for DMA-Based Operations
    7. 13.7 Programming Guidelines
      1. 13.7.1 One-Time Initialization After a Reset
      2. 13.7.2 DMAC and Master Control
        1. 13.7.2.1 Regular Use
        2. 13.7.2.2 Interrupting DMA Transfers
        3. 13.7.2.3 Interrupts, Hardware, and Software Synchronization
      3. 13.7.3 Hashing
        1. 13.7.3.1 Data Format and Byte Order
        2. 13.7.3.2 Basic Hash With Data From DMA
          1. 13.7.3.2.1 New Hash Session With Digest Read Through Slave
          2. 13.7.3.2.2 New Hash Session With Digest to External Memory
          3. 13.7.3.2.3 Resumed Hash Session
        3. 13.7.3.3 HMAC
          1. 13.7.3.3.1 Secure HMAC
        4. 13.7.3.4 Alternative Basic Hash Where Data Originates From Slave Interface
          1. 13.7.3.4.1 New Hash Session
          2. 13.7.3.4.2 Resumed Hash Session
      4. 13.7.4 Encryption and Decryption
        1. 13.7.4.1 Data Format and Byte Order
        2. 13.7.4.2 Key Store
          1. 13.7.4.2.1 Load Keys From External Memory
        3. 13.7.4.3 Basic AES Modes
          1. 13.7.4.3.1 AES-ECB
          2. 13.7.4.3.2 AES-CBC
          3. 13.7.4.3.3 AES-CTR
          4. 13.7.4.3.4 Programming Sequence With DMA Data
        4. 13.7.4.4 CBC-MAC
          1. 13.7.4.4.1 Programming Sequence for CBC-MAC
        5. 13.7.4.5 AES-CCM
          1. 13.7.4.5.1 Programming Sequence for AES-CCM
        6. 13.7.4.6 AES-GCM
          1. 13.7.4.6.1 Programming Sequence for AES-GCM
      5. 13.7.5 Exceptions Handling
        1. 13.7.5.1 Soft Reset
        2. 13.7.5.2 External Port Errors
        3. 13.7.5.3 Key Store Errors
          1. 13.7.5.3.1 PKA Engine
          2. 13.7.5.3.2 Functional Description
            1. 13.7.5.3.2.1 Module Architecture
          3. 13.7.5.3.3 PKA RAM
            1. 13.7.5.3.3.1 PKCP Operations
            2. 13.7.5.3.3.2 Sequencer Operations
              1. 13.7.5.3.3.2.1 Modular Exponentiation Operations
              2. 13.7.5.3.3.2.2 Modular Inversion Operation
              3. 13.7.5.3.3.2.3 Performance
              4. 13.7.5.3.3.2.4 ECC Operations
              5. 13.7.5.3.3.2.5 Performance
              6. 13.7.5.3.3.2.6 ExpMod Performance
              7. 13.7.5.3.3.2.7 Modular Inversion Performance
              8. 13.7.5.3.3.2.8 ECC Operation Performance
            3. 13.7.5.3.3.3 Sequencer ROM Behavior and Interfaces
            4. 13.7.5.3.3.4 Register Configurations
            5. 13.7.5.3.3.5 Operation Sequence
    8. 13.8 Conventions and Compliances
      1. 13.8.1 Conventions Used in This Manual
        1. 13.8.1.1 Terminology
        2. 13.8.1.2 Formulas and Nomenclature
      2. 13.8.2 Compliance
    9. 13.9 Cryptography Registers
      1. 13.9.1 CRYPTO Registers
  14. 14I/O Controller (IOC)
    1. 14.1  Introduction
    2. 14.2  IOC Overview
    3. 14.3  I/O Mapping and Configuration
      1. 14.3.1 Basic I/O Mapping
      2. 14.3.2 Mapping AUXIOs to DIO Pins
      3. 14.3.3 Control External LNA/PA (Range Extender) With I/Os
      4. 14.3.4 Map the 32 kHz System Clock (LF Clock) to DIO
    4. 14.4  Edge Detection on DIO Pins
      1. 14.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT
    5. 14.5  Unused I/O Pins
    6. 14.6  GPIO
    7. 14.7  I/O Pin Capability
    8. 14.8  Peripheral PORTIDs
    9. 14.9  I/O Pins
      1. 14.9.1 Input/Output Modes
        1. 14.9.1.1 Physical Pin
        2. 14.9.1.2 Pin Configuration
    10. 14.10 IOC Registers
      1. 14.10.1 AON_IOC Registers
      2. 14.10.2 GPIO Registers
      3. 14.10.3 IOC Registers
  15. 15Micro Direct Memory Access (µDMA)
    1. 15.1 μDMA Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
    4. 15.4 Initialization and Configuration
      1. 15.4.1 Module Initialization
      2. 15.4.2 Configuring a Memory-to-Memory Transfer
        1. 15.4.2.1 Configure the Channel Attributes
        2. 15.4.2.2 Configure the Channel Control Structure
        3. 15.4.2.3 Start the Transfer
    5. 15.5 µDMA Registers
      1. 15.5.1 UDMA Registers
  16. 16Timers
    1. 16.1 General-Purpose Timers
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1 GPTM Reset Conditions
      2. 16.3.2 Timer Modes
        1. 16.3.2.1 One-Shot or Periodic Timer Mode
        2. 16.3.2.2 Input Edge-Count Mode
        3. 16.3.2.3 Input Edge-Time Mode
        4. 16.3.2.4 PWM Mode
        5. 16.3.2.5 Wait-for-Trigger Mode
      3. 16.3.3 Synchronizing GPT Blocks
      4. 16.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 16.4 Initialization and Configuration
      1. 16.4.1 One-Shot and Periodic Timer Modes
      2. 16.4.2 Input Edge-Count Mode
      3. 16.4.3 Input Edge-Timing Mode
      4. 16.4.4 PWM Mode
      5. 16.4.5 Producing DMA Trigger Events
    5. 16.5 GPTM Registers
      1. 16.5.1 GPT Registers
  17. 17Real-Time Clock (RTC)
    1. 17.1 Introduction
    2. 17.2 Functional Specifications
      1. 17.2.1 Functional Overview
      2. 17.2.2 Free-Running Counter
      3. 17.2.3 Channels
        1. 17.2.3.1 Capture and Compare
      4. 17.2.4 Events
    3. 17.3 RTC Register Information
      1. 17.3.1 Register Access
      2. 17.3.2 Entering Sleep and Wakeup From Sleep
      3. 17.3.3 AON_RTC:SYNC Register
    4. 17.4 RTC Registers
      1. 17.4.1 AON_RTC Registers
  18. 18Watchdog Timer (WDT)
    1. 18.1 Introduction
    2. 18.2 Functional Description
    3. 18.3 Initialization and Configuration
    4. 18.4 WDT Registers
      1. 18.4.1 WDT Registers
  19. 19True Random Number Generator (TRNG)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 TRNG Software Reset
    4. 19.4 Interrupt Requests
    5. 19.5 TRNG Operation Description
      1. 19.5.1 TRNG Shutdown
      2. 19.5.2 TRNG Alarms
      3. 19.5.3 TRNG Entropy
    6. 19.6 TRNG Low-Level Programing Guide
      1. 19.6.1 Initialization
        1. 19.6.1.1 Interfacing Modules
        2. 19.6.1.2 TRNG Main Sequence
        3. 19.6.1.3 TRNG Operating Modes
          1. 19.6.1.3.1 Polling Mode
          2. 19.6.1.3.2 Interrupt Mode
    7. 19.7 TRNG Registers
      1. 19.7.1 TRNG Registers
  20. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 AIODIO
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 SMPH
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPIM
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
              1. 20.4.7.2.5.1.1 Timer Period and Pulse Width Capture
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.2.1 Center-Aligned PWM Generation by Channel 0
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.3.1 Edge-Aligned PWM Generation by Channel 0
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 COMPA
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 COMPB
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference DAC
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 ISRC
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  21. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 BATMON Registers
      1. 21.3.1 AON_BATMON Registers
  22. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud-rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to DMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
      1. 22.7.1 UART Registers
  23. 23Synchronous Serial Interface (SSI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
        2. 23.4.2.2 Receive FIFO
      3. 23.4.3 Interrupts
      4. 23.4.4 Frame Formats
        1. 23.4.4.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.4.2 Motorola SPI Frame Format
          1. 23.4.4.2.1 SPO Clock Polarity Bit
          2. 23.4.4.2.2 SPH Phase-Control Bit
        3. 23.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
        4. 23.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
        5. 23.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
        6. 23.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
        7. 23.4.4.7 MICROWIRE Frame Format
    5. 23.5 DMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SSI Registers
      1. 23.7.1 SSI Registers
  24. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format With 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
      1. 24.5.1 I2C Registers
  25. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
      1. 25.9.1 I2S Registers
  26. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization With Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond With Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration (Depricated)
          19. 26.3.3.2.19 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          20. 26.3.3.2.20 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® low energy
      1. 26.6.1 Bluetooth® low energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® low energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® low energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Nonconnectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  27. 27Revision History

16.5.1 GPT Registers

Table 16-7 lists the memory-mapped registers for the GPT registers. All register offset addresses not listed in Table 16-7 should be considered as reserved locations and the register contents should not be modified.

Table 16-7 GPT Registers
OffsetAcronymRegister NameSection
0hCFGConfigurationCFG Register (Offset = 0h) [Reset = 00000000h]
4hTAMRTimer A ModeTAMR Register (Offset = 4h) [Reset = 00000000h]
8hTBMRTimer B ModeTBMR Register (Offset = 8h) [Reset = 00000000h]
ChCTLControlCTL Register (Offset = Ch) [Reset = 00000000h]
10hSYNCSynch RegisterSYNC Register (Offset = 10h) [Reset = 00000000h]
18hIMRInterrupt MaskIMR Register (Offset = 18h) [Reset = 00000000h]
1ChRISRaw Interrupt StatusRIS Register (Offset = 1Ch) [Reset = 00000000h]
20hMISMasked Interrupt StatusMIS Register (Offset = 20h) [Reset = 00000000h]
24hICLRInterrupt ClearICLR Register (Offset = 24h) [Reset = 00000000h]
28hTAILRTimer A Interval Load RegisterTAILR Register (Offset = 28h) [Reset = FFFFFFFFh]
2ChTBILRTimer B Interval Load RegisterTBILR Register (Offset = 2Ch) [Reset = 0000FFFFh]
30hTAMATCHRTimer A Match RegisterTAMATCHR Register (Offset = 30h) [Reset = FFFFFFFFh]
34hTBMATCHRTimer B Match RegisterTBMATCHR Register (Offset = 34h) [Reset = 0000FFFFh]
38hTAPRTimer A Pre-scaleTAPR Register (Offset = 38h) [Reset = 00000000h]
3ChTBPRTimer B Pre-scaleTBPR Register (Offset = 3Ch) [Reset = 00000000h]
40hTAPMRTimer A Pre-scale MatchTAPMR Register (Offset = 40h) [Reset = 00000000h]
44hTBPMRTimer B Pre-scale MatchTBPMR Register (Offset = 44h) [Reset = 00000000h]
48hTARTimer A RegisterTAR Register (Offset = 48h) [Reset = FFFFFFFFh]
4ChTBRTimer B RegisterTBR Register (Offset = 4Ch) [Reset = 0000FFFFh]
50hTAVTimer A ValueTAV Register (Offset = 50h) [Reset = FFFFFFFFh]
54hTBVTimer B ValueTBV Register (Offset = 54h) [Reset = 0000FFFFh]
5ChTAPSTimer A Pre-scale Snap-shotTAPS Register (Offset = 5Ch) [Reset = 00000000h]
60hTBPSTimer B Pre-scale Snap-shotTBPS Register (Offset = 60h) [Reset = 00000000h]
64hTAPVTimer A Pre-scale ValueTAPV Register (Offset = 64h) [Reset = 00000000h]
68hTBPVTimer B Pre-scale ValueTBPV Register (Offset = 68h) [Reset = 00000000h]
6ChDMAEVDMA EventDMAEV Register (Offset = 6Ch) [Reset = 00000000h]
FB0hVERSIONPeripheral VersionVERSION Register (Offset = FB0h) [Reset = 00000400h]
FB4hANDCCPCombined CCP OutputANDCCP Register (Offset = FB4h) [Reset = 00000000h]

Complex bit access types are encoded to fit into small table cells. Table 16-8 shows the codes that are used for access types in this section.

Table 16-8 GPT Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

16.5.1.1 CFG Register (Offset = 0h) [Reset = 00000000h]

CFG is shown in Figure 16-9 and described in Table 16-9.

Return to the Summary Table.

Configuration

Figure 16-9 CFG Register
313029282726252423222120191817161514131211109876543210
RESERVEDCFG
R-0hR/W-0h
Table 16-9 CFG Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CFGR/W0hGPT Configuration
0x2- 0x3 - Reserved
0x5- 0x7 - Reserved
0h = 32BIT_TIMER : 32-bit timer configuration
4h = 16BIT_TIMER : 16-bit timer configuration.
Configure for two 16-bit timers.
Also see TAMR.TAMR and TBMR.TBMR.

16.5.1.2 TAMR Register (Offset = 4h) [Reset = 00000000h]

TAMR is shown in Figure 16-10 and described in Table 16-10.

Return to the Summary Table.

Timer A Mode

Figure 16-10 TAMR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
TCACTTACINTDTAPLOTAMRSUTAPWMIETAILD
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TASNAPSTAWOTTAMIETACDIRTAAMSTACMTAMR
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 16-10 TAMR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-13TCACTR/W0hTimer Compare Action Select
0h = DIS_CMP : Disable compare operations
1h = Toggle State on Time-Out
2h = Clear CCP output pin on Time-Out
3h = Set CCP output pin on Time-Out
4h = Set CCP output pin immediately and toggle on Time-Out
5h = Clear CCP output pin immediately and toggle on Time-Out
6h = Set CCP output pin immediately and clear on Time-Out
7h = Clear CCP output pin immediately and set on Time-Out
12TACINTDR/W0hOne-Shot/Periodic Interrupt Disable
0h = Time-out interrupt function as normal
1h = Time-out interrupt are disabled
11TAPLOR/W0hGPTM Timer A PWM Legacy Operation
0 Legacy operation with CCP pin driven Low when the TAILR
register is reloaded after the timer reaches 0.
1 CCP is driven High when the TAILR register is reloaded after the timer reaches 0.
This bit is only valid in PWM mode.
0h = Legacy operation
1h = CCP output pin is set to 1 on time-out
10TAMRSUR/W0hTimer A Match Register Update mode

This bit defines when the TAMATCHR and TAPR registers are updated.
If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and TAPR are updated when the timer is enabled.
If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and TAPR are updated according to the configuration of this bit.
0h = Update TAMATCHR and TAPR, if used, on the next cycle.
1h = Update TAMATCHR and TAPR, if used, on the next time-out.
9TAPWMIER/W0hGPTM Timer A PWM Interrupt Enable
This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TAEVENT
In addition, when this bit is set and a capture event occurs, Timer A
automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit respectively.
0 Capture event interrupt is disabled.
1 Capture event interrupt is enabled.
This bit is only valid in PWM mode.
0h = Interrupt is disabled.
1h = Interrupt is enabled. This bit is only valid in PWM mode.
8TAILDR/W0hGPT Timer A PWM Interval Load Write
0h = Update the TAR register with the value in the TAILR register on the next clock cycle. If the pre-scaler is used, update the TAPS register with the value in the TAPR register on the next clock cycle.
1h = Update the TAR register with the value in the TAILR register on the next timeout. If the prescaler is used, update the TAPS register with the value in the TAPR register on the next timeout.
7TASNAPSR/W0hGPT Timer A Snap-Shot Mode
0h = Snap-shot mode is disabled.
1h = If Timer A is configured in the periodic mode, the actual free-running value of Timer A is loaded at the time-out event into the GPT Timer A (TAR) register.
6TAWOTR/W0hGPT Timer A Wait-On-Trigger
0h = Timer A begins counting as soon as it is enabled.
1h = If Timer A is enabled (CTL.TAEN = 1), Timer A does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain. This bit must be clear for GPT Module 0, Timer A. This function is valid for one-shot, periodic, and PWM modes
5TAMIER/W0hGPT Timer A Match Interrupt Enable
0h = The match interrupt is disabled for match events. Additionally, output triggers on match events are prevented.
1h = An interrupt is generated when the match value in TAMATCHR is reached in the one-shot and periodic modes.
4TACDIRR/W0hGPT Timer A Count Direction
0h = DOWN : The timer counts down.
1h = UP : The timer counts up. When counting up, the timer starts from a value of 0x0.
3TAAMSR/W0hGPT Timer A Alternate Mode
Note: To enable PWM mode, you must also clear TACM and then configure TAMR field to 0x2.
0h = Capture/Compare mode is enabled.
1h = PWM mode is enabled
2TACMR/W0hGPT Timer A Capture Mode
0h = EDGCNT : Edge-Count mode
1h = EDGTIME : Edge-Time mode
1-0TAMRR/W0hGPT Timer A Mode
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register
1h = One-Shot Timer mode
2h = Periodic Timer mode
3h = Capture mode

16.5.1.3 TBMR Register (Offset = 8h) [Reset = 00000000h]

TBMR is shown in Figure 16-11 and described in Table 16-11.

Return to the Summary Table.

Timer B Mode

Figure 16-11 TBMR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
TCACTTBCINTDTBPLOTBMRSUTBPWMIETBILD
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TBSNAPSTBWOTTBMIETBCDIRTBAMSTBCMTBMR
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 16-11 TBMR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-13TCACTR/W0hTimer Compare Action Select
0h = DIS_CMP : Disable compare operations
1h = Toggle State on Time-Out
2h = Clear CCP output pin on Time-Out
3h = Set CCP output pin on Time-Out
4h = Set CCP output pin immediately and toggle on Time-Out
5h = Clear CCP output pin immediately and toggle on Time-Out
6h = Set CCP output pin immediately and clear on Time-Out
7h = Clear CCP output pin immediately and set on Time-Out
12TBCINTDR/W0hOne-Shot/Periodic Interrupt Mode
0h = Normal Time-Out Interrupt
1h = Mask Time-Out Interrupt
11TBPLOR/W0hGPTM Timer B PWM Legacy Operation
0 Legacy operation with CCP pin driven Low when the TBILR
register is reloaded after the timer reaches 0.
1 CCP is driven High when the TBILR register is reloaded after the timer reaches 0.
This bit is only valid in PWM mode.
0h = Legacy operation
1h = CCP output pin is set to 1 on time-out
10TBMRSUR/W0hTimer B Match Register Update mode

This bit defines when the TBMATCHR and TBPR registers are updated
If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR and TBPR are updated when the timer is enabled.
If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR and TBPR are updated according to the configuration of this bit.
0h = Update TBMATCHR and TBPR, if used, on the next cycle.
1h = Update TBMATCHR and TBPR, if used, on the next time-out.
9TBPWMIER/W0hGPTM Timer B PWM Interrupt Enable
This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TBEVENT
In addition, when this bit is set and a capture event occurs, Timer A
automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit respectively.
0 Capture event interrupt is disabled.
1 Capture event interrupt is enabled.
This bit is only valid in PWM mode.
0h = Interrupt is disabled.
1h = Interrupt is enabled. This bit is only valid in PWM mode.
8TBILDR/W0hGPT Timer B PWM Interval Load Write
0h = Update the TBR register with the value in the TBILR register on the next clock cycle. If the pre-scaler is used, update the TBPS register with the value in the TBPR register on the next clock cycle.
1h = Update the TBR register with the value in the TBILR register on the next timeout. If the prescaler is used, update the TBPS register with the value in the TBPR register on the next timeout.
7TBSNAPSR/W0hGPT Timer B Snap-Shot Mode
0h = Snap-shot mode is disabled.
1h = If Timer B is configured in the periodic mode
6TBWOTR/W0hGPT Timer B Wait-On-Trigger
0h = Timer B begins counting as soon as it is enabled.
1h = If Timer B is enabled (CTL.TBEN is set), Timer B does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain. This function is valid for one-shot, periodic, and PWM modes
5TBMIER/W0hGPT Timer B Match Interrupt Enable.
0h = The match interrupt is disabled for match events. Additionally, output triggers on match events are prevented.
1h = An interrupt is generated when the match value in the TBMATCHR register is reached in the one-shot and periodic modes.
4TBCDIRR/W0hGPT Timer B Count Direction
0h = DOWN : The timer counts down.
1h = UP : The timer counts up. When counting up, the timer starts from a value of 0x0.
3TBAMSR/W0hGPT Timer B Alternate Mode
Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR field to 0x2.
0h = Capture/Compare mode is enabled.
1h = PWM mode is enabled
2TBCMR/W0hGPT Timer B Capture Mode
0h = EDGCNT : Edge-Count mode
1h = EDGTIME : Edge-Time mode
1-0TBMRR/W0hGPT Timer B Mode
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register
1h = One-Shot Timer mode
2h = Periodic Timer mode
3h = Capture mode

16.5.1.4 CTL Register (Offset = Ch) [Reset = 00000000h]

CTL is shown in Figure 16-12 and described in Table 16-12.

Return to the Summary Table.

Control

Figure 16-12 CTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTBPWMLRESERVEDTBEVENTTBSTALLTBEN
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDTAPWMLRESERVEDTAEVENTTASTALLTAEN
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 16-12 CTL Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hReserved
14TBPWMLR/W0hGPT Timer B PWM Output Level
0: Output is unaffected.
1: Output is inverted.
0h = Not inverted
1h = Inverted
13-12RESERVEDR0hReserved
11-10TBEVENTR/W0hGPT Timer B Event Mode
The values in this register are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
Note: If PWM output inversion is enabled, edge detection interrupt
behavior is reversed. Thus, if a positive-edge interrupt trigger
has been set and the PWM inversion generates a postive
edge, no event-trigger interrupt asserts. Instead, the interrupt
is generated on the negative edge of the PWM signal.
0h = Positive edge
1h = Negative edge
3h = Both edges
9TBSTALLR/W0hGPT Timer B Stall Enable
0h = Timer B continues counting while the processor is halted by the debugger.
1h = Timer B freezes counting while the processor is halted by the debugger.
8TBENR/W0hGPT Timer B Enable
0h = Timer B is disabled.
1h = Timer B is enabled and begins counting or the capture logic is enabled based on CFG register.
7RESERVEDR0hReserved
6TAPWMLR/W0hGPT Timer A PWM Output Level
0h = Not inverted
1h = Inverted
5-4RESERVEDR0hReserved
3-2TAEVENTR/W0hGPT Timer A Event Mode
The values in this register are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
Note: If PWM output inversion is enabled, edge detection interrupt
behavior is reversed. Thus, if a positive-edge interrupt trigger
has been set and the PWM inversion generates a postive
edge, no event-trigger interrupt asserts. Instead, the interrupt
is generated on the negative edge of the PWM signal.
0h = Positive edge
1h = Negative edge
3h = Both edges
1TASTALLR/W0hGPT Timer A Stall Enable
0h = Timer A continues counting while the processor is halted by the debugger.
1h = Timer A freezes counting while the processor is halted by the debugger.
0TAENR/W0hGPT Timer A Enable
0h = Timer A is disabled.
1h = Timer A is enabled and begins counting or the capture logic is enabled based on the CFG register.

16.5.1.5 SYNC Register (Offset = 10h) [Reset = 00000000h]

SYNC is shown in Figure 16-13 and described in Table 16-13.

Return to the Summary Table.

Synch Register

Figure 16-13 SYNC Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSYNC3SYNC2SYNC1SYNC0
R-0hW-0hW-0hW-0hW-0h
Table 16-13 SYNC Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-6SYNC3W0hSynchronize GPT Timer 3.
0h = No Sync. GPT3 is not affected.
1h = A timeout event for Timer A of GPT3 is triggered
2h = A timeout event for Timer B of GPT3 is triggered
3h = A timeout event for both Timer A and Timer B of GPT3 is triggered
5-4SYNC2W0hSynchronize GPT Timer 2.
0h = No Sync. GPT2 is not affected.
1h = A timeout event for Timer A of GPT2 is triggered
2h = A timeout event for Timer B of GPT2 is triggered
3h = A timeout event for both Timer A and Timer B of GPT2 is triggered
3-2SYNC1W0hSynchronize GPT Timer 1
0h = No Sync. GPT1 is not affected.
1h = A timeout event for Timer A of GPT1 is triggered
2h = A timeout event for Timer B of GPT1 is triggered
3h = A timeout event for both Timer A and Timer B of GPT1 is triggered
1-0SYNC0W0hSynchronize GPT Timer 0
0h = No Sync. GPT0 is not affected.
1h = A timeout event for Timer A of GPT0 is triggered
2h = A timeout event for Timer B of GPT0 is triggered
3h = A timeout event for both Timer A and Timer B of GPT0 is triggered

16.5.1.6 IMR Register (Offset = 18h) [Reset = 00000000h]

IMR is shown in Figure 16-14 and described in Table 16-14.

Return to the Summary Table.

Interrupt Mask
This register is used to enable the interrupts.
Associated registers:
RIS, MIS, ICLR

Figure 16-14 IMR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDMABIMRESERVEDTBMIMCBEIMCBMIMTBTOIM
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDDMAAIMTAMIMRESERVEDCAEIMCAMIMTATOIM
R-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 16-14 IMR Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13DMABIMR/W0hEnabling this bit will make the RIS.DMABRIS interrupt propagate to MIS.DMABMIS
0h = Disable Interrupt
1h = Enable Interrupt
12RESERVEDR0hReserved
11TBMIMR/W0hEnabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS
0h = Disable Interrupt
1h = Enable Interrupt
10CBEIMR/W0hEnabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS
0h = Disable Interrupt
1h = Enable Interrupt
9CBMIMR/W0hEnabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS
0h = Disable Interrupt
1h = Enable Interrupt
8TBTOIMR/W0hEnabling this bit will make the RIS.TBTORIS interrupt propagate to MIS.TBTOMIS
0h = Disable Interrupt
1h = Enable Interrupt
7-6RESERVEDR0hReserved
5DMAAIMR/W0hEnabling this bit will make the RIS.DMAARIS interrupt propagate to MIS.DMAAMIS
0h = Disable Interrupt
1h = Enable Interrupt
4TAMIMR/W0hEnabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS
0h = Disable Interrupt
1h = Enable Interrupt
3RESERVEDR0hReserved
2CAEIMR/W0hEnabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS
0h = Disable Interrupt
1h = Enable Interrupt
1CAMIMR/W0hEnabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS
0h = Disable Interrupt
1h = Enable Interrupt
0TATOIMR/W0hEnabling this bit will make the RIS.TATORIS interrupt propagate to MIS.TATOMIS
0h = Disable Interrupt
1h = Enable Interrupt

16.5.1.7 RIS Register (Offset = 1Ch) [Reset = 00000000h]

RIS is shown in Figure 16-15 and described in Table 16-15.

Return to the Summary Table.

Raw Interrupt Status
Associated registers:
IMR, MIS, ICLR

Figure 16-15 RIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDMABRISRESERVEDTBMRISCBERISCBMRISTBTORIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDDMAARISTAMRISRESERVEDCAERISCAMRISTATORIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 16-15 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13DMABRISR0hGPT Timer B DMA Done Raw Interrupt Status
0: Transfer has not completed
1: Transfer has completed
12RESERVEDR0hReserved
11TBMRISR0hGPT Timer B Match Raw Interrupt
0: The match value has not been reached
1: The match value is reached.
TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR have been reached when configured in one-shot or periodic mode.
10CBERISR0hGPT Timer B Capture Mode Event Raw Interrupt
0: The event has not occured.
1: The event has occured.
This interrupt asserts when the subtimer is configured in Input Edge-Time mode
9CBMRISR0hGPT Timer B Capture Mode Match Raw Interrupt
0: The capture mode match for Timer B has not occurred.
1: A capture mode match has occurred for Timer B. This interrupt
asserts when the values in the TBR and TBPR
match the values in the TBMATCHR and TBPMR
when configured in Input Edge-Time mode.
This bit is cleared by writing a 1 to the ICLR.CBMCINT bit.
8TBTORISR0hGPT Timer B Time-out Raw Interrupt
0: Timer B has not timed out
1: Timer B has timed out.
This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TBILR, depending on the count direction.
7-6RESERVEDR0hReserved
5DMAARISR0hGPT Timer A DMA Done Raw Interrupt Status
0: Transfer has not completed
1: Transfer has completed
4TAMRISR0hGPT Timer A Match Raw Interrupt
0: The match value has not been reached
1: The match value is reached.
TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR have been reached when configured in one-shot or periodic mode.
3RESERVEDR0hReserved
2CAERISR0hGPT Timer A Capture Mode Event Raw Interrupt
0: The event has not occured.
1: The event has occured.
This interrupt asserts when the subtimer is configured in Input Edge-Time mode
1CAMRISR0hGPT Timer A Capture Mode Match Raw Interrupt
0: The capture mode match for Timer A has not occurred.
1: A capture mode match has occurred for Timer A. This interrupt
asserts when the values in the TAR and TAPR
match the values in the TAMATCHR and TAPMR
when configured in Input Edge-Time mode.
This bit is cleared by writing a 1 to the ICLR.CAMCINT bit.
0TATORISR0hGPT Timer A Time-out Raw Interrupt
0: Timer A has not timed out
1: Timer A has timed out.
This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TAILR, depending on the count direction.

16.5.1.8 MIS Register (Offset = 20h) [Reset = 00000000h]

MIS is shown in Figure 16-16 and described in Table 16-16.

Return to the Summary Table.

Masked Interrupt Status
Values are result of bitwise AND operation between RIS and IMR
Assosciated clear register: ICLR

Figure 16-16 MIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDMABMISRESERVEDTBMMISCBEMISCBMMISTBTOMIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDDMAAMISTAMMISRESERVEDCAEMISCAMMISTATOMIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 16-16 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13DMABMISR0h0: No interrupt or interrupt not enabled
1: RIS.DMABRIS = 1 && IMR.DMABIM = 1
12RESERVEDR0hReserved
11TBMMISR0h0: No interrupt or interrupt not enabled
1: RIS.TBMRIS = 1 && IMR.TBMIM = 1
10CBEMISR0h0: No interrupt or interrupt not enabled
1: RIS.CBERIS = 1 && IMR.CBEIM = 1
9CBMMISR0h0: No interrupt or interrupt not enabled
1: RIS.CBMRIS = 1 && IMR.CBMIM = 1
8TBTOMISR0h0: No interrupt or interrupt not enabled
1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1
7-6RESERVEDR0hReserved
5DMAAMISR0h0: No interrupt or interrupt not enabled
1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1
4TAMMISR0h0: No interrupt or interrupt not enabled
1: RIS.TAMRIS = 1 && IMR.TAMIM = 1
3RESERVEDR0hReserved
2CAEMISR0h0: No interrupt or interrupt not enabled
1: RIS.CAERIS = 1 && IMR.CAEIM = 1
1CAMMISR0h0: No interrupt or interrupt not enabled
1: RIS.CAMRIS = 1 && IMR.CAMIM = 1
0TATOMISR0h0: No interrupt or interrupt not enabled
1: RIS.TATORIS = 1 && IMR.TATOIM = 1

16.5.1.9 ICLR Register (Offset = 24h) [Reset = 00000000h]

ICLR is shown in Figure 16-17 and described in Table 16-17.

Return to the Summary Table.

Interrupt Clear
This register is used to clear status bits in the RIS and MIS registers

Figure 16-17 ICLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDMABINTRESERVEDTBMCINTCBECINTCBMCINTTBTOCINT
R-0hR/W1C-0hR-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
RESERVEDDMAAINTTAMCINTRESERVEDCAECINTCAMCINTTATOCINT
R-0hR/W1C-0hR/W1C-0hR-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 16-17 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13DMABINTR/W1C0h0: Do nothing.
1: Clear RIS.DMABRIS and MIS.DMABMIS
12RESERVEDR0hReserved
11TBMCINTR/W1C0h0: Do nothing.
1: Clear RIS.TBMRIS and MIS.TBMMIS
10CBECINTR/W1C0h0: Do nothing.
1: Clear RIS.CBERIS and MIS.CBEMIS
9CBMCINTR/W1C0h0: Do nothing.
1: Clear RIS.CBMRIS and MIS.CBMMIS
8TBTOCINTR/W1C0h0: Do nothing.
1: Clear RIS.TBTORIS and MIS.TBTOMIS
7-6RESERVEDR0hReserved
5DMAAINTR/W1C0h0: Do nothing.
1: Clear RIS.DMAARIS and MIS.DMAAMIS
4TAMCINTR/W1C0h0: Do nothing.
1: Clear RIS.TAMRIS and MIS.TAMMIS
3RESERVEDR0hReserved
2CAECINTR/W1C0h0: Do nothing.
1: Clear RIS.CAERIS and MIS.CAEMIS
1CAMCINTR/W1C0h0: Do nothing.
1: Clear RIS.CAMRIS and MIS.CAMMIS
0TATOCINTR/W1C0h0: Do nothing.
1: Clear RIS.TATORIS and MIS.TATOMIS

16.5.1.10 TAILR Register (Offset = 28h) [Reset = FFFFFFFFh]

TAILR is shown in Figure 16-18 and described in Table 16-18.

Return to the Summary Table.

Timer A Interval Load Register

Figure 16-18 TAILR Register
313029282726252423222120191817161514131211109876543210
TAILR
R/W-FFFFFFFFh
Table 16-18 TAILR Register Field Descriptions
BitFieldTypeResetDescription
31-0TAILRR/WFFFFFFFFhGPT Timer A Interval Load Register
Writing this field loads the counter for Timer A. A read returns the current value of TAILR.

16.5.1.11 TBILR Register (Offset = 2Ch) [Reset = 0000FFFFh]

TBILR is shown in Figure 16-19 and described in Table 16-19.

Return to the Summary Table.

Timer B Interval Load Register

Figure 16-19 TBILR Register
313029282726252423222120191817161514131211109876543210
TBILR
R/W-FFFFh
Table 16-19 TBILR Register Field Descriptions
BitFieldTypeResetDescription
31-0TBILRR/WFFFFhGPT Timer B Interval Load Register
Writing this field loads the counter for Timer B. A read returns the current value of TBILR.

16.5.1.12 TAMATCHR Register (Offset = 30h) [Reset = FFFFFFFFh]

TAMATCHR is shown in Figure 16-20 and described in Table 16-20.

Return to the Summary Table.

Timer A Match Register
Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode.
In Edge-Count mode, this register along with TAILR, determines how many edge events are counted.
The total number of edge events counted is equal to the value in TAILR minus this value.
Note that in edge-count mode, when executing an up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and this register.
In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM signal.
When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit register. (The upper 16-bits correspond to the contents TBMATCHR).
In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBMATCHR.
Note : This register is updated internally (takes effect) based on TAMR.TAMRSU

Figure 16-20 TAMATCHR Register
313029282726252423222120191817161514131211109876543210
TAMATCHR
R/W-FFFFFFFFh
Table 16-20 TAMATCHR Register Field Descriptions
BitFieldTypeResetDescription
31-0TAMATCHRR/WFFFFFFFFhGPT Timer A Match Register

16.5.1.13 TBMATCHR Register (Offset = 34h) [Reset = 0000FFFFh]

TBMATCHR is shown in Figure 16-21 and described in Table 16-21.

Return to the Summary Table.

Timer B Match Register
When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR.
Reads from this register return the current match value of Timer B and writes are ignored.
In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases.
Note : This register is updated internally (takes effect) based on TBMR.TBMRSU

Figure 16-21 TBMATCHR Register
313029282726252423222120191817161514131211109876543210
RESERVEDTBMATCHR
R-0hR/W-FFFFh
Table 16-21 TBMATCHR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0TBMATCHRR/WFFFFhGPT Timer B Match Register

16.5.1.14 TAPR Register (Offset = 38h) [Reset = 00000000h]

TAPR is shown in Figure 16-22 and described in Table 16-22.

Return to the Summary Table.

Timer A Pre-scale
This register allows software to extend the range of the timers when they are used individually.
When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter.
When acting as a true prescaler, the prescaler counts down to 0 before the value in TAR and TAV registers are incremented.
In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT.

Figure 16-22 TAPR Register
313029282726252423222120191817161514131211109876543210
RESERVEDTAPSR
R-0hR/W-0h
Table 16-22 TAPR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0TAPSRR/W0hTimer A Pre-scale.
Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is:
0: Prescaler ratio = 1
1: Prescaler ratio = 2
2: Prescaler ratio = 3
...
255: Prescaler ratio = 256

16.5.1.15 TBPR Register (Offset = 3Ch) [Reset = 00000000h]

TBPR is shown in Figure 16-23 and described in Table 16-23.

Return to the Summary Table.

Timer B Pre-scale
This register allows software to extend the range of the timers when they are used individually.
When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter.
When acting as a true prescaler, the prescaler counts down to 0 before the value in TBR and TBV registers are incremented.
In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT.

Figure 16-23 TBPR Register
313029282726252423222120191817161514131211109876543210
RESERVEDTBPSR
R-0hR/W-0h
Table 16-23 TBPR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0TBPSRR/W0hTimer B Pre-scale.
Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is:
0: Prescaler ratio = 1
1: Prescaler ratio = 2
2: Prescaler ratio = 3
...
255: Prescaler ratio = 256

16.5.1.16 TAPMR Register (Offset = 40h) [Reset = 00000000h]

TAPMR is shown in Figure 16-24 and described in Table 16-24.

Return to the Summary Table.

Timer A Pre-scale Match
This register allows software to extend the range of the TAMATCHR when used individually.

Figure 16-24 TAPMR Register
313029282726252423222120191817161514131211109876543210
RESERVEDTAPSMR
R-0hR/W-0h
Table 16-24 TAPMR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0TAPSMRR/W0hGPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16.

16.5.1.17 TBPMR Register (Offset = 44h) [Reset = 00000000h]

TBPMR is shown in Figure 16-25 and described in Table 16-25.

Return to the Summary Table.

Timer B Pre-scale Match
This register allows software to extend the range of the TBMATCHR when used individually.

Figure 16-25 TBPMR Register
313029282726252423222120191817161514131211109876543210
RESERVEDTBPSMR
R-0hR/W-0h
Table 16-25 TBPMR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0TBPSMRR/W0hGPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits 23 to 16.

16.5.1.18 TAR Register (Offset = 48h) [Reset = FFFFFFFFh]

TAR is shown in Figure 16-26 and described in Table 16-26.

Return to the Summary Table.

Timer A Register
This register shows the current value of the Timer A counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that
have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place.
When a GPT is configured to one of the 32-bit modes, this register appears as a 32-bit register (the upper 16-bits correspond to the contents of the Timer B (TBR) register). In
the16-bit Input Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count. Bits
31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the TAV register. To read the value of the prescalar in periodic snapshot
mode, read the Timer A Prescale Snapshot (TAPS) register.

Figure 16-26 TAR Register
313029282726252423222120191817161514131211109876543210
TAR
R-FFFFFFFFh
Table 16-26 TAR Register Field Descriptions
BitFieldTypeResetDescription
31-0TARRFFFFFFFFhGPT Timer A Register
Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAILR register either on the next cycle or on the next timeout.
A read returns the current value of the Timer A Count Register, in all cases except for Input Edge count and Timer modes.
In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place.

16.5.1.19 TBR Register (Offset = 4Ch) [Reset = 0000FFFFh]

TBR is shown in Figure 16-27 and described in Table 16-27.

Return to the Summary Table.

Timer B Register
This register shows the current value of the Timer B counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that
have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place.
When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the TAR register. Reads from this register return the current
value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler in Input Edge Count, Input Edge Time, and PWM modes, which is the
upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the TBV register. To read the value of the
prescalar in periodic snapshot mode, read the Timer B Prescale Snapshot (TBPS) register.

Figure 16-27 TBR Register
313029282726252423222120191817161514131211109876543210
TBR
R-FFFFh
Table 16-27 TBR Register Field Descriptions
BitFieldTypeResetDescription
31-0TBRRFFFFhGPT Timer B Register
Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBILR register either on the next cycle or on the next timeout.
A read returns the current value of the Timer B Count Register, in all cases except for Input Edge count and Timer modes.
In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place.

16.5.1.20 TAV Register (Offset = 50h) [Reset = FFFFFFFFh]

TAV is shown in Figure 16-28 and described in Table 16-28.

Return to the Summary Table.

Timer A Value
When read, this register shows the current, free-running value of Timer A in all modes. Softwarecan use this value to determine the time elapsed between an interrupt and the ISR entry when using
the snapshot feature with the periodic operating mode. When written, the value written into this register is loaded into the TAR register on the next clock cycle.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, this register appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Value (TBV) register). In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic
down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0.

Figure 16-28 TAV Register
313029282726252423222120191817161514131211109876543210
TAV
R/W-FFFFFFFFh
Table 16-28 TAV Register Field Descriptions
BitFieldTypeResetDescription
31-0TAVR/WFFFFFFFFhGPT Timer A Register
A read returns the current, free-running value of Timer A in all modes.
When written, the value written into this register is loaded into the
TAR register on the next clock cycle.
Note: In 16-bit mode, only the lower 16-bits of this
register can be written with a new value. Writes to the prescaler bits have no effect

16.5.1.21 TBV Register (Offset = 54h) [Reset = 0000FFFFh]

TBV is shown in Figure 16-29 and described in Table 16-29.

Return to the Summary Table.

Timer B Value
When read, this register shows the current, free-running value of Timer B in all modes. Software can use this value to determine the time elapsed between an interrupt and the ISR entry. When
written, the value written into this register is loaded into the TBR register on the next clock cycle.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the TAV register. Reads from this register return
the current free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of
the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes.
In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0.

Figure 16-29 TBV Register
313029282726252423222120191817161514131211109876543210
TBV
R/W-FFFFh
Table 16-29 TBV Register Field Descriptions
BitFieldTypeResetDescription
31-0TBVR/WFFFFhGPT Timer B Register
A read returns the current, free-running value of Timer B in all modes.
When written, the value written into this register is loaded into the
TBR register on the next clock cycle.
Note: In 16-bit mode, only the lower 16-bits of this
register can be written with a new value. Writes to the prescaler bits have no effect

16.5.1.22 TAPS Register (Offset = 5Ch) [Reset = 00000000h]

TAPS is shown in Figure 16-30 and described in Table 16-30.

Return to the Summary Table.

Timer A Pre-scale Snap-shot
Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAPR register either on the next cycle or on the next timeout.
This register shows the current value of the Timer A pre-scaler in the 16-bit mode.

Figure 16-30 TAPS Register
313029282726252423222120191817161514131211109876543210
RESERVEDPSS
R-0hR-0h
Table 16-30 TAPS Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0PSSR0hGPT Timer A Pre-scaler

16.5.1.23 TBPS Register (Offset = 60h) [Reset = 00000000h]

TBPS is shown in Figure 16-31 and described in Table 16-31.

Return to the Summary Table.

Timer B Pre-scale Snap-shot
Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBPR register either on the next cycle or on the next timeout.
This register shows the current value of the Timer B pre-scaler in the 16-bit mode.

Figure 16-31 TBPS Register
313029282726252423222120191817161514131211109876543210
RESERVEDPSS
R-0hR-0h
Table 16-31 TBPS Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0PSSR0hGPT Timer B Pre-scaler

16.5.1.24 TAPV Register (Offset = 64h) [Reset = 00000000h]

TAPV is shown in Figure 16-32 and described in Table 16-32.

Return to the Summary Table.

Timer A Pre-scale Value
This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode.

Figure 16-32 TAPV Register
313029282726252423222120191817161514131211109876543210
RESERVEDPSV
R-0hR-0h
Table 16-32 TAPV Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0PSVR0hGPT Timer A Pre-scaler Value

16.5.1.25 TBPV Register (Offset = 68h) [Reset = 00000000h]

TBPV is shown in Figure 16-33 and described in Table 16-33.

Return to the Summary Table.

Timer B Pre-scale Value
This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode.

Figure 16-33 TBPV Register
313029282726252423222120191817161514131211109876543210
RESERVEDPSV
R-0hR-0h
Table 16-33 TBPV Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0PSVR0hGPT Timer B Pre-scaler Value

16.5.1.26 DMAEV Register (Offset = 6Ch) [Reset = 00000000h]

DMAEV is shown in Figure 16-34 and described in Table 16-34.

Return to the Summary Table.

DMA Event
This register allows software to enable/disable GPT DMA trigger events.

Figure 16-34 DMAEV Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTBMDMAENCBEDMAENCBMDMAENTBTODMAEN
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDTAMDMAENRESERVEDCAEDMAENCAMDMAENTATODMAEN
R/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 16-34 DMAEV Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hSoftware should not rely on the value of a reserved field. Writing any other value may result in undefined behavior.
11TBMDMAENR/W0hGPT Timer B Match DMA Trigger Enable
10CBEDMAENR/W0hGPT Timer B Capture Event DMA Trigger Enable
9CBMDMAENR/W0hGPT Timer B Capture Match DMA Trigger Enable
8TBTODMAENR/W0hGPT Timer B Time-Out DMA Trigger Enable
7-5RESERVEDR/W0hSoftware should not rely on the value of a reserved field. Writing any other value may result in undefined behavior.
4TAMDMAENR/W0hGPT Timer A Match DMA Trigger Enable
3RESERVEDR0hReserved
2CAEDMAENR/W0hGPT Timer A Capture Event DMA Trigger Enable
1CAMDMAENR/W0hGPT Timer A Capture Match DMA Trigger Enable
0TATODMAENR/W0hGPT Timer A Time-Out DMA Trigger Enable

16.5.1.27 VERSION Register (Offset = FB0h) [Reset = 00000400h]

VERSION is shown in Figure 16-35 and described in Table 16-35.

Return to the Summary Table.

Peripheral Version
This register provides information regarding the GPT version

Figure 16-35 VERSION Register
313029282726252423222120191817161514131211109876543210
VERSION
R-400h
Table 16-35 VERSION Register Field Descriptions
BitFieldTypeResetDescription
31-0VERSIONR400hTimer Revision.

16.5.1.28 ANDCCP Register (Offset = FB4h) [Reset = 00000000h]

ANDCCP is shown in Figure 16-36 and described in Table 16-36.

Return to the Summary Table.

Combined CCP Output
This register is used to logically AND CCP output pairs for each timer

Figure 16-36 ANDCCP Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDLD_TO_ENCCP_AND_EN
R-0hR/W-0hR/W-0h
Table 16-36 ANDCCP Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1LD_TO_ENR/W0hPWM assertion would happen at timeout
0: PWM assertion happens when counter matches load value
1: PWM assertion happens at timeout of the counter
0CCP_AND_ENR/W0hEnables AND operation of the CCP outputs for timers A and B.
0 : PWM outputs of Timer A and Timer B are the internal generated PWM signals of the respective timers.
1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM signals and Timer B PWM ouput is Timer B PWM signal only.