홈 마이크로컨트롤러(MCU) 및 프로세서 마이크로프로세서 및 DSP 멀티미디어 및 산업용 네트워킹 SoC
홈
마이크로컨트롤러(MCU) 및 프로세서
마이크로프로세서 및 DSP
멀티미디어 및 산업용 네트워킹 SoC

AM62P-Q1

활성

고급 3D 그래픽, 4K 비디오 코덱 및 임베디드 안전을 지원하는 오토모티브 디스플레이 SoC

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AM62P-Q1

활성
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제품 상세 정보

CPU 2 Arm Cortex-A53, 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 DSI, MIPI DPI, OLDI Protocols Ethernet, TSN Hardware accelerators CPU only, Video decode accelerator, Video encode accelerator Features General purpose Operating system Android, Linux Security Secure boot TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution TPS65224-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled Yes
CPU 2 Arm Cortex-A53, 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 DSI, MIPI DPI, OLDI Protocols Ethernet, TSN Hardware accelerators CPU only, Video decode accelerator, Video encode accelerator Features General purpose Operating system Android, Linux Security Secure boot TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution TPS65224-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled Yes
FCBGA (AMH) 466 289 mm² 17 x 17

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories

Multimedia:

  • Display subsystem
    • Triple display support over OLDI (LVDS) (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
      • OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165MHZ Pixel Clock)
      • OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150MHz Pixel Clock)
      • MIPI DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300MHz Pixel Clock)
      • DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165MHz pixel clock)
    • Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display.
    • Supports safety features such as freeze frame detection and data correctness check
  • 3D Graphics Processing Unit
    • IMG BXS-4-64 with 256KB cache
    • Up to 50GFLOPS
    • Single shader core
    • OpenGL ES3.2 and Vulkan 1.2 API support
  • One Camera Serial Interface (CSI-2) Receiver with 4 Lane D-PHY
    • MIPI® CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
    • Support for 1,2,3 or 4 data lane mode up to 2.5Gbps per lane
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Up to 300MPixels/s operation, with reduced clocking options available for lower power applications with lower performance needs

Memory Subsystem:

  • Up to 1.09MB of On-chip RAM
    • 64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device Manager Subsystem
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4 memory type
    • 32-bit data bus with inline ECC
    • Supports speeds up to 3733MT/s
    • Max size of 8GB

Functional Safety:

  • Functional Safety-Compliant targeted [Industrial]
    • Developed for functional safety applications
    • Documentation will be available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3 targeted
    • Hardware Integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 by TÜV SÜD planned
  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 by TÜV SÜD planned
  • AEC - Q100 qualified [Automotive]

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50MHz
    • Up to 4/6/16 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 4x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN-FD support (up to 64 data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8Mbps

Media and Data Storage:

  • 3x Multi-Media Card/Secure Digital (MMC/SD/SDIO) interfaces
    • 1x 8-bit eMMC interface up to:
      • HS200 for non-Q1 devices
      • HS400 for Q1 devices
    • 2x 4-bit SD/SDIO interfaces up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
    • Flexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH code to support 4-, 8-, or 16-bit ECC
    • Uses Hamming code to support 1-bit ECC
    • Error Locator Module (ELM)
      • Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithms
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash devices
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low-power modes supported by Device Manager:
    • Partial IO support for CAN/GPIO/UART wakeup
    • I/O Only + DDR in Self Refresh for Suspend to RAM
    • DeepSleep
    • MCU Only
    • Standby
    • Dynamic frequency scaling

Optimal Power Management Solution:

  • Recommended TI Power Management ICs (PMIC)
    • Supports up to Automotive ASIL-B functional safety when powering the AEC – Q100 qualified AM62P-Q1 device
    • Supports up to SIL-2 functional safety industrial applications when powering the AM62P device
    • Companion PMIC is specially designed to meet power supply requirements
    • Flexible mapping and factory programmed configurations to support different use cases

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • SD Card
  • eMMC
  • USB (host) Mass storage
  • USB (device) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16nm FinFET technology
  • 17mm x 17mm, 0.65/0.8mm pitch with VCA, 466-pin FCBGA

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories

Multimedia:

  • Display subsystem
    • Triple display support over OLDI (LVDS) (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
      • OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165MHZ Pixel Clock)
      • OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150MHz Pixel Clock)
      • MIPI DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300MHz Pixel Clock)
      • DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165MHz pixel clock)
    • Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display.
    • Supports safety features such as freeze frame detection and data correctness check
  • 3D Graphics Processing Unit
    • IMG BXS-4-64 with 256KB cache
    • Up to 50GFLOPS
    • Single shader core
    • OpenGL ES3.2 and Vulkan 1.2 API support
  • One Camera Serial Interface (CSI-2) Receiver with 4 Lane D-PHY
    • MIPI® CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
    • Support for 1,2,3 or 4 data lane mode up to 2.5Gbps per lane
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Up to 300MPixels/s operation, with reduced clocking options available for lower power applications with lower performance needs

Memory Subsystem:

  • Up to 1.09MB of On-chip RAM
    • 64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device Manager Subsystem
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4 memory type
    • 32-bit data bus with inline ECC
    • Supports speeds up to 3733MT/s
    • Max size of 8GB

Functional Safety:

  • Functional Safety-Compliant targeted [Industrial]
    • Developed for functional safety applications
    • Documentation will be available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3 targeted
    • Hardware Integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 by TÜV SÜD planned
  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 by TÜV SÜD planned
  • AEC - Q100 qualified [Automotive]

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50MHz
    • Up to 4/6/16 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 4x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN-FD support (up to 64 data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8Mbps

Media and Data Storage:

  • 3x Multi-Media Card/Secure Digital (MMC/SD/SDIO) interfaces
    • 1x 8-bit eMMC interface up to:
      • HS200 for non-Q1 devices
      • HS400 for Q1 devices
    • 2x 4-bit SD/SDIO interfaces up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
    • Flexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH code to support 4-, 8-, or 16-bit ECC
    • Uses Hamming code to support 1-bit ECC
    • Error Locator Module (ELM)
      • Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithms
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash devices
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low-power modes supported by Device Manager:
    • Partial IO support for CAN/GPIO/UART wakeup
    • I/O Only + DDR in Self Refresh for Suspend to RAM
    • DeepSleep
    • MCU Only
    • Standby
    • Dynamic frequency scaling

Optimal Power Management Solution:

  • Recommended TI Power Management ICs (PMIC)
    • Supports up to Automotive ASIL-B functional safety when powering the AEC – Q100 qualified AM62P-Q1 device
    • Supports up to SIL-2 functional safety industrial applications when powering the AM62P device
    • Companion PMIC is specially designed to meet power supply requirements
    • Flexible mapping and factory programmed configurations to support different use cases

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • SD Card
  • eMMC
  • USB (host) Mass storage
  • USB (device) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16nm FinFET technology
  • 17mm x 17mm, 0.65/0.8mm pitch with VCA, 466-pin FCBGA

The AM62Px (P = Plus) is an extension of the existing Sitara™ AM62x low-cost family of application processors built for high-performance embedded 3D display applications. Scalable Arm® Cortex®-A53 performance and embedded features, such as: multi-screen high-definition display support, 3D-graphics acceleration, 4K video acceleration, and extensive peripherals make the AM62Px well-suited for a broad range of automotive and industrial applications, including automotive digital instrumentation, automotive displays, industrial HMI, and more.

Key features and benefits:

  • Focus on innovation and fast development with Linux and Android™ SDKs accompanied with real-time functional safety and security SDKs.
  • Address next wave of HMI designs with new generation of 3D GPU and 4K video acceleration.
  • Enhance your design connectivity with an extensive set of automotive and high-speed IOs, including: 4x CAN-FD, 3-port Gigabit Ethernet switch (two external ports) with TSN support, and two USB2.0 ports.
  • Supports the latest cybersecurity requirements with the built-in Hardware Security Module (HSM).
  • Provides intelligent features, such as: facial recognition and touchless HMI with Arm® Cortex®-A53 CPUs and open-source AI software and tools

The AM62Px processors comply with the AEC - Q100 automotive standard and support industrial-grade. ASIL-B and SIL-2 functional safety requirements can be addressed using an integrated Arm Cortex-R5F core and dedicated peripherals, which can all be isolated from the rest of the processor.

Products in the AM62Px processor family:

AM62P-Q1 – Automotive digital instrumentation SoC with scalable Arm Cortex-A53 performance, multi high-definition display support, 3D GPU and 4K video acceleration.

Featured design resources:

  • Hardware Evaluation Module (EVM) - SK-AM62P-LP
  • Software Development Kit (SDK) - PROCESSOR-SDK-AM62P
  • Linux Academy

The AM62Px (P = Plus) is an extension of the existing Sitara™ AM62x low-cost family of application processors built for high-performance embedded 3D display applications. Scalable Arm® Cortex®-A53 performance and embedded features, such as: multi-screen high-definition display support, 3D-graphics acceleration, 4K video acceleration, and extensive peripherals make the AM62Px well-suited for a broad range of automotive and industrial applications, including automotive digital instrumentation, automotive displays, industrial HMI, and more.

Key features and benefits:

  • Focus on innovation and fast development with Linux and Android™ SDKs accompanied with real-time functional safety and security SDKs.
  • Address next wave of HMI designs with new generation of 3D GPU and 4K video acceleration.
  • Enhance your design connectivity with an extensive set of automotive and high-speed IOs, including: 4x CAN-FD, 3-port Gigabit Ethernet switch (two external ports) with TSN support, and two USB2.0 ports.
  • Supports the latest cybersecurity requirements with the built-in Hardware Security Module (HSM).
  • Provides intelligent features, such as: facial recognition and touchless HMI with Arm® Cortex®-A53 CPUs and open-source AI software and tools

The AM62Px processors comply with the AEC - Q100 automotive standard and support industrial-grade. ASIL-B and SIL-2 functional safety requirements can be addressed using an integrated Arm Cortex-R5F core and dedicated peripherals, which can all be isolated from the rest of the processor.

Products in the AM62Px processor family:

AM62P-Q1 – Automotive digital instrumentation SoC with scalable Arm Cortex-A53 performance, multi high-definition display support, 3D GPU and 4K video acceleration.

Featured design resources:

  • Hardware Evaluation Module (EVM) - SK-AM62P-LP
  • Software Development Kit (SDK) - PROCESSOR-SDK-AM62P
  • Linux Academy
filter 기타 멀티미디어 및 산업용 네트워킹 SoC 찾기
다운로드 스크립트와 함께 비디오 보기 비디오
추가 정보 요청

AM62P-Q1에 대한 기능 안전 고급 문서. 지금 요청

AM62P-Q1에 대한 보안 고급 문서입니다. 지금 요청

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
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25개 모두 보기
상위 문서 유형 직함 형식 옵션 날짜
* Data sheet AM62Px Sitara™ Processors datasheet (Rev. C) PDF | HTML 2025/10/24
* Errata AM62Px Sitara™ Processors Silicon Errata (Rev. B) PDF | HTML 2025/10/31
* User guide AM62Px Sitara™ Processors Technical Reference Manual (Rev. D) 2026/02/05
Application note AM62Px eMMC Board Design and Layout Guidelines PDF | HTML 2026/01/27
Application note Linux Audio on Sitara Socs PDF | HTML 2025/12/12
User guide Hardware Design Considerations for Custom Board Using AM62P, AM62P-Q1 Family of Processors (Rev. C) PDF | HTML 2025/10/24
Application note Sitara Processor Power Distribution Networks: Implementation and Analysis (Rev. H) PDF | HTML 2025/10/17
User guide AM62P, AM62P-Q1 Processor Family Schematic, Design Guidelines and Review Checklist (Rev. B) PDF | HTML 2025/09/17
User guide AM62x, AM62Ax, AM62D-Q1 and AM62Px Processor Family Schematic, Design Guidelines and Review Checklist (Rev. I) PDF | HTML 2025/09/17
Application note AM62x, AM62Ax, AM62Px, AM62Lx Spread-Spectrum Clocking PDF | HTML 2025/09/08
Application note Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 2025/09/05
Functional safety information AM6x, AM24x Software Diagnostics Library TÜV SÜD Functional Safety Certificate for 9.2.0 SDK (Rev. A) 2025/07/17
White paper Securing Arm-Based Application Processors (Rev. F) PDF | HTML 2025/02/26
Application note MCAN Debug Guide PDF | HTML 2025/02/18
Application note Microcontroller Abstraction Layer on Jacinto™ and Sitara™ Embedded Processors PDF | HTML 2025/01/28
Application note AM62Ax, AM62Px LPDDR4 Board Design and Layout Guidelines (Rev. B) PDF | HTML 2024/12/17
User guide AM62P Power Estimation Tool User's Guide PDF | HTML 2024/09/24
Application note Minimal Platform Development on AM62x Devices (Rev. A) PDF | HTML 2024/09/24
Application note Sitara AM62P Benchmarks (Rev. A) PDF | HTML 2024/08/13
Product overview PMIC for Powering AM62Px Devices PDF | HTML 2024/03/14
Application note Developing Multiple-Camera Applications on AM6x (Rev. A) PDF | HTML 2024/02/14
Application note AM62Px Escape Guidelines (Rev. B) PDF | HTML 2024/01/11
Application note Multimedia Applications on AM62A PDF | HTML 2023/11/29
Application note Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 2023/11/15
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023/02/24

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

SK-AM62P-LP — AM62P 스타터 키트 평가 모듈

SK-AM62P-LP SK(스타터 키트) EVM(평가 모듈)은 확장 가능한 Arm® Cortex®-A53 성능 및 삼중 고해상도 디스플레이 지원, 고성능 3D-GPU, 4K 동영상 가속 및 광범위한 주변 기기와 같은 임베디드 기능이 포함된 AM62P 디스플레이 프로세서를 중심으로 구축되었습니다. SK-AM62P-LP는 차량용 디지털 기기, 차량용 디스플레이, 산업용 HMI 등을 포함한 차량용 및 산업용 애플리케이션 개발을 위한 것입니다.

SK-AM62P-LP에는 최대 3개의 화면을 지원하는 다중 디스플레이 커넥터, (...)

사용 설명서: PDF | HTML
TI.com에서 구매할 수 없음
디버그 프로브

TMDSEMU110-U — XDS110 JTAG 디버그 프로브

텍사스 인스트루먼트 XDS110은 TI 임베디드 프로세서를 위한 새로운 디버그 프로브(에뮬레이터)입니다. XDS110은 XDS100 제품군을 대체하면서 하나의 포드로 더 다양한 표준(IEEE1149.1, IEEE1149.7, SWD)을지원합니다. 또한 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)가 포함되어 있는 모든 Arm® 및 DSP 프로세서에서 코어(Core) 및 시스템 트레이스(System Trace)를 지원합니다.  핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

(...)
사용 설명서: PDF
Download English Version: PDF
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디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 장치를 디버깅하는 데 사용되는 디버그 프로브(에뮬레이터)입니다. 대부분의 장치의 경우 더욱 저렴한 신형 XDS110(www.ti.com/tool/TMDSEMU110-U)을 사용하실 것을 권장합니다. XDS200은 단일 포드에서 다양한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(임베디드 트레이스 버퍼)가 포함되어 있는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 트레이스를 지원합니다.

XDS200은 TI 20핀 커넥터(TI 14핀, (...)

TI.com에서 구매할 수 없음
디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

TI.com에서 구매할 수 없음
디버그 프로브

LB-3P-TRACE32-ARM — Arm® 기반 마이크로컨트롤러 및 프로세서용 Lauterbach TRACE32® 디버그 및 트레이스 시스템

Lauterbach의 TRACE32® 툴은 개발자가 모든 종류의 Arm® 기반 마이크로컨트롤러 및 프로세서를 분석, 최적화 및 인증할 수 있도록 하는 첨단 하드웨어 및 소프트웨어 구성 요소 제품군입니다. 세계적으로 유명한 임베디드 시스템 및 SoC용 디버그 및 트레이스 솔루션은 초기 사전 실리콘 개발부터 현장의 제품 인증 및 문제 해결에 이르기까지 모든 개발 단계를 위한 완벽한 솔루션입니다. Lauterbach 툴의 직관적인 모듈형 설계는 엔지니어에게 현존하는 최고의 성능을 제공하고 요구 사항 변화에 따라 적응하고 성장하는 (...)

발송: Lauterbach GmbH
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디버그 프로브

TSK-3P-BLUEBOX — TASKING BlueBox hardware debugger

TASKING’s Debug, Trace, and Test tools offer comprehensive solutions for efficient debugging, tracing, and testing of TI's embedded systems. The scalable TASKING BlueBox debuggers allow users to easily flash, debug, and test across TI's portfolio. Development on TI hardware is made even easier with (...)

발송: TASKING Germany GmbH
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소프트웨어 개발 키트(SDK)

MCU-PLUS-SDK-AM62P — MCU+ SDK for AM62P – RTOS, No-RTOS

The AM62P processor Linux®, Android™ and TI MCU+ software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across our broad portfolio for which (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
찾아보기 다운로드 옵션
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-ANDROID-AM62P — Processor SDK Android for AM62P

The AM62P processor Linux®, Android™ and TI MCU+ software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across our broad portfolio for which (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
다운로드 옵션
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-AM62P — Processor SDK Linux for AM62P

The AM62P processor Linux®, Android™ and TI MCU+ software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across our broad portfolio for which (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
다운로드 옵션
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-RT-AM62P — Processor SDK Linux RT for AM62P

The AM62P processor Linux®, Android™ and TI MCU+ software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across our broad portfolio for which (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
다운로드 옵션
애플리케이션 소프트웨어 및 프레임워크

CANDERA-3P-CGI-STUDIO — AM62x Sitara 프로세서를 위한 Candera CGI Studio HMI 개발 소프트웨어

Candera CGI Studio is a powerful design tool for creating dynamic HMIs across diverse industries. It provides an intuitive workflow with state-of-the-art 2D/3D graphics, scalable architecture, and full multi-language support. Designed for efficiency and flexibility, it enables seamless (...)
발송: Candera GmbH
파트너 사이트 방문
애플리케이션 소프트웨어 및 프레임워크

EB-3P-TRESOS — Elektrobit EB tresos 클래식 AUTOSAR 소프트웨어

기본 소프트웨어 분야에서 수십 년의 경험을 보유한 Elektrobit의 EB tresos 제품 라인과 맞춤형 클래식 AUTOSAR 솔루션은 첨단 소프트웨어를 제공하는 각 자동차 제조업체의 특정 요구 사항을 해결하는 데 도움이 됩니다. 각 프로젝트에서 Elektrobit는 OSEK-/VDX 호환 기본 소프트웨어부터 클래식 AUTOSAR 기반 멀티 코어 및 기능 안전 시스템까지 차량용 AUTOSAR 요구 사항을 충족하는 적절한 솔루션을 제공합니다.
발송: Elektrobit
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펌웨어

DDR-MARGIN-FW — Firmware and scripts to measure system DDR margin

The DDR margin firmware and supporting scripts allow visualization and measurement of system margin in the DDR interface on board. These tools enable probe-less measurement of critical data signals to understand the integrity and robustness of the interface.
지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
다운로드 옵션
시작하기

TI-DEVELOPER-ZONE — Start embedded development on your desktop or in the cloud

From evaluation to deployment the TI Developer Zone provides a comprehensive range of software, tools and training to ensure that you have everything you need for each stage of the development process.
지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
시작하기
IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
시작 다운로드 옵션
IDE, 구성, 컴파일러 또는 디버거

DDR-CONFIG-AM62P — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
시작 다운로드
IDE, 구성, 컴파일러 또는 디버거

K3-RESOURCE-CONFIGURATION — Resource partitioning tool for multi core SOCs

Also known as the k3-respart-tool, the Resource Configuration tool allows for configuration of various system level parameters and generate the necessary data to be fed into software components
지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
시작
IDE, 구성, 컴파일러 또는 디버거

SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
시작 다운로드 옵션
온라인 교육

AM62P-ACADEMY — AM62P Academy

AM62P Academy is designed to simplify and accelerate custom AM62Px development.
지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
찾아보기
운영 체제(OS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
발송: Green Hills Software
파트너 사이트 방문
운영 체제(OS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
발송: Green Hills Software
파트너 사이트 방문
운영 체제(OS)

WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS 사전 인증 안전 RTOS

SAFERTOS®는 임베디드 프로세서를 위해 설계된 고유한 실시간 운영 체제입니다. TÜV SÜD의 IEC 61508 SIL3 및 ISO 26262 ASILD 표준에 따라 사전 인증을 받았습니다. SAFERTOS®는 WHIS 전문가 팀에서 안전을 위해 특별히 제작되었으며, 전 세계적으로 안전이 중요한 응용 분야에 사용됩니다. WHIS와 텍사스 인스트루먼트는 10년 넘게 협력해 왔습니다. 이 기간 동안, WHIS는 SAFERTOS®를 광범위한 TI 프로세서로 이식하여 널리 사용되는 모든 코어를 지원하며 요청 시 추가 아키텍처를 (...)
발송: WITTENSTEIN High Integrity Systems
파트너 사이트 방문
지원 소프트웨어

PROCESSOR-SDK-QNX-AM62P — Processor SDK QNX for AM62P

The AM62P processor Linux®, Android™ and TI MCU+ software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across our broad portfolio for which (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
요청
지원 소프트웨어

VCTR-3P-MICROSAR — 마이크로컨트롤러 및 고성능 컴퓨터(HPC)용 벡터 MICROSAR AUTOSAR 소프트웨어

MICROSAR 및 DaVinci 제품군은 정교한 임베디드 소프트웨어 및 마이크로 컨트롤러 및 HPC를 위한 강력한 개발 툴로 ECU 개발을 간소화합니다. 고급 인프라 소프트웨어를 사용하면 ECU를 위한 최적의 기반을 만들고 관련 툴로 수반되는 모든 개발 작업을 간소화할 수 있습니다. MICROSAR 내장 소프트웨어는 AUTOSAR 클래식 및 적응형과 같은 관련 표준에 따라 개발되었습니다. 이 소프트웨어는 ISO 26262까지 ASIL D에 따른 안전 관련 애플리케이션에도 적합합니다. 또한, 지능형 사이버 보안 기능은 무단 액세스 (...)
발송: Vector Informatik GmbH
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시뮬레이션 모델

AM62P and AM62P-Q1 Sitara™ BSDL Model (Rev. A)

SPRM827A.ZIP (10 KB) - BSDL Model
다운로드
시뮬레이션 모델

AM62Px Sitara™ AMI Model

SPRM826.ZIP (61927 KB) - IBIS-AMI Model
다운로드
시뮬레이션 모델

AM62Px Sitara™ IBIS Model (Rev. C)

SPRM825C.ZIP (3296 KB) - IBIS Model
다운로드
시뮬레이션 모델

AM62Px Sitara™ Thermal Model

SPRM828.ZIP (1 KB) - Thermal Model
다운로드
시뮬레이션 툴

AM62P-EMMC-BIT-PATTERN-SIM-TOOL — AM62P EVM eMMC HS400 SI Simulation bit pattern text file

This text file patterns are designed to exercise the system to real, but worst-case conditions in SI Simulation
지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
다운로드
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
FCBGA (AMH) 466 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

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