홈 마이크로컨트롤러(MCU) 및 프로세서 마이크로프로세서 및 DSP 멀티미디어 및 산업용 네트워킹 SoC
홈
마이크로컨트롤러(MCU) 및 프로세서
마이크로프로세서 및 DSP
멀티미디어 및 산업용 네트워킹 SoC

AM625SIP

활성

Arm® Cortex®-A53 및 일체형 LPDDR4이 포함된 패키지에 들어 있는 범용 시스템

지금 주문하기
데이터 시트
사용자 가이드

AM625SIP

활성
데이터 시트 지금 주문하기

제품 상세 정보

CPU 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-M4F Graphics acceleration 1 3D Display type MIPI DPI, OLDI Protocols Ethernet, TSN Hardware accelerators CPU only, Industrial communications subsystem, Programable real-time unit Features General purpose, Integrated 512MB LPDDR4 SDRAM Operating system Android, Linux, RTOS Security Secure boot Rating Catalog Power supply solution TPS65219 Operating temperature range (°C) -40 to 95 Edge AI enabled Yes
CPU 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-M4F Graphics acceleration 1 3D Display type MIPI DPI, OLDI Protocols Ethernet, TSN Hardware accelerators CPU only, Industrial communications subsystem, Programable real-time unit Features General purpose, Integrated 512MB LPDDR4 SDRAM Operating system Android, Linux, RTOS Security Secure boot Rating Catalog Power supply solution TPS65219 Operating temperature range (°C) -40 to 95 Edge AI enabled Yes
FCCSP (AMK) 425 169 mm² (13 mm × 13 mm)

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache withParity protection
  • Single-core Arm® Cortex®-M4F MCU at up to400MHz
    • 256KB SRAM with SECDED ECC
  • Dedicated Device/Power Manager

Multimedia:

  • Display subsystem
    • Dual display support
    • 1920x1080 @ 60fps for each display
    • 1x 2048x1080 + 1x 1280x720
    • Up to 165MHz pixel clock support with Independent PLL for each display
    • OLDI (4 lanes LVDS - 2x) andDPI (24-bit RGB LVCMOS)
    • Support safety feature such as freeze frame detection and MISR data check
  • 3D Graphics Processing Unit
    • 1 pixel per clock or higher
    • Fillrate greater than 500Mpixels/sec
    • >500 MTexels/s, >8GFLOPs
    • Supports at least 2 composition layers
    • Supports up to 2048x1080 @60fps
    • Supports ARGB32, RGB565 and YUV formats
    • 2D graphics capable
    • OpenGL ES 3.1, Vulkan 1.2
  • One Camera Serial interface (CSI-Rx) - 4 Lane with DPHY
    • MIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
    • Support for 1,2,3 or 4 data lane mode up to 1.5Gbps per lane
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA

Memory Subsystem:

  • Up to 816KB of On-chip RAM
    • 64KB of On-chip RAM (OCSRAM) with SECDED ECC , Can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 256KB of On-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
  • DDR Subsystem (DDRSS)
    • Integrated 512MB LPDDR4 SDRAM
    • Supports speeds up to 1600MT/s
    • 16-Bit data bus with inline ECC

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

PRU Subsystem:

  • Dual-core Programmable Real-Time Unit Subystem (PRUSS) running up to 333MHz
  • Intended for driving GPIO for cycle accurate protocols such as additional:
    • General Purpose Input/Output (GPIO)
    • UARTs
    • I2C
    • External ADC
  • 16KByte program memory per PRU withSECDED ECC
  • 8KB data memory per PRU with SECDED ECC
  • 32KB general purpose memory withSECDED ECC
  • CRC32/16 HW accelerator
  • Scratch PAD memory with 3 banks of30 x 32-bit registers
  • 1 Industrial 64-bit timer with 9 capture and 16 compare events, along with slow and fast compensation
  • 1 interrupt controller (INTC), minimum of 64 input events supported

High-Speed Interfaces:

  • Integrated Ethernet switch supporting(total of 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time sensitive networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50 MHz
    • Up to 16/10/6 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive(256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 3x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN FD support (up to 64 data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8Mbps

Media and Data Storage:

  • 3x Multi-Media Card/Secure Digital(MMC/SD/SDIO) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0 andSDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133 MHz
    • Flexible 8- and 16-Bit Asynchronous Memory Interface With up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
    • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR flash devices
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low power modes supported by Device/Power Manager
    • Partial IO support for CAN/GPIO/UART wakeup
    • DeepSleep
    • MCU Only
    • Standby
    • Dynamic frequency scaling for Cortex-A53

Optimal Power Management Solution:

  • Recommended TPS65219 Power Management ICs (PMIC)
    • Companion PMIC specially designed to meet device power supply requirements
    • Flexible mapping and factory programmed configurations to support different use cases

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • Serial NAND Flash
  • SD Card
  • eMMC
  • USB (host) boot from Mass Storage device
  • USB (device) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16-nm technology
  • 13mm x 13mm, 0.5-mm pitch, 425-pinFCCSP BGA (AMK)

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache withParity protection
  • Single-core Arm® Cortex®-M4F MCU at up to400MHz
    • 256KB SRAM with SECDED ECC
  • Dedicated Device/Power Manager

Multimedia:

  • Display subsystem
    • Dual display support
    • 1920x1080 @ 60fps for each display
    • 1x 2048x1080 + 1x 1280x720
    • Up to 165MHz pixel clock support with Independent PLL for each display
    • OLDI (4 lanes LVDS - 2x) andDPI (24-bit RGB LVCMOS)
    • Support safety feature such as freeze frame detection and MISR data check
  • 3D Graphics Processing Unit
    • 1 pixel per clock or higher
    • Fillrate greater than 500Mpixels/sec
    • >500 MTexels/s, >8GFLOPs
    • Supports at least 2 composition layers
    • Supports up to 2048x1080 @60fps
    • Supports ARGB32, RGB565 and YUV formats
    • 2D graphics capable
    • OpenGL ES 3.1, Vulkan 1.2
  • One Camera Serial interface (CSI-Rx) - 4 Lane with DPHY
    • MIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
    • Support for 1,2,3 or 4 data lane mode up to 1.5Gbps per lane
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA

Memory Subsystem:

  • Up to 816KB of On-chip RAM
    • 64KB of On-chip RAM (OCSRAM) with SECDED ECC , Can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 256KB of On-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
  • DDR Subsystem (DDRSS)
    • Integrated 512MB LPDDR4 SDRAM
    • Supports speeds up to 1600MT/s
    • 16-Bit data bus with inline ECC

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

PRU Subsystem:

  • Dual-core Programmable Real-Time Unit Subystem (PRUSS) running up to 333MHz
  • Intended for driving GPIO for cycle accurate protocols such as additional:
    • General Purpose Input/Output (GPIO)
    • UARTs
    • I2C
    • External ADC
  • 16KByte program memory per PRU withSECDED ECC
  • 8KB data memory per PRU with SECDED ECC
  • 32KB general purpose memory withSECDED ECC
  • CRC32/16 HW accelerator
  • Scratch PAD memory with 3 banks of30 x 32-bit registers
  • 1 Industrial 64-bit timer with 9 capture and 16 compare events, along with slow and fast compensation
  • 1 interrupt controller (INTC), minimum of 64 input events supported

High-Speed Interfaces:

  • Integrated Ethernet switch supporting(total of 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time sensitive networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50 MHz
    • Up to 16/10/6 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive(256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 3x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN FD support (up to 64 data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8Mbps

Media and Data Storage:

  • 3x Multi-Media Card/Secure Digital(MMC/SD/SDIO) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0 andSDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133 MHz
    • Flexible 8- and 16-Bit Asynchronous Memory Interface With up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
    • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR flash devices
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low power modes supported by Device/Power Manager
    • Partial IO support for CAN/GPIO/UART wakeup
    • DeepSleep
    • MCU Only
    • Standby
    • Dynamic frequency scaling for Cortex-A53

Optimal Power Management Solution:

  • Recommended TPS65219 Power Management ICs (PMIC)
    • Companion PMIC specially designed to meet device power supply requirements
    • Flexible mapping and factory programmed configurations to support different use cases

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • Serial NAND Flash
  • SD Card
  • eMMC
  • USB (host) boot from Mass Storage device
  • USB (device) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16-nm technology
  • 13mm x 13mm, 0.5-mm pitch, 425-pinFCCSP BGA (AMK)

AM625SIP is a System In Package (SIP) derivative of the ALW packaged AM6254 device, with the addition of an integrated LPDDR4 SDRAM. This document only defines differences or exceptions to the ALW packaged AM6254 device defined in AM62x Sitara Processors Datasheet (revision B or later).

The AM625SIP (System in Package) Sitara™ MPU with integrated LPDDR4 is an application processor built for Linux development. The system in package integrates 512MB of LPDDR4 with the AM6254 device which has 4x Arm® Cortex®-A53 performance and embedded features, such as: dual-display support, 3D graphics acceleration, along with an extensive set of peripherals that make the System in package well-suited for a broad range of industrial applications while offering intelligent features and optimized power architecture. Additionally, the AM625SIP offers a simplified hardware design, increased robustness, optimized size/system BOM, and power consumption savings all enabling faster software and hardware development.

Some of these applications include:

  • Industrial HMI
  • Medical equipment, Patient monitoring, and Portable medical devices
  • Smart home gateways & Appliances
  • Embedded security: Control & Access panels

The 3-port Gigabit Ethernet switch has one internal port and two external ports with Time-Sensitive Networking (TSN) support. An additional PRU module on the device enables real-time I/O capability for customer’s own use cases. In addition, the extensive set of peripherals included in AM625SIP enables system-level connectivity, such as: USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. The AM625SIP device also supports secure boot for IP protection with the built-in Hardware Security Module (HSM) and employs advanced power management support for portable and power-sensitive applications

AM625SIP is a System In Package (SIP) derivative of the ALW packaged AM6254 device, with the addition of an integrated LPDDR4 SDRAM. This document only defines differences or exceptions to the ALW packaged AM6254 device defined in AM62x Sitara Processors Datasheet (revision B or later).

The AM625SIP (System in Package) Sitara™ MPU with integrated LPDDR4 is an application processor built for Linux development. The system in package integrates 512MB of LPDDR4 with the AM6254 device which has 4x Arm® Cortex®-A53 performance and embedded features, such as: dual-display support, 3D graphics acceleration, along with an extensive set of peripherals that make the System in package well-suited for a broad range of industrial applications while offering intelligent features and optimized power architecture. Additionally, the AM625SIP offers a simplified hardware design, increased robustness, optimized size/system BOM, and power consumption savings all enabling faster software and hardware development.

Some of these applications include:

  • Industrial HMI
  • Medical equipment, Patient monitoring, and Portable medical devices
  • Smart home gateways & Appliances
  • Embedded security: Control & Access panels

The 3-port Gigabit Ethernet switch has one internal port and two external ports with Time-Sensitive Networking (TSN) support. An additional PRU module on the device enables real-time I/O capability for customer’s own use cases. In addition, the extensive set of peripherals included in AM625SIP enables system-level connectivity, such as: USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. The AM625SIP device also supports secure boot for IP protection with the built-in Hardware Security Module (HSM) and employs advanced power management support for portable and power-sensitive applications
filter 기타 멀티미디어 및 산업용 네트워킹 SoC 찾기
다운로드 스크립트와 함께 비디오 보기 비디오

기술 자료

검색된 결과가 없습니다. 검색어를 지우고 다시 시도하세요.
25개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 AM625SIP – AM6254 Sitara™ Processor with Integrated LPDDR4 SDRAM datasheet (Rev. A) PDF | HTML 2024. 6. 16
* 사용 설명서 AM62x Sitara Processors Technical Reference Manual (Rev. C) PDF | HTML 2025. 11. 7
* 정오표 AM62x Sitara Errata (Rev. G) PDF | HTML 2025. 10. 30
애플리케이션 노트 Enable PipeWire on TI Sitara Devices PDF | HTML 2026. 6. 8
애플리케이션 노트 GUI Development on AM6x Processors PDF | HTML 2026. 3. 25
애플리케이션 노트 Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 2026. 2. 12
애플리케이션 노트 Enabling Matter on Sitara MPU (Rev. A) PDF | HTML 2025. 11. 24
사용 설명서 Hardware Design Considerations for Custom Board Using AM625, AM623, AM620-Q1, AM625-Q1, AM625SIP Processor (Rev. E) PDF | HTML 2025. 10. 24
애플리케이션 노트 Sitara Processor Power Distribution Networks: Implementation and Analysis (Rev. H) PDF | HTML 2025. 10. 17
사용 설명서 AM62x, AM62Ax, AM62D-Q1 and AM62Px Processor Family Schematic, Design Guidelines and Review Checklist (Rev. I) PDF | HTML 2025. 9. 17
사용 설명서 AM625, AM623, AM620-Q1, AM625-Q1, AM625SIP Processor Family Schematic, Design Guidelines and Review Checklist (Rev. B) PDF | HTML 2025. 9. 16
애플리케이션 노트 AM62x, AM62Ax, AM62Px, AM62Lx Spread-Spectrum Clocking PDF | HTML 2025. 9. 8
애플리케이션 노트 Processors Tools Overview PDF | HTML 2025. 6. 16
백서 Securing Arm-Based Application Processors (Rev. F) PDF | HTML 2025. 2. 26
애플리케이션 노트 Minimal Platform Development on AM62x Devices (Rev. A) PDF | HTML 2024. 9. 24
Product overview AM625SIP: System In Package Explained PDF | HTML 2024. 2. 22
애플리케이션 노트 AM62x Power Consumption PDF | HTML 2024. 2. 16
애플리케이션 노트 Powering the AM625SIP With the TPS65219 PMIC PDF | HTML 2023. 12. 20
Application brief AM625SIP 프로세서가 LPDDR4를 통합하여 개발을 가속화하는 방법 (Rev. A) PDF | HTML Download English Version (Rev.A) 2023. 12. 18
애플리케이션 노트 Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 2023. 11. 15
Application brief Keyword Spotting Using AI at the Edge With Sitara Processors PDF | HTML 2023. 9. 28
백서 Time Sensitive Networking for Industrial Automation (Rev. C) PDF | HTML 2023. 7. 31
애플리케이션 노트 AM62x SiP PCB Escape Routing PDF | HTML 2023. 7. 21
애플리케이션 노트 AM62x Maximum Current Ratings PDF | HTML 2023. 4. 18
애플리케이션 노트 High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023. 2. 24

설계 및 개발

전원 공급 솔루션

AM625SIP에 사용 가능한 전원 공급 솔루션을 찾아보세요. TI는 칩(SoC), 프로세서, 마이크로컨트롤러, 센서 또는 FPGA(Field Programmable Gate Array)의 TI와 비TI 시스템을 위한 전원 공급 솔루션을 제공합니다.

솔루션 보기
평가 보드

SK-AM62-SIP — Sitara™ 프로세서용 AM62x 시스템 인 패키지 스타터 키트

SK-AM62-SIP 스타터 키트(SK) 평가 모듈(EVM)은 단일 패키지에 통합된 512MB LPDDR4 SDRAM이 포함된 AM6254 시스템 온 칩(SoC) 주변에 구축된 독립형 테스트 및 개발 플랫폼입니다. AM625SIP 프로세서는 쿼드 코어 64비트 Arm®-Cortex®-A53 마이크로프로세서 및 싱글 코어 Arm Cortex-M4F MCU로 구성되어 있습니다.

SK-AM62-SIP에는 보안 애플리케이션용으로 키와 암호화를 선택적으로 맞춤 설정할 수 있는 HS-FS(high-security (...)

사용 설명서: PDF | HTML
지원되는 제품 및 하드웨어
재고 있음
제한:
??asset.out-of-stock-ti_ko_KR??
이용할 수 없음
디버그 프로브

TMDSEMU110-U — XDS110 JTAG 디버그 프로브

텍사스 인스트루먼트 XDS110은 TI 임베디드 프로세서를 위한 새로운 디버그 프로브(에뮬레이터)입니다. XDS110은 XDS100 제품군을 대체하면서 하나의 포드로 더 다양한 표준(IEEE1149.1, IEEE1149.7, SWD)을지원합니다. 또한 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)가 포함되어 있는 모든 Arm® 및 DSP 프로세서에서 코어(Core) 및 시스템 트레이스(System Trace)를 지원합니다.  핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

(...)
지원되는 제품 및 하드웨어
재고 있음
제한:
??asset.out-of-stock-ti_ko_KR??
이용할 수 없음
디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

지원되는 제품 및 하드웨어
재고 있음
제한:
??asset.out-of-stock-ti_ko_KR??
이용할 수 없음
디버그 프로브

LB-3P-TRACE32-ARM — Arm® 기반 마이크로컨트롤러 및 프로세서용 Lauterbach TRACE32® 디버그 및 트레이스 시스템

Lauterbach의 TRACE32® 툴은 개발자가 모든 종류의 Arm® 기반 마이크로컨트롤러 및 프로세서를 분석, 최적화 및 인증할 수 있도록 하는 첨단 하드웨어 및 소프트웨어 구성 요소 제품군입니다. 세계적으로 유명한 임베디드 시스템 및 SoC용 디버그 및 트레이스 솔루션은 초기 사전 실리콘 개발부터 현장의 제품 인증 및 문제 해결에 이르기까지 모든 개발 단계를 위한 완벽한 솔루션입니다. Lauterbach 툴의 직관적인 모듈형 설계는 엔지니어에게 현존하는 최고의 성능을 제공하고 요구 사항 변화에 따라 적응하고 성장하는 (...)

발송: Lauterbach GmbH
지원되는 제품 및 하드웨어
디버그 프로브

TSK-3P-BLUEBOX — TASKING BlueBox hardware debugger

TASKING’s Debug, Trace, and Test tools offer comprehensive solutions for efficient debugging, tracing, and testing of TI's embedded systems. The scalable TASKING BlueBox debuggers allow users to easily flash, debug, and test across TI's portfolio. Development on TI hardware is made even easier with (...)

발송: TASKING Germany GmbH
지원되는 제품 및 하드웨어
소프트웨어 개발 키트(SDK)

MCU-PLUS-SDK-AM62X — MCU+ SDK for AM62x – RTOS, No-RTOS

AM62 프로세서 Linux® 소프트웨어 개발 키트(SDK)는 임베디드 프로세서를 위한 통합 소프트웨어 플랫폼으로 벤치마크 및 데모에 대한 쉬운 설정과 빠른 즉시 액세스를 제공합니다.

이 SDK의 모든 릴리스는 제공되는 TI의 광범위한 포트폴리오에서 일관되므로 개발자는 제품 간에 소프트웨어를 원활하게 재사용하고 개발할 수 있습니다.

지원되는 제품 및 하드웨어
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-AM62X — Processor SDK Linux for AM62x

AM62 프로세서 Linux® 소프트웨어 개발 키트(SDK)는 임베디드 프로세서를 위한 통합 소프트웨어 플랫폼으로 벤치마크 및 데모에 대한 쉬운 설정과 빠른 즉시 액세스를 제공합니다.

이 SDK의 모든 릴리스는 제공되는 TI의 광범위한 포트폴리오에서 일관되므로 개발자는 제품 간에 소프트웨어를 원활하게 재사용하고 개발할 수 있습니다.

지원되는 제품 및 하드웨어
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-RT-AM62X — Processor SDK RT-Linux for AM62x

AM62 프로세서 Linux® 소프트웨어 개발 키트(SDK)는 임베디드 프로세서를 위한 통합 소프트웨어 플랫폼으로 벤치마크 및 데모에 대한 쉬운 설정과 빠른 즉시 액세스를 제공합니다.

이 SDK의 모든 릴리스는 제공되는 TI의 광범위한 포트폴리오에서 일관되므로 개발자는 제품 간에 소프트웨어를 원활하게 재사용하고 개발할 수 있습니다.

지원되는 제품 및 하드웨어
IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

지원되는 제품 및 하드웨어
IDE, 구성, 컴파일러 또는 디버거

DDR-CONFIG-AM62 — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
지원되는 제품 및 하드웨어
IDE, 구성, 컴파일러 또는 디버거

EDGE-AI-STUDIO — Edge AI Studio

Edge AI Studio는 TI 프로세서, 마이크로컨트롤러, 레이더 센서의 에지 AI 개발을 가속화하기 위해 설계된 그래픽 및 명령줄 툴 모음입니다. TI Model Zoo의 모델을 활용해 개념 증명을 개발하든,
자체 모델을 활용하든, Edge AI Studio는 필요한 모든 툴을 제공합니다.

Edge AI Studio 그래픽 사용자 인터페이스는 라이브 개발 플랫폼에 배포할 모델을 교육 및 컴파일하고, 데이터를 수집하고 데이터에 주석을 추가하기 위한 완전 통합 솔루션을 제공합니다. TI Model Zoo에서 다양한 사전 학습된 (...)

지원되는 제품 및 하드웨어
IDE, 구성, 컴파일러 또는 디버거

K3-RESOURCE-CONFIGURATION — Resource partitioning tool for multi core SOCs

Also known as the k3-respart-tool, the Resource Configuration tool allows for configuration of various system level parameters and generate the necessary data to be fed into software components
지원되는 제품 및 하드웨어
IDE, 구성, 컴파일러 또는 디버거

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

지원되는 제품 및 하드웨어
IDE, 구성, 컴파일러 또는 디버거

TSK-3P-VX-TOOLSET — Arm용 TASKING VX-toolset

Arm용 VX-Toolset은 일부 Cortex-M 및 Cortex-R 코어 장치의 안전 필수 임베디드 소프트웨어 개발을 위해 인증된 컴파일러 툴체인입니다. Eclipse IDE 통합, 고급 멀티코어 지원, TASKING BlueBox 디버거와의 호환성을 제공하는 VX-toolset은 개발을 단순화합니다. 최대 ASIL D까지의 ISO 26262 및 ISO 21434 규격 준수를 위해 TÜV NORD 인증을 획득했습니다.

발송: TASKING Germany GmbH
지원되는 제품 및 하드웨어
온라인 교육

AM62-ACADEMY — AM62x Academy

AM62x Academy is designed to simplify and accelerate custom AM62x development.
지원되는 제품 및 하드웨어
시작하기

TI-DEVELOPER-ZONE — Start embedded development on your desktop or in the cloud

From evaluation to deployment the TI Developer Zone provides a comprehensive range of software, tools and training to ensure that you have everything you need for each stage of the development process.
지원되는 제품 및 하드웨어
운영 체제(OS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
지원되는 제품 및 하드웨어
운영 체제(OS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)

발송: Green Hills Software
지원되는 제품 및 하드웨어
운영 체제(OS)

WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS 사전 인증 안전 RTOS

SAFERTOS®는 임베디드 프로세서를 위해 설계된 고유한 실시간 운영 체제입니다. TÜV SÜD의 IEC 61508 SIL3 및 ISO 26262 ASILD 표준에 따라 사전 인증을 받았습니다. SAFERTOS®는 WHIS 전문가 팀에서 안전을 위해 특별히 제작되었으며, 전 세계적으로 안전이 중요한 응용 분야에 사용됩니다. WHIS와 텍사스 인스트루먼트는 10년 넘게 협력해 왔습니다. 이 기간 동안, WHIS는 SAFERTOS®를 광범위한 TI 프로세서로 이식하여 널리 사용되는 모든 코어를 지원하며 요청 시 추가 아키텍처를 (...)

발송: WITTENSTEIN High Integrity Systems
지원되는 제품 및 하드웨어
펌웨어

DDR-MARGIN-FW — Firmware and scripts to measure system DDR margin

The DDR margin firmware and supporting scripts allow visualization and measurement of system margin in the DDR interface on board. These tools enable probe-less measurement of critical data signals to understand the integrity and robustness of the interface.
지원되는 제품 및 하드웨어
시뮬레이션 모델

AM625SIP AMK SR 1.0 BSDL Model

SPRM841.ZIP (9 KB) - BSDL 모델
지원되는 제품 및 하드웨어
시뮬레이션 모델

AM625SIP AMK SR 1.0 IBIS Model (Rev. A)

SPRM842A.ZIP (2149 KB) - IBIS 모델
지원되는 제품 및 하드웨어
시뮬레이션 모델

AM625SIP AMK SR 1.0 IBIS-AMI Model

SPRM844.ZIP (80697 KB) - IBIS-AMI 모델
지원되는 제품 및 하드웨어
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
FCCSP (AMK) 425 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

비디오 시리즈

모든 비디오 보기

동영상