DRA75P

활성

ISP를 지원하고 인포테인먼트 애플리케이션을 위해 DRA75x SoC 프로세서와 핀 호환 가능한 멀티코어 SoC 프로세서

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사용자 가이드

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DRA77xP, DRA76xP, DRA75xP, DRA74xP Technical Reference Manual (Rev. D) (영어)

정오표

DRA75P

활성

지금 주문하기

제품 상세 정보

CPU

2 Arm Cortex-A15

Frequency (MHz)

1500

Coprocessors

4 Arm Cortex-M4

Graphics acceleration

1 2D, 2 3D

Display type

1 HDMI, 3 LCD

Protocols

Ethernet

PCIe

2 PCIe Gen 2

Hardware accelerators

Audio tracking logic, Image system processor, Image video accelerator, Viterbi decoder

Features

Multimedia

Operating system

Android, Linux, RTOS

Security

Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection

Rating

Automotive

Operating temperature range (°C)

-40 to 125

Edge AI enabled

CPU

2 Arm Cortex-A15

Frequency (MHz)

1500

Coprocessors

4 Arm Cortex-M4

Graphics acceleration

1 2D, 2 3D

Display type

1 HDMI, 3 LCD

Protocols

Ethernet

PCIe

2 PCIe Gen 2

Hardware accelerators

Audio tracking logic, Image system processor, Image video accelerator, Viterbi decoder

Features

Multimedia

Operating system

Android, Linux, RTOS

Security

Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection

Rating

Automotive

Operating temperature range (°C)

-40 to 125

Edge AI enabled

FCCSP (ABZ)

760

529 mm² 23 x 23

Architecture Designed for Infotainment Applications
Video, Image, and Graphics Processing Support
- Full-HD Video (1920 × 1080p, 60 fps)
- Multiple Video Input and Video Output
- 2D and 3D Graphics
Dual Arm^® Cortex^®-A15 Microprocessor Subsystem
Up to Two C66x Floating-Point VLIW DSP
- Fully Object-Code Compatible with C67x and C64x+
- Up to Thirty-Two 16 x 16-Bit Fixed-Point Multiplies per Cycle
Up to 2.5MB of On-Chip L3 RAM
Level 3 (L3) and Level 4 (L4) Interconnects
Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
- Supports up to DDR2-800 and DDR3-1333
- Up to 2GB Supported per EMIF
Dual ARM® Cortex®-M4 Image Processing Units (IPU)
Up to Two Embedded Vision Engines (EVEs)
Imaging Subsystem (ISS)
- Image Signal Processor (ISP)
- Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
- One Camera Adaptation Layer (CAL_B)
IVA Subsystem
Display Subsystem
- Display Controller with DMA Engine and up to Three Pipelines
- HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
Video Processing Engine (VPE)
2D-Graphics Accelerator (BB2D) Subsystem
- Vivante^® GC320 Core
Dual-Core PowerVR^® SGX544 3D GPU
Two Video Input Port (VIP) Modules
- Support for up to Eight Multiplexed Input Ports
General-Purpose Memory Controller (GPMC)
Enhanced Direct Memory Access (EDMA) Controller
2-Port Gigabit Ethernet (GMAC)
Sixteen 32-Bit General-Purpose Timers
32-Bit MPU Watchdog Timer
Five Inter-Integrated Circuit (I²C) Ports
HDQ™/1-Wire^® Interface
SATA Interface
Media Local Bus (MLB) Subsystem
Ten Configurable UART/IrDA/CIR Modules
Four Multichannel Serial Peripheral Interfaces (McSPI)
Quad SPI (QSPI)
Eight Multichannel Audio Serial Port (McASP) Modules
SuperSpeed USB 3.0 Dual-Role Device
Three High-Speed USB 2.0 Dual-Role Devices
Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD^®/SDIO)
PCI Express^® 3.0 Subsystems with Two 5-Gbps Lanes
- One 2-Lane Gen2-Compliant Port
- or Two 1-Lane Gen2-Compliant Ports
Up to Two Controller Area Network (DCAN) Modules
- CAN 2.0B Protocol
Modular Controller Area Network (MCAN) Module
- CAN 2.0B Protocol with Available FD (Flexible Data Rate) Functionality
Up to 247 General-Purpose I/O (GPIO) Pins
Real-Time Clock Subsystem (RTCSS)
Device Security Features
- Hardware Crypto Accelerators and DMA
- Firewalls
- JTAG^® Lock
- Secure Keys
- Secure ROM and Boot
- Customer Programmable Keys and OTP Data
Power, Reset, and Clock Management
On-Chip Debug with CTools Technology
28-nm CMOS Technology
23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABZ)

Architecture Designed for Infotainment Applications
Video, Image, and Graphics Processing Support
- Full-HD Video (1920 × 1080p, 60 fps)
- Multiple Video Input and Video Output
- 2D and 3D Graphics
Dual Arm^® Cortex^®-A15 Microprocessor Subsystem
Up to Two C66x Floating-Point VLIW DSP
- Fully Object-Code Compatible with C67x and C64x+
- Up to Thirty-Two 16 x 16-Bit Fixed-Point Multiplies per Cycle
Up to 2.5MB of On-Chip L3 RAM
Level 3 (L3) and Level 4 (L4) Interconnects
Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
- Supports up to DDR2-800 and DDR3-1333
- Up to 2GB Supported per EMIF
Dual ARM® Cortex®-M4 Image Processing Units (IPU)
Up to Two Embedded Vision Engines (EVEs)
Imaging Subsystem (ISS)
- Image Signal Processor (ISP)
- Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
- One Camera Adaptation Layer (CAL_B)
IVA Subsystem
Display Subsystem
- Display Controller with DMA Engine and up to Three Pipelines
- HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
Video Processing Engine (VPE)
2D-Graphics Accelerator (BB2D) Subsystem
- Vivante^® GC320 Core
Dual-Core PowerVR^® SGX544 3D GPU
Two Video Input Port (VIP) Modules
- Support for up to Eight Multiplexed Input Ports
General-Purpose Memory Controller (GPMC)
Enhanced Direct Memory Access (EDMA) Controller
2-Port Gigabit Ethernet (GMAC)
Sixteen 32-Bit General-Purpose Timers
32-Bit MPU Watchdog Timer
Five Inter-Integrated Circuit (I²C) Ports
HDQ™/1-Wire^® Interface
SATA Interface
Media Local Bus (MLB) Subsystem
Ten Configurable UART/IrDA/CIR Modules
Four Multichannel Serial Peripheral Interfaces (McSPI)
Quad SPI (QSPI)
Eight Multichannel Audio Serial Port (McASP) Modules
SuperSpeed USB 3.0 Dual-Role Device
Three High-Speed USB 2.0 Dual-Role Devices
Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD^®/SDIO)
PCI Express^® 3.0 Subsystems with Two 5-Gbps Lanes
- One 2-Lane Gen2-Compliant Port
- or Two 1-Lane Gen2-Compliant Ports
Up to Two Controller Area Network (DCAN) Modules
- CAN 2.0B Protocol
Modular Controller Area Network (MCAN) Module
- CAN 2.0B Protocol with Available FD (Flexible Data Rate) Functionality
Up to 247 General-Purpose I/O (GPIO) Pins
Real-Time Clock Subsystem (RTCSS)
Device Security Features
- Hardware Crypto Accelerators and DMA
- Firewalls
- JTAG^® Lock
- Secure Keys
- Secure ROM and Boot
- Customer Programmable Keys and OTP Data
Power, Reset, and Clock Management
On-Chip Debug with CTools Technology
28-nm CMOS Technology
23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABZ)

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.