SPRUIN7C March 2020 – March 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1
The watchdog can be configured in the SCSR register to either reset the device (WDRST) or assert an interrupt (WDINT), if the watchdog counter reaches the maximum value. The behavior of each condition is:
If the watchdog is configured to reset the device, then the WDRST signal pulls the device reset (XRS) pin low for 512 INTOSC1 cycles when the watchdog counter reaches the maximum value.
When the watchdog counter expires, the counter asserts an interrupt by driving the WDINT signal low for 512 INTOSC1 cycles. The falling edge of WDINT triggers a WAKEINT interrupt in the PIE, if enabled. Because the PIE is edge-triggered, re-enabling the WAKEINT while WDINT is active does not produce a duplicate interrupt.
To avoid unexpected behavior, software must not change the configuration of the watchdog while WDINT is active. For example, changing from interrupt mode to reset mode while WDINT is active immediately resets the device. Disabling the watchdog while WDINT is active causes a duplicate interrupt if the watchdog is later re-enabled. If a debug reset is issued while WDINT is active, the reset cause register (RESC) shows a watchdog reset. The WDINTS bit in the SCSR register can be read to determine the current state of WDINT.