SPRUIN7C March 2020 – March 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1
The device has a watchdog timer that can optionally trigger a reset if the watchdog is not serviced by the CPU within a user-specified amount of time. This watchdog reset (WDRS) produces an XRS that lasts for 512 INTOSC1 cycles.
After a watchdog reset, the WDRSn and XRSn bits in RESC are set.