SPRUIN7C March 2020 – March 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1
Table 3-2 summarizes the various reset signals and the effect on the device.
Reset Source | CPU Core Reset (C28x, FPU, VCRC) | Peripherals Reset | JTAG/Debug Logic Reset | IOs | XRS Output |
---|---|---|---|---|---|
POR | Yes | Yes | Yes | Hi-Z | Yes |
BOR | Yes | Yes | Yes | Hi-Z | Yes |
XRS Pin | Yes | Yes | No | Hi-Z | - |
WDRS | Yes | Yes | No | Hi-Z | Yes |
NMIWDRS | Yes | Yes | No | Hi-Z | Yes |
SYSRS (DebuggeLOSr Reset) | Yes | Yes | No | Hi-Z | No |
SCCRESET | Yes | Yes | No | Hi-Z | No |
SIMRESET. XRS | Yes | Yes | No | Hi-Z | Yes |
SIMRESET. CPU1RS | Yes | Yes | No | Hi-Z | No |
HWBISTRS | Yes | No | No | No | No |
The resets can be divided into two groups:
After a reset, the reset cause register (RESC) is updated with the reset cause. The bits in this register maintain the state across multiple resets. The bits can only be cleared by a power-on reset (POR) or by writing ones to the RESCCLR register. Some bits are cleared by the boot ROM as part of the start-up routines.
Many peripheral modules have individual resets accessible through the SOFTPRESx registers. For information about a module's reset state, refer to the specific chapter for that module.
After any reset, the CPU begins execution from address 0x3FFFC0 (the reset vector), which is in the boot ROM. After running the boot ROM code, the CPU typically branches to the start of the Flash memory at address 0x80000. For more information on controlling the boot process, see Chapter 4.