SPRUIN7C March 2020 – March 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1
Table 3-169 lists the memory-mapped registers for the PERIPH_AC_REGS registers. All register offset addresses not listed in Table 3-169 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | ADCA_AC | ADCA Master Access Control Register | EALLOW | Go |
4h | ADCC_AC | ADCC Master Access Control Register | EALLOW | Go |
10h | CMPSS1_AC | CMPSS1 Master Access Control Register | EALLOW | Go |
12h | CMPSS2_AC | CMPSS2 Master Access Control Register | EALLOW | Go |
14h | CMPSS3_AC | CMPSS3 Master Access Control Register | EALLOW | Go |
16h | CMPSS4_AC | CMPSS4 Master Access Control Register | EALLOW | Go |
48h | EPWM1_AC | EPWM1 Master Access Control Register | EALLOW | Go |
4Ah | EPWM2_AC | EPWM2 Master Access Control Register | EALLOW | Go |
4Ch | EPWM3_AC | EPWM3 Master Access Control Register | EALLOW | Go |
4Eh | EPWM4_AC | EPWM4 Master Access Control Register | EALLOW | Go |
50h | EPWM5_AC | EPWM5 Master Access Control Register | EALLOW | Go |
52h | EPWM6_AC | EPWM6 Master Access Control Register | EALLOW | Go |
54h | EPWM7_AC | EPWM7 Master Access Control Register | EALLOW | Go |
70h | EQEP1_AC | EQEP1 Master Access Control Register | EALLOW | Go |
72h | EQEP2_AC | EQEP2 Master Access Control Register | EALLOW | Go |
80h | ECAP1_AC | ECAP1 Master Access Control Register | EALLOW | Go |
82h | ECAP2_AC | ECAP2 Master Access Control Register | EALLOW | Go |
84h | ECAP3_AC | ECAP3 Master Access Control Register | EALLOW | Go |
B0h | CLB1_AC | CLB1 Master Access Control Register | EALLOW | Go |
B2h | CLB2_AC | CLB2 Master Access Control Register | EALLOW | Go |
100h | SCIA_AC | SCIA Master Access Control Register | EALLOW | Go |
110h | SPIA_AC | SPIA Master Access Control Register | EALLOW | Go |
112h | SPIB_AC | SPIB Master Access Control Register | EALLOW | Go |
120h | I2CA_AC | I2CA Master Access Control Register | EALLOW | Go |
122h | I2CB_AC | I2CB Master Access Control Register | EALLOW | Go |
130h | PMBUS_A_AC | PMBUSA Master Access Control Register | EALLOW | Go |
138h | LIN_A_AC | LINA Master Access Control Register | EALLOW | Go |
13Ah | LIN_B_AC | LINB Master Access Control Register | EALLOW | Go |
140h | DCANA_AC | DCANA Master Access Control Register | EALLOW | Go |
158h | FSIATX_AC | FSIA Master Access Control Register | EALLOW | Go |
15Ah | FSIARX_AC | FSIB Master Access Control Register | EALLOW | Go |
1AAh | HRPWM_A_AC | HRPWM Master Access Control Register | EALLOW | Go |
1ACh | HIC_A_AC | HIC Master Access Control Register | EALLOW | Go |
1FEh | PERIPH_AC_LOCK | Lock Register to stop Write access to peripheral Access register. | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-170 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
ADCA_AC is shown in Figure 3-146 and described in Table 3-171.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ADCC_AC is shown in Figure 3-147 and described in Table 3-172.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CMPSS1_AC is shown in Figure 3-148 and described in Table 3-173.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CMPSS2_AC is shown in Figure 3-149 and described in Table 3-174.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CMPSS3_AC is shown in Figure 3-150 and described in Table 3-175.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CMPSS4_AC is shown in Figure 3-151 and described in Table 3-176.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM1_AC is shown in Figure 3-152 and described in Table 3-177.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM2_AC is shown in Figure 3-153 and described in Table 3-178.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM3_AC is shown in Figure 3-154 and described in Table 3-179.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM4_AC is shown in Figure 3-155 and described in Table 3-180.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM5_AC is shown in Figure 3-156 and described in Table 3-181.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM6_AC is shown in Figure 3-157 and described in Table 3-182.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM7_AC is shown in Figure 3-158 and described in Table 3-183.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EQEP1_AC is shown in Figure 3-159 and described in Table 3-184.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EQEP2_AC is shown in Figure 3-160 and described in Table 3-185.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ECAP1_AC is shown in Figure 3-161 and described in Table 3-186.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ECAP2_AC is shown in Figure 3-162 and described in Table 3-187.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ECAP3_AC is shown in Figure 3-163 and described in Table 3-188.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CLB1_AC is shown in Figure 3-164 and described in Table 3-189.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACCRESERVED | RESERVED | RESERVED | CPU1_ACCRESERVED | ||||
R/W-3hR/W-3h | R/W-3h | R/W-3h | R/W-3hR/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | RESERVED | R/W | 3h | Reserved |
CLB2_AC is shown in Figure 3-165 and described in Table 3-190.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACCRESERVED | RESERVED | RESERVED | CPU1_ACCRESERVED | ||||
R/W-3hR/W-3h | R/W-3h | R/W-3h | R/W-3hR/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | RESERVED | R/W | 3h | Reserved |
SCIA_AC is shown in Figure 3-166 and described in Table 3-191.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R-0-0h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | RESERVED | R-0 | 0h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
SPIA_AC is shown in Figure 3-167 and described in Table 3-192.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
SPIB_AC is shown in Figure 3-168 and described in Table 3-193.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
I2CA_AC is shown in Figure 3-169 and described in Table 3-194.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R-0-0h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | RESERVED | R-0 | 0h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
I2CB_AC is shown in Figure 3-170 and described in Table 3-195.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R-0-0h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | RESERVED | R-0 | 0h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
PMBUS_A_AC is shown in Figure 3-171 and described in Table 3-196.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
LIN_A_AC is shown in Figure 3-172 and described in Table 3-197.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
LIN_B_AC is shown in Figure 3-173 and described in Table 3-198.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
DCANA_AC is shown in Figure 3-174 and described in Table 3-199.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
FSIATX_AC is shown in Figure 3-175 and described in Table 3-200.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
FSIARX_AC is shown in Figure 3-176 and described in Table 3-201.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
HRPWM_A_AC is shown in Figure 3-177 and described in Table 3-202.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
HIC_A_AC is shown in Figure 3-178 and described in Table 3-203.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
PERIPH_AC_LOCK is shown in Figure 3-179 and described in Table 3-204.
Return to the Summary Table.
Based on status bit control the Access registers are either RD/WR or RD only.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_AC_WR | ||||||
R-0-0h | R/WSonce-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R-0 | 0h | Reserved |
0 | LOCK_AC_WR | R/WSonce | 0h | Defines Access control definition for the CPU1 as: 1: Access Control registers are Read Only 0: Read/Write Access allowed to Access Control registers. Writing '1' sets the bit, writing '0' has no effect. Reset type: SYSRSn |