Once the application requirements are understood,
a specific clock configuration can be determined. The default configuration is for
INTOSC2 to be used as the system clock (PLLSYSCLK) with a divider of 1. The
following procedure must be used to set up the desired application
configuration:
Refer to your device SysCtl_setClock() function inside C2000Ware installation for an example.
Recommended sequence to set up the system PLL:
- Bypass the PLL by clearing SYSPLLCTL1[PLLCLKEN].
Allow at least 60 NOP instructions for this to take effect.
- Power down the PLL by writing to SYSPLLCTL1.PLLEN = 0 and allow at least 60 NOP
instructions for this to take effect.
- Select the reference clock source (OSCCLK) by writing to
CLKSRCCTL1.OSCCLKSRCSEL. Allow at least 300 NOP instructions for this to take
effect.
- Set the system clock divider to /1 to make sure
the fastest PLL configuration by clearing SYSCLKDIVSEL[ PLLSYSCLKDIV].
- Set the IMULT, REFDIV, and ODIV simultaneously by
writing a 32-bit value in SYSPLLMULT at once. This automatically enables the
PLL. Be sure the settings for multiplier and dividers do not violate the
frequency specifications as defined in the TMS320F28002x Real-Time
Microcontrollers Data Sheet.
- Wait for PLL to lock by polling for the lock
status bit to go high, that is, SYSPLLSTS.LOCKS = 1
- Configure DCC with reference clock as OSCCLK and clock under measurement as
PLLRAWCLK, and verify the frequency of the PLL. If the frequency is out of
range, do not enable PLLRAWCLK as SYSCLK, stop here and troubleshoot. Refer to
Chapter 6 for more information on the configuration and usage.
- Switch to the PLL as the system clock by setting SYSPLLCTL1[PLLCLKEN].
Note: - SYSPLL must be bypassed and powered down manually before changing the OSCCLK source.
- At least 60 CPU clock cycles delay is needed after bypassing PLL, that is,
SYSPLLCTL1.PLLCLKEN = 0.
- At least 60 CPU clock cycles delay is needed after PLL is powered down, that
is, SYSPLLCTL1.PLLEN = 0.
- At least 300 CPU clock cycles delay is needed after OSSCLK source is changed.
- PLL SLIP bit is not supported. The DCC must be used to check the validity of
the PLL clock. This feature is included as part of SysCtl_setClock()
function inside C2000Ware.